CN107589368A - EPC3C120F484 types FPGA configurations/test/debugging adapter - Google Patents
EPC3C120F484 types FPGA configurations/test/debugging adapter Download PDFInfo
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- CN107589368A CN107589368A CN201710735136.0A CN201710735136A CN107589368A CN 107589368 A CN107589368 A CN 107589368A CN 201710735136 A CN201710735136 A CN 201710735136A CN 107589368 A CN107589368 A CN 107589368A
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Abstract
A kind of EPC3C120F484 types FPGA configurations/test/debugging adapter disclosed by the invention, it is desirable to provide a kind of easy to operate, operating efficiency is high, and mass loss is small, test result accurately and reliably FPGA LSI testings and debugging adapter.The technical scheme is that：Configuration mode selection circuit (2), interface circuit (3), power circuit (4), status display circuit (5) and storage configuration circuit (6) electrically connect around test jack (1).The functional configuration file of FPGA large scale integrated circuits is pre-stored with storage configuration circuit, the online device under test of power circuit is powered up, configuration mode selection circuit is according to main string configuration mode, logic function configuration is carried out by interface circuit option and installment interface device under test, verify whether the configuration of device under test is normal by status display circuit indicator lamp, function, performance test can be carried out by automatic test machine ATE after the completion of logic function configuration.
Description
Technical field
The invention mainly relates to a kind of large scale integrated circuit (LSIC) EPC3C120F484 type field programmable gate arrays
(FPGA) configure, test and debugging adapter.
Background technology
With the development of science and technology, the raising that integrated circuit production technology is horizontal, the integrated level of digital circuit is increasing, from
(SSIC), middle scale (MSIC), large scale integrated circuit (LSIC) develop into super large-scale integration (VLSIC) on a small scale,
Kind is also more and more.Wherein, on-site programmable gate array FPGA device has become half of most rich attraction in the world today
Conductor device.Due to FPGA device small volume, integrated level is high, low in energy consumption, speed is fast, the advantages that can programming repeatedly infinitely,
User not only can go out various dedicated IC chips by designed, designed in a short time by means of development system, can also facilitate
Emulated on computers and real-time simulation, pinpoint the problems in time, adjustment circuit, improved design project.So FPGA devices
Part has become the preferred device of product development and miniaturization, and more and more important angle is play in modern electronic system design
Color, it is widely used in the numerous areas such as Aeronautics and Astronautics, communication, internet and auto industry.With extensively should for FPGA
With, the requirement to its reliability also becomes more and more higher, therefore in order to ensure the core devices quality of system, to FPGA device
Fault detection and diagnosis method design for Measurability and various measuring technologies, which carry out comprehensive in-depth study, has important reality meaning
Justice.Test is the link that expense highest difficulty is maximum in design, testing expense can account for the 50% of chip manufacturing cost with
On.Increasing influence will be had to the Time To Market of product, construction cycle by testing, and as restricting FPGA practical applications
One key factor.
Need that FPGA first is configured into the circuit with specific function due to FPGA programmability, during test, then it is right
FPGA applies corresponding vector.So it can just complete to survey to cover all resources inside FPGA by repeated multiple times different configuration
Examination.FPGA test can be divided into two major classes according to test needs:
1. the test process of Facing to Manufacturing
The test process of Facing to Manufacturing is the test for manufacturing angle, is needed in manufacturing process to the complete tests of FPGA, its
Testing cost mainly determined by the whole testing time, therefore, how to be reduced on the premise of test coverage is ensured test to
Quantity set length and setup time are the crucial considerations of test.
2. application oriented test process
Application oriented test process is the test on application layer, that is, the particular electrical circuit that FPGA is configured to use is entered
Row test.Application oriented test process has very strong specific aim, is usually used in FPGA and has specific characteristics the application field that can be required.No
Pipe is the test process of Facing to Manufacturing or application oriented test process, and its test process is all a configuration device, is applied
The process of test vector.It is the test based on ATE (ATE) to carry out the most of test to FPGA now, is being surveyed
It is required for using during examination both with FPGA device being connected, the hardware circuit being connected again with ATE machines both adapter.Due to FPGA
The complexity of this body structure, currently for the configuration, test and debugging of FPGA large scale integrated circuits, the discrete much all used
Adapter, i.e., a kind of technical need correspond to a set of special fixture.This not only adds manufacturing cost, extends production week
Phase, and complex operation is caused, extended time consumption, and cause device to wear because frequently changing frock clamp.
The content of the invention
The purpose of the present invention is in place of above-mentioned the shortcomings of the prior art, there is provided a kind of easy to operate, work effect
Rate is high, and mass loss is small, test result accurately and reliably FPGA LSI testings and debugging adapter.
The above-mentioned purpose of the present invention can be reached by following measures, and a kind of EPC3C120F484 types FPGA configurations are surveyed
Examination/debugging adapter, including：Around the configuration mode selection circuit (2) of test jack (1) electrical connection, interface circuit (3), electricity
Source circuit (4), status display circuit (5) and storage configuration circuit (6), it is characterised in that：It is pre-stored in storage configuration circuit (6)
There is the functional configuration file of FPGA large scale integrated circuits, the online device under test of power circuit (4) is powered up, configuration mode
Selection circuit (2) is programmed data according to main string configuration mode by interface circuit (3) option and installment interface device under test
Configuration, verify whether the configuration of device under test is normal by status display circuit (5) indicator lamp, after the completion of programming data configuration i.e.
Function, performance test can be carried out by automatic test machine (ATE).
The present invention has the advantages that compared to prior art.
Easy to operate, operating efficiency is high, and mass loss is small.The present invention is on the memory in storage configuration circuit (6), in advance
The configuration file of device under test is stored, device under test is installed in test jack (1), according to the pattern being pre-designed, chosen
Configuration mode (2), normal power-up is carried out to power circuit (4), by interface circuit (3) option and installment interface directly to device to be measured
Part is configured, you can device under test is configured, and its state can be characterized by status display circuit (5).Device to be measured
It after part is configured, can be connected with ATE, complete function and the performance test of device under test.It is real on one piece of test adapter
Clamping is carried out to FPGA large scale integrated circuits to be measured under present non-solder state.Device under test is freely installed, with peace with taking,
Not only processing cost is low, easy to operate, drastically increases operating efficiency, and reduces caused by frequently changing frock clamp
Device wears and the operating time；FPGA to be measured working condition is preferably observed by status display circuit (5) indicator lamp, can
To verify whether the configuration of FPGA device is normal,.Solves a device multiple technologies demand, making originally will be in three adapter
On realize EPC3C120F484 type FPGA large scale integrated circuits configuration function, can complete three with a frock clamp
The target of kind functional requirement.
The present invention realizes a kind of frock clamp and can complete to configure, test target with three kinds of functions of debugging.It can use
In large scale integrated circuit EPC3C120F484 types FPGA unified collocation, test and debugging.
Brief description of the drawings
Fig. 1 is the line construction schematic diagram of EPC3C120F484 types FPGA configurations/test/debugging adapter of the present invention.
Embodiment
Refering to Fig. 1.In embodiment described below, a kind of EPC3C120F484 types FPGA configuration testings/debugging adaptation
Device, including：Around the configuration mode selection circuit (2) of test jack (1) electrical connection, interface circuit (3), power circuit (4), shape
State display circuit (5) and storage configuration circuit (6).Storage configuration circuit is pre-stored with FPGA large scale integrated circuits in (6)
Logic function configuration file, the online device under test of power circuit (4) are powered up, and configuration mode selection circuit (2) is according to pre-
The main string configuration mode first set, logic function configuration is carried out by interface circuit (3) option and installment interface device under test, led to
Whether normal cross the configuration of status display circuit (5) indicator lamp checking device under test, can pass through after the completion of logic function configuration
ATE machines carry out logic function, performance test.
Test jack (1) is a 484 core sockets, and include MSEL0, MSEL1, MSEL2, MSEL3 of 484 core sockets match somebody with somebody
It is defeated to put pattern, boundary scan clock TCK, boundary scan data output TDO, boundary scan model selection TMS, boundary scan data
Enter TDI, configuration status signal nSTATUS, configuration end signal CONF-DONE, configuration initial signal nCONFIG, enabled input
NCE, data input DATA, clock output DCLK, enabled output nCSO, serial data output ASDO port pinouts, wherein, configuration
Status signal nSTATUS, configuration end signal CONF-DONE, configuration initial signal nCONFIG pins pass through resistance R1, resistance
R2 and resistance R3 electrical connection 3.3V power supplys.EPC3C120F484FPGA device pins to be measured are according to device under test upper left corner flag
The upper left position installation of corresponding 484 core sockets is put, after the alignment of direction, 484 pins of device under test are just arranged on 484 cores and surveyed
Socket (1) is tried, so as to ensure that device pin defines, assurance function and performance test consistent with the pin definitions of socket.
Configuration mode selection circuit (2) is electrically connected by line with MSEL0~MSEL4 pins of test mounting receptacle (1),
FPGA configuration mode is determined by the level on MSEL0~MSEL4 pins, as MSEL0~MSEL4 pin level is
(0100) be then main string pattern, MSEL0~MSEL4 pin level be (0011) be then from string pattern, MSEL0~MSEL4's
Pin level is that (0000) is then JTAG mode, and different configuration modes represents that FPGA device loads programming number in a different manner
According to device under test.The present invention can realize different configuration modes by wire jumper.
First interface circuit (3) JTAG sockets are provided with 10 core sockets, and resistance R5, electricity are parallel with respectively in JTAG socket pins
TCK, TDO, TMS and TDI pin of R6 and grounding resistance R7, JTAG socket by the connected test jack (1) of above-mentioned line are hindered, from
And realize and download programming data.When host computer connects JTAG sockets by downloading wire, logic function configurator is written to
It can carry out the work such as debugging inside FPGA, program just disappears after power-off.
Second interface circuit (3) AS sockets are provided with 10 core sockets, AS socket pins respectively the DATA with test jack (1),
DCLK, nCSO, ASDO, CONF-DONE, nCONFIG pin electrically connect, and AS sockets are parallel with resistance R4 and test jack (1) nCE
It is connected.When host computer connects AS sockets by downloading wire, programming data is written to FLASH, and the programming data in FLASH is disconnected
It will not be disappeared after electricity.
Power circuit (4) is provided with three voltage-stablizers of 5v power supplys power supply, is exported respectively accordingly by three voltage-stablizers
3.3V, 2.5V, 1.2V voltage, the 3.3V being connected to test jack (1), 2.5V, 1.2V pin powereds, voltage are respectively supplied to
The circuit powered is needed inside FPGA.
Status display circuit (5) includes three-line, series connection light emitting diode D1, resistance R12 and series connection light emitting diode
D2, resistance R13 line electricity connecting test socket (1) CONF-DONE, nCONFIG, the other end is connected with 3.3V power supplys；String
Join light emitting diode D3, resistance R14, the nCE of electrical connection test jack (1), other end ground connection.Status display circuit (5) passes through
Three light emitting diodes indicate, judge whether the download state of FPGA device and stress state are working properly.
Storage configuration circuit (6) includes two FLASH chips of IC2, IC3, and IC2 chip DATA, DCLK pins are electrically connected with
Resistance R8, resistance R9 are electrically connected with resistance R10 with IC3 chip DATA, DCLK pins, resistance R11 is carried out and is coupled, and electrical connection is surveyed
Try DATA, DCLK of socket (1)；NCSO, ASDO after IC2, IC3 chip nCS, ASDI pins in parallel with test jack (1) draw
Pin is electrically connected, and storage configuration circuit (6) IC2, IC3 chip power pin is connected by switching SW1 with power supply.Pass through manual control
SW1 is switched, when optional IC2 or IC3 connects AS sockets as host computer by downloading wire, downloads the storage core of programming data
Piece, then control the storage chip that logic function configurator is written in fpga chip after being worked on power by FPGA to be measured, from
And the chip is possessed certain logic function, and then coordinate ATE machines to carry out function, performance test.
Claims (10)
1. a kind of EPC3C120F484 types FPGA configuration testings/debugging adapter, including：Around test jack (1) electrical connection
Configuration mode selection circuit (2), interface circuit (3), power circuit (4), status display circuit (5) and storage configuration circuit (6),
It is characterized in that：The functional configuration file of FPGA large scale integrated circuits, power circuit are pre-stored with storage configuration circuit (6)
(4) online device under test is powered up, and configuration mode selection circuit (2) passes through interface circuit (3) according to main string configuration mode
Option and installment interface device under test carries out logic function configuration, and the configuration of device under test is verified by status display circuit (5)
It is whether normal, logic function, performance test can be carried out by automatic test machine ATE after the completion of logic function configuration.
2. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：Test
Socket (1) is a 484 core sockets, and 484 core sockets include MSEL0, MSEL1, MSEL2, MSEL3 configuration mode, border
Scan clock TCK, boundary scan data output TDO, boundary scan model selection TMS, boundary scan data input TDI, configuration
Status signal nSTATUS, configuration end signal CONF-DONE, configuration initial signal nCONFIG, enabled input nCE, data are defeated
Enter DATA, clock output DCLK, enabled output nCSO, serial data output ASDO port pinouts, wherein, configuration status signal
NSTATUS, configuration end signal CONF-DONE, configuration initial signal nCONFIG pins pass through resistance R1, resistance R2 and resistance
R3 electrically connects 3.3V power supplys.
3. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：Configuration
Mode selection circuit (2) is electrically connected by line with MSEL0~MSEL4 pins of test mounting receptacle (1), FPGA configuration mould
Formula is determined by the level on MSEL0~MSEL4 pins, and different configuration modes is realized by wire jumper.
4. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：First
Interface circuit (3) JTAG sockets are provided with 10 core sockets, are parallel with resistance R5, resistance R6 and ground connection electricity in JTAG socket pins respectively
R7 is hindered, JTAG sockets are compiled by TCK, TDO, TMS and TDI pin of the connected test jack (1) of above-mentioned line so as to realize to download
Number of passes evidence.
5. second interface circuit (3) AS sockets are provided with 10 core sockets, AS socket pins respectively the DATA with test jack (1),
DCLK, nCSO, ASDO, CONF-DONE, nCONFIG pin electrically connect, and AS sockets are parallel with resistance R4 and test jack (1) nCE
It is connected.
6. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：Power supply
Circuit (4) is provided with three voltage-stablizers of 5v power supplys power supply, and corresponding 3.3V, 2.5V, 1.2V are exported respectively by three voltage-stablizers
Voltage, the 3.3V being connected to test jack (1), 2.5V, 1.2V pin powereds, voltage is respectively supplied to need to supply inside FPGA
The circuit of electricity.
7. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：State
Display circuit (5) includes three-line, series connection light emitting diode D1, resistance R12 and series connection light emitting diode D2, resistance R13
CONF-DONE, nCONFIG of line electricity connecting test socket (1), the other end are connected with 3.3V power supplys；Series connection light emitting diode
D3, resistance R14, the nCE of electrical connection test jack (1), other end ground connection.
8. status display circuit (5) is indicated by three light emitting diodes, the download state and loading shape of FPGA device are judged
Whether state is working properly.
9. EPC3C120F484 types FPGA configuration testings/debugging adapter as claimed in claim 1, it is characterised in that：Storage
Configuration circuit (6) includes two FLASH chips of IC2, IC3, and IC2 chip DATA, DCLK pins are electrically connected with resistance R8, resistance R9
With IC3 chip DATA, DCLK pins it is electrically connected with resistance R10, resistance R11 is carried out and is coupled, electrical connection test jack (1)
DATA、DCLK；NCSO, ASDO pin after IC2, IC3 chip nCS, ASDI pins in parallel with test jack (1) is electrically connected, and deposits
Storage configuration circuit (6) IC2, IC3 chip power pin is connected by switching SW1 with power supply.
10. SW1 is switched by manual control, when optional IC2 or IC3 connects AS sockets as host computer by downloading wire, under
The storage chip of programming data is carried, then controls the storage chip to write logic function configurator after being worked on power by FPGA to be measured
Enter into fpga chip, so that the chip possesses certain logic function, and then coordinate ATE machines to carry out function, performance test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710735136.0A CN107589368A (en) | 2017-08-24 | 2017-08-24 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
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|---|---|---|---|
| CN201710735136.0A CN107589368A (en) | 2017-08-24 | 2017-08-24 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109164278A (en) * | 2018-10-25 | 2019-01-08 | 江苏七维测试技术有限公司 | A kind of DTS1000 test adaptor box and its test method |
| CN109766292A (en) * | 2019-01-23 | 2019-05-17 | 济南浪潮高新科技投资发展有限公司 | A kind of jtag interface multiplexing functions circuit |
| CN114003550A (en) * | 2021-11-01 | 2022-02-01 | 北京中科胜芯科技有限公司 | FPGA configuration device in JTAG mode |
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