CN109766292A - A kind of jtag interface multiplexing functions circuit - Google Patents
A kind of jtag interface multiplexing functions circuit Download PDFInfo
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- CN109766292A CN109766292A CN201910062461.4A CN201910062461A CN109766292A CN 109766292 A CN109766292 A CN 109766292A CN 201910062461 A CN201910062461 A CN 201910062461A CN 109766292 A CN109766292 A CN 109766292A
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- jtag
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Abstract
The present invention is more particularly directed to a kind of jtag interface multiplexing functions circuits.The jtag interface multiplexing functions circuit, including power module, the chip with jtag interface, toggle switch and two contact pin pedestals；The power module is connected to the chip with jtag interface, powers for circuit；The toggle switch has the chip and two contact pin pedestals of jtag interface by data/address bus connection respectively, and the chip signal with jtag interface is respectively connected to two contact pin pedestals.The jtag interface multiplexing functions circuit, structure is simple, and improvement cost is low, has wide range of applications, and can realize jtag boundary scanning and avoid the program burn writing quality problems generated due to signal bifurcated while programming function.
Description
Technical field
The present invention relates to jtag circuit design field, in particular to a kind of jtag interface multiplexing functions circuit.
Background technique
In recent years, electronic information technology rapidly develops, and plays in for daily life more and more important
Effect, brings great convenience for daily life.With the fast development of electronic information technology, common electronics core
Piece is unable to satisfy demand at this stage already, and integrated electronic chip becomes mainstream gradually.However, integrated electronic chip not only makes core
Piece function is stronger and stronger, simultaneously as the Integration Design of electronic chip and processing technology but also electronic chip integrated level
It is higher and higher with complexity.
JTAG(Joint Test Action Group；Combined testing action group) it is a kind of international standard test protocol
(IEEE1149.1 is compatible) is mainly used for chip interior test.Now most high-grade devices all support JTAG protocol, as DSP,
FPGA device etc..
Usually said JTAG is substantially divided to two classes, and one kind is for testing whether the electrical characteristic of chip, detection chip ask
Topic；One kind is used for Debug, all contains the two modules in the general CPU for supporting JTAG.
One CPU containing JTAG Debug interface module, as long as clock is normal, so that it may be accessed by jtag interface
The internal register of CPU and hang over the equipment on cpu bus, such as FLASH, RAM, SOC (such as 4510B, 44Box, AT91M system
Column) built-in module register, as UART, the register of Timers, GPIO etc..
The jtag interface of standard is 4 lines: TMS, TCK, TDI, TDO, and respectively model selection, clock, data input sum number
According to output line.There is following JTAG pin to define with JTAG mouthfuls of chips:
TCK --- test clock input；
TDI --- test data input, data input JTAG mouthfuls by TDI；
TDO --- test data output, data are exported by TDO from JTAG mouthfuls；
TMS --- test pattern selection, TMS are used to be arranged JTAG mouthfuls in certain specific test pattern.
Optional pin TRST --- test reset, input pin, low level are effective.
JTAG is initially for being tested chip, and the basic principle of JTAG is to define a TAP in device inside
(Test Access Port；Test access mouth) internal node is tested by dedicated jtag test tool.JTAG is surveyed
Examination allows multiple devices to be cascaded by jtag interface, forms a JTAG chain, is able to achieve and is tested respectively each device.
The hardware of multiple devices connects into daisy chain structure, and the device of connection jtag interface TDO is first in daisy chain
A device, the device of connection jtag interface TDI are the last one device in daisy chain.The TDI and the latter of previous device
The TDO of device links together, and TMS, the tck signal of all ARM devices link together in daisy chain.By JTAG chain, just
It can be seen that simulated which pin of chip is abnormal, different simulation documents can be loaded, tests I/O pin, DDR connection,
Nand flash connection etc..
Chip type containing JTAG mouthfuls is more, such as CPU, DSP, CPLD.
There are a state machine, referred to as TAP controller inside JTAG.The state machine of TAP controller is carried out by TCK and TMS
The input of data and instruction is realized in the change of state.
JTAG standard defines a serial shift register.Each unit of register distributes to the phase of IC chip
Pin is answered, each independent unit is known as BSC (Boundary-Scan Cell) boundary scan cell.This concatenated BSC
In the circuit IC Inner Constitution JTAG, all BSR (Boundary-Scan Register) boundary scan register passes through JTAG
Test activation, usually these pins keep normal IC function.
Two scan chain table buffer areas of JTAG programming program maintenance, a corresponding input, a corresponding output.One scanning
Chain buffer area is exactly an int type integer array, and the pin (PIN) that the length of array is CPU counts, each element pair in array
Answer the state of a pin.There are two types of the states of one pin: 0 or 1 in fact can describe both shapes with 1
State, and described to waste very much with an int integer in program.Input scan chain table array is used to save just from CPU scan
The state of each pin out, and export scan chain table array and be used to save by scanning to the state in the pin of CPU.
Flash chip must be wiped by flash chip programming first, write operation then is carried out to it again.Wipe flash
Chip can sector erasing one by one, can also once wipe entire chip, carrying out erasable timing and order to flash chip can
To check the datasheet of specific flash chip model.
By simple JTAG cable read and write flash chip data must byte-by-byte be written and read, operating process all very classes
Seemingly, for reading flash, operating process is as follows:
1) safe condition of each pin of CPU is written in output scan chain table array；
2) by " SAMPLE " command scan(ning) into the TAP controller of CPU；
3) status scan in scan chain table array will be exported into the TAP controller of CPU；
4) again by " SAMPLE " command scan(ning) into the TAP controller of CPU；
5) by " EXTEST " command scan(ning) into the TAP controller of CPU；
6) it executes for circulation byte-by-byte and reads data, cycle-index is equal to the data length to be read: will first read
Flash address the corresponding element of address pins state write-in output scan chain table array in, then will export scan chain
The state synchronized of CPU pin is input to input at the same time and swept by the status scan in table array into the TAP controller of CPU
It retouches in linked list array, then extracts flash data from input linked list array.
When chip jtag interface simultaneously connect debugging interface and boundary scan interface when, often because JTAG signal bifurcated and
Programming program singal quality is set to go wrong.
Based on the above situation, the invention proposes a kind of jtag interface multiplexing functions circuits.
Summary of the invention
In order to compensate for the shortcomings of the prior art, the present invention provides a kind of jtag interface multiplexing functions electricity being simple and efficient
Road.
The present invention is achieved through the following technical solutions:
A kind of jtag interface multiplexing functions circuit, it is characterised in that: including power module, the chip with jtag interface,
Toggle switch and two contact pin pedestals；The power module is connected to the chip with jtag interface, powers for circuit；Described group
Code switch has the chip and two contact pin pedestals of jtag interface by data/address bus connection respectively, by the core with jtag interface
Piece signal is respectively connected to two contact pin pedestals.
The pin TRST/TMS/TCK/TDI/TDO signal of the chip with jtag interface is branched into two-way respectively,
Obtain two groups of JTAG signals；Two groups of JTAG signals are connected with toggle switch one end pin respectively, and are respectively connected to two contact pin bottoms
Seat.
Two contact pin pedestals are separately connected fever writes and tester.
In two groups of JTAG signals that the chip with jtag interface is separated, first group of JTAG signal and toggle switch
One end pin is connected, and fever writes are connected to toggle switch other end pin by the pin of corresponding contact pin pedestal.
When the toggle switch controls first group of JTAG signal connection, when second group of JTAG signal disconnects, JTAG programming function
It can open, fever writes can pass through corresponding contact pin pedestal burning program into the chip with jtag interface.
In two groups of JTAG signals that the chip with jtag interface is separated, second group of JTAG signal and toggle switch
One end pin is connected, and tester is connected to toggle switch other end pin by the pin of corresponding contact pin pedestal.
It is disconnected when the toggle switch controls first group of JTAG signal, when second group of JTAG signal connection, tester can be with
Jtag boundary scanning function is realized by corresponding contact pin pedestal.
The power module is connected to the power pins of the chip with jtag interface.
The beneficial effects of the present invention are: the jtag interface multiplexing functions circuit, structure is simple, and improvement cost is low, using model
It encloses extensively, can realize jtag boundary scanning and avoid the program burn writing matter generated due to signal bifurcated while programming function
Amount problem.
Detailed description of the invention
Attached drawing 1 is jtag interface multiplexing functions circuit diagram of the present invention.
Specific embodiment
In order to which technical problems, technical solutions and advantages to be solved are more clearly understood, tie below
Drawings and examples are closed, the present invention will be described in detail.It should be noted that specific embodiment described herein is only used
To explain the present invention, it is not intended to limit the present invention.
The jtag interface multiplexing functions circuit, including power module, the chip with jtag interface, toggle switch and two
Contact pin pedestal；The power module is connected to the chip with jtag interface, powers for circuit；The toggle switch passes through respectively
Data/address bus connection has the chip and two contact pin pedestals of jtag interface, and the chip signal with jtag interface is respectively connected to
Two contact pin pedestals.
The pin TRST/TMS/TCK/TDI/TDO signal of the chip with jtag interface is branched into two-way respectively,
Obtain two groups of JTAG signals；Two groups of JTAG signals are connected with toggle switch one end pin respectively, and are respectively connected to two contact pin bottoms
Seat.
Two contact pin pedestals are separately connected fever writes and tester.
In two groups of JTAG signals that the chip with jtag interface is separated, first group of JTAG signal and toggle switch
One end pin is connected, and fever writes are connected to toggle switch other end pin by the pin of corresponding contact pin pedestal.
When the toggle switch controls first group of JTAG signal connection, when second group of JTAG signal disconnects, JTAG programming function
It can open, fever writes can pass through corresponding contact pin pedestal burning program into the chip with jtag interface.
In two groups of JTAG signals that the chip with jtag interface is separated, second group of JTAG signal and toggle switch
One end pin is connected, and tester is connected to toggle switch other end pin by the pin of corresponding contact pin pedestal.
It is disconnected when the toggle switch controls first group of JTAG signal, when second group of JTAG signal connection, tester can be with
Jtag boundary scanning function is realized by corresponding contact pin pedestal.
The power module is connected to the power pins of the chip with jtag interface.
The jtag interface multiplexing functions circuit, structure is simple, and improvement cost is low, has wide range of applications, and can realize
The program burn writing quality problems generated due to signal bifurcated are avoided while jtag boundary scanning and programming function.
Claims (8)
1. a kind of jtag interface multiplexing functions circuit, it is characterised in that: including power module, the chip with jtag interface is dialled
Code switch and two contact pin pedestals；The power module is connected to the chip with jtag interface, powers for circuit；The dial-up
Switch has the chip and two contact pin pedestals of jtag interface by data/address bus connection respectively, by the chip with jtag interface
Signal is respectively connected to two contact pin pedestals.
2. jtag interface multiplexing functions circuit according to claim 1, it is characterised in that: by described with jtag interface
The pin TRST/TMS/TCK/TDI/TDO signal of chip is branched into two-way respectively, obtains two groups of JTAG signals；Two groups of JTAG letters
Number it is connected respectively with toggle switch one end pin, and is respectively connected to two contact pin pedestals.
3. jtag interface multiplexing functions circuit according to claim 1 or 2, it is characterised in that: two contact pin pedestal difference
Connect fever writes and tester.
4. jtag interface multiplexing functions circuit according to claim 3, it is characterised in that: by described with jtag interface
In two groups of JTAG signals that chip separates, first group of JTAG signal is connected with toggle switch one end pin, and fever writes pass through correspondence
The pin of contact pin pedestal be connected to toggle switch other end pin.
5. jtag interface multiplexing functions circuit according to claim 4, it is characterised in that: when toggle switch control the
One group of JTAG signal connection, when second group of JTAG signal disconnects, JTAG programming function is opened, and fever writes can be inserted by corresponding
Needle pedestal burning program into the chip with jtag interface.
6. jtag interface multiplexing functions circuit according to claim 3, it is characterised in that: by described with jtag interface
In two groups of JTAG signals that chip separates, second group of JTAG signal is connected with toggle switch one end pin, and tester passes through correspondence
The pin of contact pin pedestal be connected to toggle switch other end pin.
7. jtag interface multiplexing functions circuit according to claim 6, it is characterised in that: when toggle switch control the
One group of JTAG signal disconnects, and when second group of JTAG signal connects, tester can pass through corresponding contact pin pedestal and realize the side JTAG
Boundary's scanning function.
8. the jtag interface multiplexing functions circuit according to claim 4 or 6, it is characterised in that: the power module connection
To the power pins of the chip with jtag interface.
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| CN201910062461.4A CN109766292A (en) | 2019-01-23 | 2019-01-23 | A kind of jtag interface multiplexing functions circuit |
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| CN201910062461.4A CN109766292A (en) | 2019-01-23 | 2019-01-23 | A kind of jtag interface multiplexing functions circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113687839A (en) * | 2021-08-24 | 2021-11-23 | 天津津航计算技术研究所 | On-board programming method of CPCI board card configuration chip based on PCI9054 |
Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1567213A (en) * | 2003-06-21 | 2005-01-19 | 华为技术有限公司 | Method for Loading FLASH using boundary scanning device |
| US7191265B1 (en) * | 2003-04-29 | 2007-03-13 | Cisco Technology, Inc. | JTAG and boundary scan automatic chain selection |
| US20070226558A1 (en) * | 2005-11-28 | 2007-09-27 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| CN101183139A (en) * | 2007-11-02 | 2008-05-21 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101464806A (en) * | 2008-12-29 | 2009-06-24 | 华为技术有限公司 | Method, apparatus and system for loading programmable logic device |
| CN101581759A (en) * | 2009-06-16 | 2009-11-18 | 华为技术有限公司 | JTAG switching interface, single board, JTAG interface conversion board and single board testing system |
| CN102929651A (en) * | 2012-09-21 | 2013-02-13 | 中国航空无线电电子研究所 | Chip-array-based on-line loading system and loading method thereof |
| CN102929194A (en) * | 2012-11-06 | 2013-02-13 | 长安大学 | Asynchronous multi-core programmable automation controller (PAC) |
| CN103440148A (en) * | 2013-08-27 | 2013-12-11 | 无锡泛太科技有限公司 | Device and method for programming multiple single-chip microcomputer programs |
| US20130346639A1 (en) * | 2012-06-21 | 2013-12-26 | Jonathan Stroud | Systems and methods for programming configurable logic devices via usb |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN105224372A (en) * | 2015-11-02 | 2016-01-06 | 积成电子股份有限公司 | The circuit of program operation and JTAG download program wire jumper free |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN207690065U (en) * | 2018-01-22 | 2018-08-03 | 济南浪潮高新科技投资发展有限公司 | It is a kind of based on FPGA can multy-way switching JTAG downloaders |
-
2019
- 2019-01-23 CN CN201910062461.4A patent/CN109766292A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7191265B1 (en) * | 2003-04-29 | 2007-03-13 | Cisco Technology, Inc. | JTAG and boundary scan automatic chain selection |
| CN1567213A (en) * | 2003-06-21 | 2005-01-19 | 华为技术有限公司 | Method for Loading FLASH using boundary scanning device |
| US20070226558A1 (en) * | 2005-11-28 | 2007-09-27 | Renesas Technology Corp. | Semiconductor integrated circuit device |
| CN101183139A (en) * | 2007-11-02 | 2008-05-21 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101464806A (en) * | 2008-12-29 | 2009-06-24 | 华为技术有限公司 | Method, apparatus and system for loading programmable logic device |
| CN101581759A (en) * | 2009-06-16 | 2009-11-18 | 华为技术有限公司 | JTAG switching interface, single board, JTAG interface conversion board and single board testing system |
| US20130346639A1 (en) * | 2012-06-21 | 2013-12-26 | Jonathan Stroud | Systems and methods for programming configurable logic devices via usb |
| CN102929651A (en) * | 2012-09-21 | 2013-02-13 | 中国航空无线电电子研究所 | Chip-array-based on-line loading system and loading method thereof |
| CN102929194A (en) * | 2012-11-06 | 2013-02-13 | 长安大学 | Asynchronous multi-core programmable automation controller (PAC) |
| CN103440148A (en) * | 2013-08-27 | 2013-12-11 | 无锡泛太科技有限公司 | Device and method for programming multiple single-chip microcomputer programs |
| CN104407882A (en) * | 2014-10-28 | 2015-03-11 | 大唐移动通信设备有限公司 | Board card device |
| CN105224372A (en) * | 2015-11-02 | 2016-01-06 | 积成电子股份有限公司 | The circuit of program operation and JTAG download program wire jumper free |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN207690065U (en) * | 2018-01-22 | 2018-08-03 | 济南浪潮高新科技投资发展有限公司 | It is a kind of based on FPGA can multy-way switching JTAG downloaders |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113687839A (en) * | 2021-08-24 | 2021-11-23 | 天津津航计算技术研究所 | On-board programming method of CPCI board card configuration chip based on PCI9054 |
| CN113687839B (en) * | 2021-08-24 | 2023-08-08 | 天津津航计算技术研究所 | PCI 9054-based on-board programming method for CPCI board card configuration chip |
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