CN201698002U - Universal test device aiming at FPGA chips - Google Patents
Universal test device aiming at FPGA chips Download PDFInfo
- Publication number
- CN201698002U CN201698002U CN2010202417168U CN201020241716U CN201698002U CN 201698002 U CN201698002 U CN 201698002U CN 2010202417168 U CN2010202417168 U CN 2010202417168U CN 201020241716 U CN201020241716 U CN 201020241716U CN 201698002 U CN201698002 U CN 201698002U
- Authority
- CN
- China
- Prior art keywords
- fpga chip
- test device
- configuration
- chip
- hand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model discloses a universal test device aiming at FPGA chips, which comprises a main controller, a configuration memory, a relay matrix, a chip fixing clamp seat and a switching clamp seat, wherein the main controller is connected with an integrated circuit test instrument on one hand, and is respectively connected with the configuration memory and the relay matrix on the other hand, the configuration memory is connected between the main controller and the relay matrix, and is used for storing configuration files of various FPGA chips, and the relay matrix is connected with the integrated circuit test instrument on one hand, and is connected with to-be-tested FPGA chips fixed on the chip fixing clamp seat on the other hand. The universal test device of the FPGA chips can carry out automatic configuration on different FPGA chips through storing the configuration files of various FPGA chips in the configuration memory, so the test requirements of various FPGA chips can be met.
Description
Technical field
The utility model relates to a kind of arrangement for testing integrated circuit, relate in particular to a kind of can be to FPGA (Field-Programmable Gate Array, field programmable gate array) universal test device tested of chip belongs to the TEST TECHNOLOGY OF LSI field.
Background technology
FPGA is the new exclusive integrated circuit that grows up on the basis of programming devices such as PAL, GAL, comprises configurable logic blocks CLB (Configurable Logic Block), output load module IOB (Input Output Block) and three parts of interconnector (Interconnect).It is by adopting the new ideas of logical cell array LCA (Logic Cell Array), both solved the deficiency of custom circuit, having overcome the limited shortcoming of original programming device gate circuit number again, therefore is one of optimal selection of short run system raising level of integrated system, reliability.
Fpga chip needs before dispatching from the factory through test.At present, the test fpga chip generally has two kinds of means: first kind is to adopt special test macro.The function of this test macro should comprise configuration FPGA, load test vector, read test response etc.But adopt this means often to invest length big, consuming time, measuring accuracy is difficult to guarantee, and the test macro of developing is portable poor, can only be used for research and checking.Second kind of means is to adopt automatic test equipment (ATE), at first FPGA is configured, and then tests.Can in same operating process, finish repeatedly " configuration-test " process of chip like this, reduce operation link, improve chip testing efficiency, thereby realize the industrialization test of fpga chip.
In the paper " based on the FPGA method of testing of ATE " that " Electronic Testing " 2007 the 12nd periodicals carry, people such as Ji Guofan with Xilinx 4010 as research object, use two kinds of simple circuit, can finish test based on the J750 test macro to LUT, carry logic, d type flip flop, and revise conveniently, portable good, for the universal test of FPGA provides a kind of practicable effective ways.But this paper is not made specific description to implementing the required hardware device of FPGA universal testing method.
In real work, use automatic test equipment (ATE) test fpga chip need use special-purpose proving installation.This proving installation is the bridge between institute's test chip and the ATE, and ATE can be configured and test by it institute's test chip.In the prior art, proving installation all be with ATE and institute's test chip one to one, that is to say that a proving installation only is applicable to that a kind of ATE (automatic test equipment) tests the situation of a certain chip.In the face of the present situation that present fpga chip is of a great variety, renewal speed is very fast, existing proving installation ubiquity versatility is poor, the test defective that kind is single, testing cost is high.
Summary of the invention
Technical problem to be solved in the utility model is to provide a kind of universal test device at fpga chip.This proving installation has good versatility, can test multiple fpga chip.
For realizing above-mentioned purpose, the utility model adopts following technical scheme:
A kind of universal test device at fpga chip is characterized in that:
Described universal test device comprises master controller, config memory, relay matrix, chip Fixing clamp-seat and switching deck; Wherein,
Described master controller connects integrated circuit tester on the one hand, connects described config memory and described relay matrix on the other hand respectively;
Described config memory is connected between described master controller and the described relay matrix, is used to store the configuration file of various fpga chips;
Described relay matrix connects integrated circuit tester on the one hand, is fastened on the tested fpga chip on the described chip Fixing clamp-seat on the other hand.
Wherein, also comprise jtag interface in the described universal test device, described jtag interface connects described master controller on the one hand, connects tested fpga chip on the other hand.
Described chip Fixing clamp-seat is the QPF208 deck.
Described relay matrix is controlled by described master controller, according to different configuration needs the resource link of configuration memory access or integrated circuit tester to the different pins of tested fpga chip.
Fpga chip universal test device provided by the utility model can dispose at different fpga chips automatically by the configuration file of the multiple fpga chip of storage in the configuration memory access, thereby satisfies the test request of various fpga chips.The configuration mode of this universal test device is flexible, and configuration categories is complete, can improve stability, degree of accuracy and the testing efficiency of integrated circuit testing greatly.
Description of drawings
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is the schematic diagram of fpga chip universal test device provided by the utility model;
Fig. 2 is that Xilinx FPGA adopts the initiatively connection block diagram of series arrangement mode;
Fig. 3 is the connection block diagram that Xilinx FPGA adopts the configuration mode that initiatively walks abreast;
Fig. 4 is the sequential chart that adopts peripheral configuration mode;
Fig. 5 is the exemplary plot that a plurality of fpga chip series connection form a JTAG chain.
Embodiment
As shown in Figure 1, fpga chip universal test device provided by the utility model is made up of master controller, config memory, relay matrix, chip Fixing clamp-seat (not shown) and switching deck.Wherein, master controller connects integrated circuit tester on the one hand, therefrom obtains the resource of integrated circuit tester; Connect config memory and relay matrix on the other hand respectively, so that they are controlled.Config memory is connected between master controller and the relay matrix, is used to store the configuration file of various fpga chips.When test, config memory can provide test required configuration file to master controller.Above-mentioned master controller can be realized by MCU (microcontroller), DSP general purpose microprocessors such as (digital signal processors).Config memory can be E
2PROM or FLASH (nonvolatile memory) etc.As required, the config memory in this fpga chip universal test device can be set to a plurality of.Because config memory can be stored the configuration file of various fpga chips, therefore this fpga chip universal test device can be finished configuration effort to fpga chip automatically according to the configuration requirement of different fpga chips, and carries out the flexible configuration of active mode, passive mode and JTAG mode as required.
Relay matrix directly is connected with integrated circuit tester on the one hand, is fastened on the tested fpga chip on the chip Fixing clamp-seat on the other hand.This relay matrix is controlled by master controller, can according to different configuration needs the resource link of configuration memory access or integrated circuit tester to the different pins of fpga chip.According to the difference of configuration mode, can the automatically switch connected mode of integrated circuit tester pin and fpga chip of relay matrix is finished configuration, functional test and parameter testing work to fpga chip.
At present, the more employing of fpga chip QFP (Quad Flat Package, flat package) 208 packaged types, so the chip Fixing clamp-seat in this fpga chip universal test device preferentially uses the QPF208 deck to fix chip.But in practice, fpga chip also has the situation of using other packaged type such as DIP, PLCC etc., so this chip Fixing clamp-seat form of also wanting corresponding selection to adapt with it.This routine that is those of ordinary skills can both carry out is selected, and has not just given unnecessary details in detail at this.
Above-mentioned switching deck is mainly used in realizes being connected between this fpga chip universal test device and the integrated circuit tester that it is fixedly mounted on the PCB circuit board of this fpga chip universal test device.
In this fpga chip universal test device, store the configuration file of multiple fpga chip by disposing memory access, relay matrix is responsible for config memory, test resource is connected with fpga chip, the main controller controls whole test process.After master controller is received the test commencing signal, different according to configuration mode and chip kind, the pilot relay matrix is communicated with fpga chip as required with config memory, send configuration file according to correct sequential control config memory to fpga chip, thereby fpga chip is disposed automatically.Be sent completely information to this fpga chip universal test device after configuration is finished, relay matrix switches simultaneously, fpga chip is communicated with the resource of integrated circuit tester, so that carry out the test of the function and the parameter of fpga chip.
The final internal logic structure of fpga chip is determined by configuration data.For the fpga chip of a certain model, its configuration file format all is the same, disposes required pin and also determines, configuration sequential and layoutprocedure also are constant.In this fpga chip universal test device, configuration file stores is in config memory, and configuration pin is switched by relay matrix, and configuration sequential and layoutprocedure are by main controller controls.Below, be that example is carried out specific description with the XC3030 FPGA of Xilinx.
The configuration file length of XC3030 is 22,216, preceding 40 is file header, file finishes with " 1111 ", have 241 frame configuration datas in the middle of the file, every frame length is 92bit, and these configuration datas are loaded among the SRAM of fpga chip inside by external control circuit, the inside of fpga chip just possesses certain logical organization, thereby reaches the function that user program will be realized.
Xilinx FPGA has 5 kinds of configuration modes: active serial mode, byte holotype (address ascending order), byte holotype (address descending), peripheral modes and active parallel schema.Fig. 2 and Fig. 3 adopt initiatively serial mode and initiatively the fpga chip configuration block diagram of parallel schema.
For fpga chip, a part of pin is used to be configured.For example used configuration pin has in peripheral configuration mode:
M0, M1, M2,
DONE/
RDY/
CS2, D0～D7 etc., D0～D7 are data-signals, other be control signal.What these pins had only works in layoutprocedure, and what have can also use as general I/O mouth after configuration is finished.
Fig. 4 is the sequential chart that adopts peripheral configuration mode.It disposes by byte, by
The CS2 input signal is controlled write operation, RDY/
Be the answer signal of shaking hands, RDY/ behind the configuration data that writes a byte
Become low,
Effectively, this moment, handled the byte that receives the internal buffer, can not receive new data, after finishing dealing with, and RDY/
Signal becomes height again, can receive the configuration data of next byte.T among Fig. 4
BUSYLength change according to the internal state of fpga chip, generally speaking,, finish tens microseconds of the longest needs of configuration of a byte to the FPGA of XC3000 series.
Concrete layoutprocedure is as follows:
1) initialization, system power on, and user-programmable I/O pins all after powering on all become three-state;
2) empty config memory;
Finish power on and empty the storer process after, fpga chip can with
Signal is put low level, begins to empty config memory simultaneously, then,
Signal will be changed to high level again.
3) sampling configuration mode;
After the emptying of config memory finished, the device inspection
Signal,
Be height, fpga chip will be sampled to configuration mode pin M2, M1, M0, to determine which kind of mode loading configuration data with.
4) load configuration data;
5) enter the START-UP state;
After all data configurations were finished, fpga chip entered the START-UP state, the DONE/ of chip
Leg signal is uprised by low, and the sign configuration finishes, and each I/O pin will switch to the state that the user is provided with from three-state.After the START-UP state finished, the content that the user is provided with successfully was loaded into fpga chip, as long as to the fpga chip normal power supply, these information will keep down always.
In general, the test of fpga chip can be represented with a set: TestFPGA={ (configuration 1, functional test 1, parameter testing 1) ..., (configuration n, functional test n, parameter testing n) }.That is to say that this fpga chip universal test device at first will be realized the configuration of fpga chip, and under the situation that the configuration information that guarantees fpga chip is not lost, finish function corresponding and parameter testing.Various configurations just can reach testing requirement if desired, and then this process need repeats repeatedly.
As shown in Figure 1, also be provided with jtag interface in this fpga chip universal test device.This jtag interface connects master controller on the one hand, connects tested fpga chip on the other hand.JTAG is a kind of international standard test protocol (IEEE 1149.1 compatibilities), is mainly used in the chip internal test.Its ultimate principle is internal node to be tested by the jtag test instrument of special use at a chip internal TAP of definition (Test Access Port, test access mouth).As shown in Figure 5, jtag test allows a plurality of fpga chips to be cascaded by jtag interface, forms a JTAG chain, thereby realizes each fpga chip is tested respectively.
Above this fpga chip universal test device is had been described in detail.For one of ordinary skill in the art, any conspicuous change of under the prerequisite that does not deviate from the utility model connotation it being done all will constitute to the utility model infringement of patent right, with corresponding legal responsibilities.
Claims (5)
1. universal test device at fpga chip is characterized in that:
Described universal test device comprises master controller, config memory, relay matrix, chip Fixing clamp-seat and switching deck; Wherein,
Described master controller connects integrated circuit tester on the one hand, connects described config memory and described relay matrix on the other hand respectively;
Described config memory is connected between described master controller and the described relay matrix, is used to store the configuration file of various fpga chips;
Described relay matrix connects integrated circuit tester on the one hand, is fastened on the tested fpga chip on the described chip Fixing clamp-seat on the other hand.
2. the universal test device at fpga chip as claimed in claim 1 is characterized in that:
Also comprise jtag interface in the described universal test device, described jtag interface connects described master controller on the one hand, connects tested fpga chip on the other hand.
3. the universal test device at fpga chip as claimed in claim 1 is characterized in that:
Described chip Fixing clamp-seat is the QPF208 deck.
4. the universal test device at fpga chip as claimed in claim 1 is characterized in that:
Described relay matrix is controlled by described master controller, according to different configuration needs the resource link of configuration memory access or integrated circuit tester to the different pins of tested fpga chip.
5. the universal test device at fpga chip as claimed in claim 1 is characterized in that:
Described config memory is E
2PROM or FLASH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202417168U CN201698002U (en) | 2010-06-29 | 2010-06-29 | Universal test device aiming at FPGA chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202417168U CN201698002U (en) | 2010-06-29 | 2010-06-29 | Universal test device aiming at FPGA chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201698002U true CN201698002U (en) | 2011-01-05 |
Family
ID=43399249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202417168U Expired - Lifetime CN201698002U (en) | 2010-06-29 | 2010-06-29 | Universal test device aiming at FPGA chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201698002U (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184721A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two stages of field programmable gate array (FPGA) chips and large-screen control system |
| CN103513206A (en) * | 2012-06-29 | 2014-01-15 | 中国船舶重工集团公司第七0九研究所 | Calibration device and method for microampere direct current in integrated circuit testing system |
| CN104020409A (en) * | 2013-02-28 | 2014-09-03 | 中兴通讯股份有限公司 | Chip adaptive configuration method and device |
| CN105093096A (en) * | 2015-08-13 | 2015-11-25 | 浪潮集团有限公司 | Testing device for FPGA (Field-Programmable Gate Array) |
| CN105205034A (en) * | 2015-09-25 | 2015-12-30 | 中国人民解放军国防科学技术大学 | Method for high-reliability parameter configuration based on application specific integrated circuit (ASIC) |
| CN105510803A (en) * | 2015-12-30 | 2016-04-20 | 深圳市科美集成电路有限公司 | Integrated circuit testing device and method |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| CN105911451A (en) * | 2016-04-05 | 2016-08-31 | 硅谷数模半导体（北京）有限公司 | Chip test method and chip test device |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| CN106483450A (en) * | 2016-09-28 | 2017-03-08 | 河海大学常州校区 | A kind of chip detecting system for digital circuit practical teaching |
| WO2017092544A1 (en) * | 2016-07-15 | 2017-06-08 | 上海华岭集成电路技术股份有限公司 | Configuration and testing method and system for fpga chip using bumping process |
| CN107390116A (en) * | 2017-07-27 | 2017-11-24 | 中科亿海微电子科技（苏州）有限公司 | The device and method of FPGA device parallel schema configuration |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN108267683A (en) * | 2017-01-04 | 2018-07-10 | 中兴通讯股份有限公司 | The method and device that a kind of FPGA tests oneself |
| CN111061677A (en) * | 2019-12-26 | 2020-04-24 | 杭州迪普科技股份有限公司 | FPGA configuration method and device and FPGA device |
| CN112485653A (en) * | 2020-11-13 | 2021-03-12 | 中国电子科技集团公司第二十四研究所 | Integrated circuit testing system and method |
-
2010
- 2010-06-29 CN CN2010202417168U patent/CN201698002U/en not_active Expired - Lifetime
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102184721B (en) * | 2011-03-31 | 2014-01-01 | 杭州海康威视数字技术股份有限公司 | Daughter board with two stages of field programmable gate array (FPGA) chips and large-screen control system |
| CN102184721A (en) * | 2011-03-31 | 2011-09-14 | 杭州海康威视数字技术股份有限公司 | Daughter board with two stages of field programmable gate array (FPGA) chips and large-screen control system |
| CN103513206A (en) * | 2012-06-29 | 2014-01-15 | 中国船舶重工集团公司第七0九研究所 | Calibration device and method for microampere direct current in integrated circuit testing system |
| CN103513206B (en) * | 2012-06-29 | 2016-08-24 | 中国船舶重工集团公司第七0九研究所 | The calibrating installation of a kind of microampere order DC current in integrated circuit test system and method thereof |
| CN104020409A (en) * | 2013-02-28 | 2014-09-03 | 中兴通讯股份有限公司 | Chip adaptive configuration method and device |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| CN105093096B (en) * | 2015-08-13 | 2017-08-29 | 浪潮集团有限公司 | A kind of FPGA test device |
| CN105093096A (en) * | 2015-08-13 | 2015-11-25 | 浪潮集团有限公司 | Testing device for FPGA (Field-Programmable Gate Array) |
| CN105205034A (en) * | 2015-09-25 | 2015-12-30 | 中国人民解放军国防科学技术大学 | Method for high-reliability parameter configuration based on application specific integrated circuit (ASIC) |
| CN105205034B (en) * | 2015-09-25 | 2016-08-17 | 中国人民解放军国防科学技术大学 | A kind of highly reliable method for parameter configuration based on ASIC |
| CN105510803A (en) * | 2015-12-30 | 2016-04-20 | 深圳市科美集成电路有限公司 | Integrated circuit testing device and method |
| CN105911451A (en) * | 2016-04-05 | 2016-08-31 | 硅谷数模半导体（北京）有限公司 | Chip test method and chip test device |
| WO2017092544A1 (en) * | 2016-07-15 | 2017-06-08 | 上海华岭集成电路技术股份有限公司 | Configuration and testing method and system for fpga chip using bumping process |
| CN106483450A (en) * | 2016-09-28 | 2017-03-08 | 河海大学常州校区 | A kind of chip detecting system for digital circuit practical teaching |
| CN108267683A (en) * | 2017-01-04 | 2018-07-10 | 中兴通讯股份有限公司 | The method and device that a kind of FPGA tests oneself |
| CN107390116A (en) * | 2017-07-27 | 2017-11-24 | 中科亿海微电子科技（苏州）有限公司 | The device and method of FPGA device parallel schema configuration |
| CN107589368A (en) * | 2017-08-24 | 2018-01-16 | 成都天奥技术发展有限公司 | EPC3C120F484 types FPGA configurations/test/debugging adapter |
| CN111061677A (en) * | 2019-12-26 | 2020-04-24 | 杭州迪普科技股份有限公司 | FPGA configuration method and device and FPGA device |
| CN111061677B (en) * | 2019-12-26 | 2023-01-24 | 杭州迪普科技股份有限公司 | FPGA configuration method and device and FPGA device |
| CN112485653A (en) * | 2020-11-13 | 2021-03-12 | 中国电子科技集团公司第二十四研究所 | Integrated circuit testing system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN201698002U (en) | Universal test device aiming at FPGA chips | |
| CN103620431B (en) | The integrated circuit tested is carried out for using high speed input/output interface | |
| US20230296670A1 (en) | Device access port selection | |
| CN103744009A (en) | Serial transmission chip test method, serial transmission chip test system and integrated chip | |
| CN111366841B (en) | FPGA programmable logic unit test equipment and use method | |
| US20070192657A1 (en) | Configuring flash memory | |
| CN202614902U (en) | Function testing device for digital signal processor (DSP) chip | |
| US6202186B1 (en) | Integrated circuit tester having pattern generator controlled data bus | |
| CN214174564U (en) | Signal gating device and chip testing device | |
| CN101872308A (en) | Memory bar control system and control method thereof | |
| CN103455419A (en) | Field programmable gate array platform and testing method thereof | |
| CN202502660U (en) | Programmable digital logic circuit basic experiment plate | |
| CN103019990A (en) | Method for uploading data at collection end through starting PCI-E (Peripheral Component Interconnect-Express) bus DMA (Direct Memory Access) | |
| JP2006162285A (en) | Testing device and method for semiconductor integrated circuit | |
| CN201489794U (en) | LCM testing device | |
| CN103809051B (en) | The detection method of switch matrix, Auto-Test System and switch matrix therein | |
| CN202285042U (en) | Automatic test system for complex programmable logic device (CPLD) | |
| CN102280141A (en) | Programming method for flash memory chip, and apparatus thereof | |
| CN104239084A (en) | Implementing method for automatically loading DSP (digital signal processor) procedures | |
| CN100442072C (en) | Test circuit and test method thereof | |
| CN209842622U (en) | Integrated simulation system | |
| CN206833184U (en) | Interface module for microcontroller | |
| CN201083810Y (en) | Test card | |
| CN100460876C (en) | Measuring system and its data interface converting device | |
| CN203325179U (en) | Circuit structure of multi-interface power meter reading terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110105 |
|
| CX01 | Expiry of patent term |