CN202502660U

CN202502660U - Programmable digital logic circuit basic experiment plate

Info

Publication number: CN202502660U
Application number: CN2012201146914U
Authority: CN
Inventors: 王鹏
Original assignee: Suzhou Vocational University
Current assignee: Suzhou Vocational University
Priority date: 2012-03-22
Filing date: 2012-03-22
Publication date: 2012-10-24
Anticipated expiration: 2022-03-22

Abstract

The utility model discloses a programmable digital logic circuit basic experiment plate, including a PCB board. A CPLD chip is arranged in the middle of the PCB board and is respectively connected with an independent logic gate, an adder and a trigger; a power supply circuit, a 8-bit LED nixie tube and a 4-bit LED nixie tube are arranged at the upper portion of the PCB board; a 8-bit switch key and a 8-bit LED indication circuit are arranged at the right corner of the PCB board; two dial-up code switches are arranged at the left corner of the PCB board, wherein the dial-up code switches are a clock frequency selection circuit and an experiment module selection module; and the CPLD chip is also connected with a JTAG debugging and download port and a signal measurement port. According to the utility model, a digital logic experiment basic experiment in a digital circuit course can be completed, thereby meeting experiment requirements at different level by students and increasing perceptual knowledge of the students conveniently; and moreover, the layout of the experiment plate enables convenience and maneuverability during the experiment to be fully considered.

Description

A kind of programmable DLC(digital logic circuit) infrastest plate

Technical field

The utility model relates to DLC(digital logic circuit) infrastest, EDA technology, PLD and pcb board design, is specifically related to a kind of programmable DLC(digital logic circuit) infrastest plate.

Background technology

Along with developing rapidly of Chinese digital circuit experiment plate market; The continuous expansion of product output; National industrial policies encourage digital circuit experiment plate industry to develop to the high-tech product direction; The investor is more and more closer to the concern of digital circuit experiment board industry, and this makes the growth requirement of digital circuit experiment board industry increase.Along with development of electronic technology, the design of electronic circuit experiment plate becomes and becomes increasingly complex, in order to better meet the use of colleges and universities and R&D institution.Electronic Design is carried out in utilization " language " has become a kind of trend, in order to improve development efficiency, shortens the construction cycle, therefore adopts the digital circuit experiment plate based on the EDA technical design will become new development trend.

Traditional digital circuit infrastest casing is long-pending greatly heavy, not portable; Different experiments needs the different hardware circuit module, needs often replacement, and is fragile; The signal of disparate modules connects through outside wire jumper during experiment, poor reliability; The cost of traditional experiment case is higher, and ease for maintenance is poor.The little portability of digital circuit experiment plate bulk based on the EDA technical design is strong; Application of logic circuit module and intermodule signal are built in the PLD in connecting all, and stable and reliable for performance, holding circuit is complete; Test convenient, flexiblely, can freely expand experimental project as required.

The utility model content

The utility model provides a kind of programmable DLC(digital logic circuit) infrastest plate; Purpose is for the experiment of satisfying the DLC(digital logic circuit) course, demand in practice; Utilize a block structure of the CPLD designs in the EDA technology compact, portable strong, need not to increase under the situation of additional experiments device or equipment; Can accomplish the Digital Logic infrastest plate in the digital circuit course, and can be through the JTAG mouth to experiment design again.

For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the utility model is realized through following technical scheme:

A kind of programmable DLC(digital logic circuit) infrastest plate comprises a pcb board, is provided with the CPLD chip in the middle of the said pcb board, and said CPLD chip connects independent logical door, totalizer and trigger respectively; Said pcb board top is provided with power circuit, 8 LED and 4 LED charactrons, and said 8 LED all are connected with said CPLD chip with said 4 LED charactrons; The lower right corner of said pcb board is provided with 8 bit switch buttons and 8 LED indicating circuits, and said 8 bit switch buttons and said 8 input state indication LED all are connected with said CPLD chip; The lower left corner of said pcb board is provided with two plucking number sign switches, and said two plucking number sign switches are that clock frequency selects circuit and experiment module to select circuit, and said two plucking number sign switches all are connected with said CPLD chip; Said CPLD chip also connects the JTAG debugging and downloads mouth, signal measurement port.

Further, said CPLD chip internal is provided with 10 combinational logic circuits, and said combinational logic circuit comprises counter, code translator, frequency divider.

Further, said CPLD chip internal is provided with 6 sequential logical circuits, and said sequential logical circuit comprises register, frequency divider.

Further, reserved on the said pcb board some groups independently not gate, with door, OR circuit and d type flip flop interface.

Further, the size of said pcb board is 11*10cm.

The principle of the utility model is:

Utilize CPLD chip EPM1270T144C5 in the EDA technology as the logical sequence processing apparatus, EPM1270T144C5 is the MAXII family chip of altera corp, has 1270 logical blocks (LE); 116 user I/O mouths; 8KB User Flash Memory, pin is 6.3ns to the time in logical delay of pin, system clock is 50MHz; Designing and developing by Quartus II software of CPLD chip accomplished, and download through the JTAG mouth.Peripheral input control device and Output Display Unit spare are made up of button (switch) and LED (data pipe) commonly used, and clock frequency is selected and the selection of experimental circuit module is realized by plucking number sign switch.

CPLD device EPM1270T144C5 indoor design has comprised counter altogether; Code translator; 10 combinational logic circuits such as frequency divider and register; 6 sequential logical circuits such as frequency divider, in addition in order to test expansion needs, also added on the brassboard 4 d type flip flop circuit and 8 with, OR circuit.

In order to satisfy portability and ease for use, need carry out rational deployment to each resource of digital brassboard, the top of the panel of brassboard is power circuit and LED and charactron display circuit.The centre then includes acp chip EPM1270T144C5; Design and draw by chip internal with door; Or door, not gate, circuit such as trigger; The lower right corner of brassboard is 8 buttons (switch) input and LED indicating circuit, and two plucking number sign switches in the lower left corner of brassboard then are clock selection circuit and experimental selection circuit.

The beneficial effect of the utility model is:

This brassboard can be accomplished the Digital Logic infrastest in the digital circuit course; (like gate logic, combinational logic, trigger, volume/code translator, counter, frequency divider, dynamic display circuit etc.); Satisfy the requirement of experiment of student's different levels, be convenient to increase student's perceptual knowledge.Convenience when the layout of brassboard has taken into full account experiment, operability.Brassboard compact conformation, experimental project satisfy the requirement of each universities and colleges " Fundamental Digital Electronic Technique " course teaching outline fully.JATG mouth on the brassboard lets student's contrived experiment content and experimentizing voluntarily; Deepen the understanding and the raising of logarithm electricity course; Teacher and Electronic Design fan also can combine the exploitation of Quartus II at the enterprising line of numbers logical circuit of brassboard, and design and emulation improve its utilization rate.

Above-mentioned explanation only is the general introduction of the utility model technical scheme, in order more to know the technological means of understanding the utility model, and can implement according to the content of instructions, below with the preferred embodiment and the conjunction with figs. detailed description of the utility model.The embodiment of the utility model is provided by following examples and accompanying drawing thereof in detail.

Description of drawings

Accompanying drawing described herein is used to provide the further understanding to the utility model, constitutes the application's a part, and illustrative examples of the utility model and explanation thereof are used to explain the utility model, do not constitute the improper qualification to the utility model.In the accompanying drawings:

The circuit module synoptic diagram of Fig. 1 the utility model.

Label declaration among the figure: 1, pcb board, 2, the CPLD chip, 3, the independent logical door, 4, totalizer; 5, trigger, 6, power circuit, 7,8 LED, 8,4 LED charactrons; 9,8 bit switch buttons, 10,8 LED indicating circuits, 11, clock frequency selects circuit; 12, experiment module is selected circuit, and 13, JTAG debugging and download mouthful, 14, the signal measurement port.

Embodiment

Below with reference to accompanying drawing and combine embodiment, specify the utility model.

Referring to shown in Figure 1, a kind of programmable DLC(digital logic circuit) infrastest plate comprises a pcb board 1, is provided with CPLD chip 2 in the middle of the said pcb board 1, and said CPLD chip 2 connects independent logical door 3, totalizer 4 and trigger 5 respectively; Said pcb board 1 top is provided with 6,8 LED 7 of power circuit and 4 LED charactrons 8, and said 8 LED 7 all are connected with said CPLD chip 2 with said 4 LED charactrons 8; The lower right corner of said pcb board 1 is provided with 8 bit switch buttons 9 and 8 LED indicating circuits 10, and said 8 bit switch buttons 9 and said 8 input state indication LED 10 all are connected with said CPLD chip 5; The lower left corner of said pcb board 1 is provided with two plucking number sign switches, and said two plucking number sign switches are that clock frequency selects circuit 11 and experiment module to select circuit 12, and said two plucking number sign switches all are connected with said CPLD chip 2; Said CPLD chip 2 also connects the JTAG debugging and downloads mouth 13, signal measurement port one 4.

Further, said CPLD chip 2 set inside have 10 combinational logic circuits, and said combinational logic circuit comprises counter, code translator, frequency divider.

Further, said CPLD chip 2 set inside have 6 sequential logical circuits, and said sequential logical circuit comprises register, frequency divider.

Further, reserved on the said pcb board 1 some groups independently not gate, with door, OR circuit and d type flip flop interface.

Further, the size of said pcb board 1 is 11*10cm.

Concrete method of application is: at first insert the 5V power supply through upper left corner power interface and power on to brassboard; Select Digital Logic infrastest circuit module by brassboard SYS_SEL plucking number sign switch then; Control signal produces through brassboard bottom right face S1-S8 button (KEY1-KEY8 switch) hardware circuit, simultaneously the state of the light on and off indication input control signal of the corresponding LED of button (switch) top.Like what select is the sequential logic experiment, and then clock signal can be obtained by three kinds of modes, and a kind of is to be produced by the inner frequency dividing circuit of CPLD, selects different clock frequencies through the SCLK plucking number sign switch; The another kind of JOUTCLK interface that can pass through on the brassboard inserts the external clock frequency; The third is to produce frequency manufal operation time through SSTEP button on the brassboard.CPLD accomplishes sequential (or combination) logic analysis processing according to input control signal and selected circuit module, controls LED or charactron display result on the pcb board from the output of I/O mouth.Realize comparatively complicated logic experiment or design like need, can utilize a plurality of unconnected gate circuit or the d type flip flop reserved around the brassboard CPLD chip, carry out circuit with the mode of wire jumper and connect.Brassboard CPLD chip the right is the JTAG mouth, can use earlier QartusII software to DLC(digital logic circuit) develop, design and emulation, and download on the brassboard and verify.

It is emphasized that; Though above-mentioned facility example is to the utility model detailed explanation of contrasting; But these explanations are just illustrative to the utility model; Rather than to the restriction of utility model, any innovation and creation that do not exceed in the utility model connotation all drop within the utility model rights protection scope.

Claims

1. programmable DLC(digital logic circuit) infrastest plate is characterized in that: comprise a pcb board (1), is provided with CPLD chip (2) in the middle of the said pcb board (1), said CPLD chip (2) connects independent logical door (3), totalizer (4) and trigger (5) respectively; Said pcb board (1) top is provided with power circuit (6), 8 LED (7) and 4 LED charactrons (8), and said 8 LED (7) all are connected with said CPLD chip (2) with said 4 LED charactrons (8); The lower right corner of said pcb board (1) is provided with 8 bit switch buttons (9) and 8 LED indicating circuits (10), and said 8 bit switch buttons (9) and said 8 input state indication LED (10) all are connected with said CPLD chip (5); The lower left corner of said pcb board (1) is provided with two plucking number sign switches, and said two plucking number sign switches are that clock frequency selects circuit (11) and experiment module to select circuit (12), and said two plucking number sign switches all are connected with said CPLD chip (2); Said CPLD chip (2) also connects the JTAG debugging and downloads mouthful (13), a signal measurement port (14).

2. programmable DLC(digital logic circuit) infrastest plate according to claim 1 is characterized in that: said CPLD chip (2) set inside has 10 combinational logic circuits, and said combinational logic circuit comprises counter, code translator, frequency divider.

3. programmable DLC(digital logic circuit) infrastest plate according to claim 1 is characterized in that: said CPLD chip (2) set inside has 6 sequential logical circuits, and said sequential logical circuit comprises register, frequency divider.

4. programmable DLC(digital logic circuit) infrastest plate according to claim 1 is characterized in that: reserved on the said pcb board (1) some groups independently not gate, with door, OR circuit and d type flip flop interface.

5. programmable DLC(digital logic circuit) infrastest plate according to claim 1, it is characterized in that: the size of said pcb board (1) is 11*10cm.