CN202383658U - SOPC (System-on-a-Programmable-Chip) development platform on basis of Nios II system - Google Patents
SOPC (System-on-a-Programmable-Chip) development platform on basis of Nios II system Download PDFInfo
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- CN202383658U CN202383658U CN2011205224833U CN201120522483U CN202383658U CN 202383658 U CN202383658 U CN 202383658U CN 2011205224833 U CN2011205224833 U CN 2011205224833U CN 201120522483 U CN201120522483 U CN 201120522483U CN 202383658 U CN202383658 U CN 202383658U
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Abstract
The utility model relates to an SOPC (System-on-a-Programmable-Chip) development platform on a basis of a Nios II system. The SOPC development platform is characterized by comprising a core board and an interface board, wherein the core board is provided with an FPGA (Field Programmable Gata Array) chip, an SDRAM (Field Programmable Gata Array), FLASH, a JTGA download interface, an ASP (Active Server Page) download interface, an active crystal and an external interface of the core board which support an Nios II soft-core processor; and the interface board is provided with an interface matched with the external interface of the core board to be connected with the core board, a VGA (Video Graphics Array) display interface, an LCD (liquid crystal display) displaying interface, a nixie tube, an LED (light-emitting diode) lattice screen, a multidigit LED lamination tube, a buzzer, a temperature sensor, an infrared wireless communication module, a serial port, a rotary coder, an expansion IO (inputoutput) port, a keyboard, a dial switch, AD (analogdigital) and DA (digitalanalog) converter, a power interface, a PS2 (Play Station 2) interface, a USB (universal serial bus) interface, an SPI (Single Program Initiation) interface and an IIC interface. The SOPC development platform has complete development functions and is simple in structure and low in manufacturing cost.
Description
Technical field
The utility model relates to a kind of SOPC development platform based on Nios II system.
Background technology
SOPC (System-on-a-Programmable-Chip), SOC(system on a chip) promptly able to programme is a kind of special embedded system, utilization FPGA technology is put into total system on the silicon chip, is used for the research of embedded system and the processing of electronic information.SOPC be SOC(system on a chip) be again programmable system, both can accomplish the main logic function of total system by single chip, the design flexible mode is arranged again, can reduce, extendible, scalable, possess the function of software and hardware at system programmable.
Develop rapidly along with semiconductor industry; SOPC has combined SOC (SOC(system on a chip)) and FPGA (field programmable gate array) advantage separately; Have programmable logic resource, processor debugging interface and FPGA DLL on high-speed RAM resource in the low capacity sheet, abundant IP Core resource, the enough sheet, and have characteristics such as single-chip, low-power consumption, little encapsulation.Dirigibility and very big advantage price on of SOPC on using makes SOPC become the optimal selection that contemporary electronic systems is designed and developed.
Present SOPC development platform, by the exploitation of external chip manufacturer, hardware configuration very complicacy, function singleness, be unfavorable for carrying, the cost costliness, both uneconomical for general beginner, also be not easy to learn at short notice.The development platform that domestic manufacturer produces generally is to do with the form of experimental box, and cost is higher, and renewal speed is slow, and the study that can't carry out system intuitively is with exploitation and be unfavorable for the exploitation of system greatly.
Summary of the invention
The purpose of the utility model is to overcome the deficiency of prior art, and a kind of SOPC development platform based on Nios II system is provided, and this development platform not only development function is complete, and simple in structure, low cost of manufacture.
The purpose of the utility model is achieved in that a kind of SOPC development platform based on Nios II system; It is characterized in that: comprise core board and the interface board that is connected with said core board, said core board is provided with fpga chip, SDRAM, FLASH, JTGA download interface, the ASP download interface of supporting Nios II soft-core processor, source crystal and core board external interface is arranged;
Said interface board is provided with said core board external interface and matches with interface, VGA display interface, LCD display interface, charactron, LED dot matrix screen, Multi-bit LED luminotron, hummer, temperature sensor, infrared radio communication module, serial ports, rotary encoder, expansion I/O mouth, keyboard, toggle switch, A/D and D/A, power interface, PS2 interface, USB interface, SPI interface and the IIC interface that is connected core board.
The beneficial effect of the utility model is:
1, Nios II soft-core processor have complete customizable performance, lower product and implementation cost, ease for use, adaptability and can be not out-of-date etc. advantage; In designing and developing, can both realize perfectly joining at every turn; Reduced the complexity of design, the power consumption of product and cost make system architecture simple; Good stability makes things convenient for upgrading product.
2, be the basis with Nios II soft-core processor, with the behavior of higher level lanquage (like Verilog or HDL) representation function piece, dirigibility is high, can repeat to revise to satisfy new system requirements; Independent with technology, do not relate to circuit, circuit component, can be comprehensive again according to concrete technology, thus avoided the destiny that is eliminated.
3, utilize the SOPC technology; Nios II soft-core processor is integrated in the fpga chip, and the user can utilize corresponding eda tool according to designing requirement; Nios II soft-core processor and peripheral hardware thereof are made up; The processor that acquisition satisfies the demands just makes the utility model satisfy the custom system designing requirement at aspects such as hardware configuration, functional characteristics, resource occupation comprehensively, and reduces the overall cost of system development.
4, owing in FPGA, use Nios II soft-core processor, can realize the upgrading of on-the-spot hardware and software easily, and product can meet up-to-date standard, have up-to-date characteristic.
5, provide JTAG to download mouth and ASP download mouth.The JTAG debugging module provide through the PC main frame realize Nios II processor in chip controls, debugging and communication function, this is a characteristic that has competitive power of this Nios II soft-core processor.
6, hardware configuration is simple, and is multiple functional, is easy to carry, cost is low, can carry out the exploitation of electronic system intuitively.Owing to be furnished with the SDRAM of 64M bit and the FLASH of 64M bit, can support the exploitation of big system, have good expanding function.
Below in conjunction with accompanying drawing and specific embodiment the utility model is done further to specify.
Description of drawings
Fig. 1 is the core board structural representation of the utility model embodiment.
Fig. 2 is the interface board structural representation of the utility model embodiment.
Fig. 3 is the one-piece construction synoptic diagram of the utility model embodiment.
Fig. 4 is a clocking scheme on the core board of the utility model embodiment.
Fig. 5 is a SDRAM circuit diagram on the core board of the utility model embodiment.
Fig. 6 is the core board external interface circuit diagram of the utility model embodiment.
Fig. 7 is VGA display interface circuit figure on the interface board of the utility model embodiment.
Fig. 8 is LCD display interface circuit figure on the interface board of the utility model embodiment.
Fig. 9 is charactron and a LED dot matrix screen circuit diagram on the interface board of the utility model embodiment.
Figure 10 is buzzer circuit figure on the interface board of the utility model embodiment.
Figure 11 is temperature sensor circuit figure on the interface board of the utility model embodiment.
Figure 12 A is an infraluminescence pipe circuit diagram on the interface board of the utility model embodiment.
Figure 12 B is an infrared receiving terminal circuit diagram on the interface board of the utility model embodiment.
Figure 13 is serial port circuit figure on the interface board of the utility model embodiment.
Figure 14 is a serial EEPROM circuit diagram on the interface board of the utility model embodiment.
Figure 15 is digital clock circuit figure on the interface board of the utility model embodiment.
Figure 16 is a rotary encoder circuit diagram on the interface board of the utility model embodiment.
Figure 17 is PS2 interface circuit figure on the interface board of the utility model embodiment.
Figure 18 A is that the I/O of a biserial 2 * 13 on the interface board of the utility model embodiment expands pin circuitry figure.
Figure 18 B is that the I/O of another biserial 2 * 13 on the interface board of the utility model embodiment expands pin circuitry figure.
Figure 19 is 4 * 4 matrix keyboard circuit diagrams on the interface board of the utility model embodiment.
Figure 20 is 4 stand-alone keypad circuit diagrams on the interface board of the utility model embodiment.
Figure 21 is 8 toggle switch circuit diagrams on the interface board of the utility model embodiment.
Figure 22 is A/D and D/A change-over circuit figure on the interface board of the utility model embodiment.
Figure 23 is a power circuit diagram on the interface board of the utility model embodiment.
Embodiment
The utility model is based on the SOPC development platform of Nios II system, and is as shown in Figure 3, comprises core board and the interface board that is connected with said core board.As shown in Figure 1; Said core board be provided with SDRAM (like Fig. 5), the 64M bit of EP2C8Q208-fpga chip of supporting Nios II soft-core processor, 64M bit FLASH, JTGA download interface, ASP download interface, source crystal (like Fig. 4) and core board external interface etc. are arranged, said core board external interface is 2 48 PIN connectors (like Fig. 6).
As shown in Figure 2, said interface board is provided with said core board external interface and matches with interface, VGA display interface, LCD display interface, charactron, LED dot matrix screen, Multi-bit LED luminotron, hummer, temperature sensor, infrared radio communication module, serial ports, rotary encoder, expansion I/O mouth, keyboard, toggle switch, A/D and D/A, power interface, PS2 interface, USB interface, SPI interface and the IIC interface that is connected core board.
Above-mentioned wireless communication module comprises infraluminescence pipe and the infrared receiving terminal that is used to simulate IR remote controller.
Be connected with the spi bus clock chip on the above-mentioned IIC interface.
Be connected with the serial EEPROM storage chip on the above-mentioned SPI interface.
In the use said core board is connected with interface board, carries out the exploitation of following system item.
The Presentation Function exploitation: 1, VGA shows (like Fig. 7), and the display of VGA display interface with the VGA interface is connected, and drives VGA through the output of core board FPGA pin and shows the demonstration that can realize picture and literal; 2, liquid crystal display shows (like Fig. 8), and the utility model is provided with 1602LCD display interface and 12864 display interfaces, through the adjusting may command contrast of display degree of potentiometer; 3, charactron shows (like Fig. 9), comes 24 common cathode charactrons are carried out position control decoding with 74HC138, directly controls segment encode with the I/O of FPGA, can realize that numeral, time etc. dynamically show to test; 4,8X8LED dot matrix screen (like Fig. 9) adopts 74HC138 to come it is gone position control decoding, saving the I/O of the utility model, comes directly control segment encode with the I/O of FPGA, can show a multiple simple figure and a simple Chinese character.5,8 LED luminotrons, FPGA comes the driving LED lamp with low level mode, can realize multiple display effects such as thunderbolt lamp, running lamp.
The hummer functional development: shown in figure 10, drive hummer work through a triode, the work of low level hummer realizes functions such as warning, jingle bell and music.
Temperature sensor functionality exploitation: shown in figure 11, adopt the DS18B20 temperature sensor, temperature is measured and the result is shown in charactron or LCD liquid crystal display.
The communication function exploitation: 1, infrared radio communication, shown in Figure 12 A, 12B, intend IR remote controller with the infraluminescence pipe die, infrared receiving terminal is realized emission switch, carries out the exploitation of infrared radio communication function; Serial communication, shown in figure 13, realize the data communication of the utility model and host computer with the RS232 serial communication interface.
IIC and SPI functional development: shown in figure 14, through read-write operation, be familiar with the iic bus agreement, to reach the function of system development to 24C02 EEPROM storage chip; Shown in figure 15, the DS1302 real-time timepiece chip is the spi bus clock chip, through the read-write operation to DS1302, can be used to realize the SPI function development.
The rotary encoder functional development: shown in figure 16, rotary encoder is digital rotary switch, and FPGA judges the number of revolutions and the sense of rotation of rotary encoder through the data of gathering rotary encoder two output channels.In addition, also be furnished with of the expansion of an independent button on the rotary encoder for systemic-function.
The PS2 interface: shown in figure 17, extract two-way PS2 interface, the centre seals in 22 Ohmages coupling, to drawing on clock pin and the data pin, can realize the exploitation of PS2 keypad function through 1k resistance.As can realize the key assignments of charactron display keyboard.Be connected computor-keyboard with the utility model through PS2,, make further powerful of the utility model development function through obtaining a large amount of load buttons.
Expand I/O: shown in Figure 18 A, 18B, the utility model provides the I/O of 2 biserials 2 * 13 to expand pin, can supply the own development system of user, makes the function of the utility model strengthen greatly.
Keyboard and switching function exploitation: like Figure 19,20, shown in 21, the utility model is from being furnished with 4X4 matrix keyboard, 4 stand-alone keypad and 8 toggle switchs.Can realize basic I/O input and coding input, to satisfy the needs of system development.8 toggle switchs can be kept the characteristic of state, also are fit to do the judgement of system state.
A/D and the exploitation of D/A translation function: shown in figure 22, the utility model adopts AD and the DA modular converter with serial SPI communication interface, to save the utility model volume.Adopt 8 AD modules of serial TLC549, input end is connected on the wire jumper pin J8, carries out the input or the outside input of potentiometer through changing bouncing pilotage; Adopt 10 DA module TLC5615, wherein reference voltage is provided by TL431 output 2.5V, and the DA output terminal is connected on the wire jumper pin J7, independently output voltage signal.Change bouncing pilotage and can select to control LED brightness, perhaps directly output.
Power supply: shown in figure 23, the utility model converts 3.3v at power interface input 5v voltage to through LM1085-3.3, converts 1.2v to through lt1117-1.2 again, and three groups of power supply voltage supplying total systems forming are thus used.Every group of voltage all uses capacitor filtering, reduces power supply ripple, and it is stable to increase system performance.
More than be the preferred embodiment of the utility model, all changes of being done according to the utility model technical scheme when the function that is produced does not exceed the scope of the utility model technical scheme, all belong to the protection domain of the utility model.
Claims (4)
1. SOPC development platform based on Nios II system; It is characterized in that: comprise core board and the interface board that is connected with said core board, said core board is provided with fpga chip, SDRAM, FLASH, JTGA download interface, the ASP download interface of supporting Nios II soft-core processor, source crystal and core board external interface is arranged;
Said interface board is provided with said core board external interface and matches with interface, VGA display interface, LCD display interface, charactron, LED dot matrix screen, Multi-bit LED luminotron, hummer, temperature sensor, infrared radio communication module, serial ports, rotary encoder, expansion I/O mouth, keyboard, toggle switch, A/D and D/A, power interface, PS2 interface, USB interface, SPI interface and the IIC interface that is connected core board.
2. the SOPC development platform based on Nios II system according to claim 1 is characterized in that: said wireless communication module comprises infraluminescence pipe and the infrared receiving terminal that is used to simulate IR remote controller.
3. the SOPC development platform based on Nios II system according to claim 1 is characterized in that: be connected with the spi bus clock chip on the said IIC interface.
4. the SOPC development platform based on Nios II system according to claim 1 is characterized in that: be connected with the serial EEPROM storage chip on the said SPI interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205224833U CN202383658U (en) | 2011-12-14 | 2011-12-14 | SOPC (System-on-a-Programmable-Chip) development platform on basis of Nios II system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205224833U CN202383658U (en) | 2011-12-14 | 2011-12-14 | SOPC (System-on-a-Programmable-Chip) development platform on basis of Nios II system |
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| Publication Number | Publication Date |
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| CN202383658U true CN202383658U (en) | 2012-08-15 |
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| CN2011205224833U Expired - Fee Related CN202383658U (en) | 2011-12-14 | 2011-12-14 | SOPC (System-on-a-Programmable-Chip) development platform on basis of Nios II system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383710A (en) * | 2013-07-05 | 2013-11-06 | 燕山大学 | Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model |
| CN104732848A (en) * | 2015-02-12 | 2015-06-24 | 北京百科融创教学仪器设备有限公司 | Experimental box for EDA teaching development |
| CN105092922A (en) * | 2014-05-05 | 2015-11-25 | 西北工业大学 | Portable digital storage oscilloscope based on SOPC technology |
| CN105425028A (en) * | 2015-10-27 | 2016-03-23 | 中国电子科技集团公司第四十一研究所 | Microwave power measurer based on FPGA |
-
2011
- 2011-12-14 CN CN2011205224833U patent/CN202383658U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103383710A (en) * | 2013-07-05 | 2013-11-06 | 燕山大学 | Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model |
| CN105092922A (en) * | 2014-05-05 | 2015-11-25 | 西北工业大学 | Portable digital storage oscilloscope based on SOPC technology |
| CN104732848A (en) * | 2015-02-12 | 2015-06-24 | 北京百科融创教学仪器设备有限公司 | Experimental box for EDA teaching development |
| CN104732848B (en) * | 2015-02-12 | 2018-02-13 | 北京百科融创教学仪器设备有限公司 | EDA Instructional Development experimental boxs |
| CN105425028A (en) * | 2015-10-27 | 2016-03-23 | 中国电子科技集团公司第四十一研究所 | Microwave power measurer based on FPGA |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120815 Termination date: 20141214 |
|
| EXPY | Termination of patent right or utility model |