CN103354053A - Divided FPGA (Field Programmable Gate Array) experimental box - Google Patents

Abstract

The invention discloses a divided FPGA experimental box, relating to FPGA experimental boxes for teaching. A core plate is divided from a base plate in the experimental box, multiple pins are led from the base plate to the core plate, the core plate can be used independently or connected with another core plate, and the base plate employs a modularized design in which different modules are structurally and functionally independent from each other. The divided FPGA experimental box has the advantages that the experimental box can be used for teaching, scientific research and S&T competition of college students; is practical, advanced, pertinent and general; is helpful for training learning initiative, divergent thinking and operational ability of the students; and is easy and convenient to maintain/upload, wide in use range, flexible in operation and high in openness.

Description

A separate FPGA experiment box

technical field

The invention relates to an FPGA experiment box for teaching, in particular to a separate FPGA experiment box, which is suitable for digital system design experiments used in college teaching. the

Background technique

The development of computer technology and microelectronic technology has brought the design and application of modern digital systems into a new stage, and the traditional design methods have been gradually replaced by chip design based on advanced EDA technology. At present, learning digital system design technology, using large-scale and ultra-large-scale programmable logic devices FPGA and CPLD, mastering modern EDA technology and hardware description language have become the basic abilities that electronic designers must have. In order to adapt to this development, various technical colleges and universities have set up the "Digital System Design" course. The digital system design experiment box is an indispensable experimental device for this course. the

Because different colleges and universities have different specific goals for talent training, the same courses, teaching content and teaching focus will also be quite different. For example, the digital system design courses offered by colleges and universities mostly focus on the cultivation of students' practical operation ability, while undergraduate colleges and universities mostly focus on the mastery of students' basic theoretical knowledge and the cultivation of pioneering and innovative abilities. To this end, each university will directly purchase or make corresponding experimental equipment according to its own needs. the

Although the complete sets of digital system design teaching experiment devices sold on the market have various types and advanced technologies, they are universal because they have to take into account the experimental requirements of most users, but they do not have strong pertinence in combination with actual teaching requirements. This makes users face many difficulties in choosing when purchasing. In contrast, colleges and universities make their own experimental devices, and generally design the overall design of the experimental box according to the teaching emphases of their own departments and take into account the cost and various expenses. limitations. the

In addition, most of the digital system design teaching experiment boxes currently on the market adopt an integrated (closed) design (that is, pin binding between the core board and the bottom board) in structural design. This structure will greatly reduce the overall function of the experiment box. Flexibility, versatility and scalability are not conducive to the cultivation of students' learning initiative, pioneering thinking and innovative ability, and it is difficult to maintain and upgrade later. the

Contents of the invention

In order to solve the shortcomings of the above-mentioned prior art, the present invention provides a separate FPGA experiment box, which has wide application range, flexible operation, high openness, convenient maintenance and easy upgrade.

The present invention is realized by following technical scheme: a kind of separate FPGA experimental box, core board and base board adopt separate structure, described core board comprises FPGA chip and configuration chip connected with it respectively, a plurality of storage chips, a USB Controller, a network controller, 50MHZ crystal oscillator, 5V power interface, USB interface, UART interface, VGA interface, PS2 interface, AS download port, JTAG download port, reset button, configuration button, pin J5, pin J6;

The base plate includes a liquid crystal display module, a digital tube display module, an LED display, a serial AD module, a serial DA module, a user IO unit module, a plurality of dial switch unit modules, an LED light output unit module, a single Pulse source module, RS232 interface unit module, RS485 interface unit module, keyboard module, continuously adjustable pulse unit module, stepper motor module, traffic light module composed of red, yellow and green LEDs, power supply module, expansion interface slot, And the system IO jack. the

The core board leads a plurality of pins to the base board, and the core board is used independently or connected with the core board. The base board adopts a modular design, and each module is independent of each other in structure and function. the

The beneficial effects of the present invention are: it can be used in teaching, scientific research and college students' science and technology competitions, it is practical and advanced, and has pertinence and versatility, which is beneficial to the cultivation of students' learning initiative, divergent thinking and hands-on ability, and Maintenance and upgrade are simple and convenient; wide application range, flexible operation and high openness. the

Description of drawings

Fig. 1 is a structural representation of the present invention;

Figure 2 is the layout of the front panel of the core board;

Figure 3 is the layout of the back panel of the core board;

Fig. 4 is a schematic diagram of the control principle of the core board;

Fig. 5 is a schematic diagram of panel layout of the bottom plate.

Detailed ways

As shown in FIG. 1 , a separate FPGA experiment box includes two parts, a core board 1 and a bottom board 2 . These two parts are independent of each other. The core board leads to the base board with a total of 84 pins in the upper and lower rows. These 84 pins are connected to the corresponding slots on the base board. Through software design simulation and USB BLASTER emulator, the design circuit is burned to the main chip of the core board and the base board. The corresponding modules together realize the function of the designed circuit; for scientific research and college students' science and technology competition: the core board can be used independently, and can be used for scientific research and science and technology competition through the equipped large-capacity memory and rich interface circuits. the

As shown in Figures 2 and 3, the core board includes an FPGA chip and configuration chips connected to it respectively, a plurality of memory chips, a USB controller, a network controller, a 50MHZ crystal oscillator, a 5V power supply interface, and a USB interface. , UART interface, VGA interface, PS2 interface, AS download port, JTAG download port, reset key 3, configuration key 4, pin J5, pin J6. the

Wherein, the FPGA chip adopts Cyclone III EP3C25F324C8N FPGA chip, the configuration chip adopts 16Mb EPCS16SI16N configuration chip, and the multiple memory chips include two 256MB HY57V561620CT-6KOR SDRAMs, two 16MB AM29LV160DB-90EC type FLASH and two pieces of IS61LV25616AL-10TL type SRAM, the described USB controller adopts a USB 2.0 controller composed of a piece of CY7C68013A-56 and a piece of 24C02 E2PROM, and the described network controller adopts a 10M/ 100M network controller, 5V power interface, USB interface, UART interface adopt MAX3232, VGA interface adopts CY7C68013A-56PVXC; pin J5 and pin J6 use double rows of 42 pins each. the

A 16MB AM29LV160DB-90EC FLASH, a IS61LV25616AL-10TL SRAM, a 256MB HY57V561620CT-6KOR SDRAM, and double rows of 42 pins J5 and J6 are arranged on the back of the core board, and other modules are arranged on the core board. the front of the board. the

The core board is an independent core board, which can be used in combination with the bottom board or independently. The core board of this utility model is equipped with multiple memory chips (two pieces of 256MB HY57V561620CT-6KOR type SDRAM, two pieces of 16MB AM29LV160DB-90EC type FLASH and two pieces of IS61LV25616AL-10TL type SRAM) and one FPGA configuration chip EPCS16SI16N, and rich external interfaces including UART interface, USB interface, VGA interface, PS2 interface, AS download port, JTAG download port, network port, etc., can be used for secondary development (scientific research, electronic design competition, etc. ) and students learn to use after class. The schematic diagram of the working principle of the core board is shown in Figure 3. Since the Cyclone III EP3C25F324C8N FPGA chip has the characteristics of easy loss of data when it is powered off, it is equipped with an EPCS16SI16N chip so that it can be used as a configuration chip for storing programs when the AS download method is adopted. Exchange data with FPGA. At the same time, SDRAM and FLASH interact with FPGA in two-way data when large-capacity memory is required. In addition, EP3C25F324C8N FPGA chip is used as a control chip to control other functional chips to achieve corresponding functions, including: UART, VGA, USB, PS2, DM9000 wait. the

It should be pointed out that because the Cyclone III EP3C25F324C8N FPGA chip has its own small-capacity memory, when it is used in combination with the backplane, except for AD/DA experiments, which need to use these external memories, other basic experiments do not need Use these to configure the chip. However, it is essential when large-capacity storage is required. the

As shown in Figure 4, the liquid crystal display module adopts Chinese liquid crystal display module LCM12864ZK, the digital tube display module adopts 8-bit red common cathode digital tube display module, the LED display adopts 16×16 LED dot matrix display, and the serial AD module adopts 10-bit serial AD module, the serial DA module adopts a 10-bit serial DA module, there are 16 IO unit modules, 16 dial switch unit modules, and an 8-bit LED light output module for the light output unit module. There are 4 groups of single pulse source modules, the keyboard module adopts 4×4 matrix keyboard, the stepper motor module adopts 28YBJ-48 stepper motor, the traffic light module is composed of red, yellow and green LEDs, and the power module is composed of LT1086CM-3.3, AS1117 -2.5 and AMS1117-1.2, the expansion interface slot adopts 16PIN expansion interface slot, and the system IO jack adopts 24-bit system IO jack. the

In the bottom board, except for the pins of the LCD module, the traffic light module and the 16 lines of the 16X16 dot matrix display that have been fixedly connected to the pins of the FPGA chip on the core board, all other modules have IO jacks leading out to the outside. This kind of implementation makes the whole box highly open, and students can assign pins and wire independently according to their own wishes, which is helpful for the cultivation of students' learning initiative and divergent thinking. the

When designing a digital system, first use the EDA software for digital system development (supporting various versions of QUARTUSII) for circuit design on the computer, connect the PC to the core board of the experiment box through the USB port with a USB BLASTER cable, and connect the computer to the core board of the experiment box according to the design requirements. Connect the lead-out jack of the core board to the jack of the baseboard module with wires on the experiment box, and then execute the download and programming task on the computer software. After the download is successful, the circuit designed on the computer can be burned to the main board through the communication port. In the chip, finally test whether the function of the circuit meets the requirements on the bottom board of the experiment box or NIOS software. the

The separate Cyclone-3C25 FPGA teaching experiment box provided by the present invention uses Cyclone III EP3C25F324C8N chip as the CPU, and adopts the original design method of "independent core board + base plate" and "modular base plate", so that the experimental box has advanced It has the advantages of perfect function, high flexibility, good openness, strong expansibility, and easy maintenance and upgrade. the

1) All the IO ports of the experiment box are open to students. Students can try different types of control methods of the design module to help diverge students' design ideas. The IO port is fully open, which greatly improves the flexibility of the whole system and increases the hands-on space for students to do experiments;

2) The modular design of the bottom plate and the modularization of each hardware circuit maximize the overall stability of the system. At the same time, each part is relatively independent, and will not affect the normal operation of the entire experiment box due to damage to some hardware. At the same time, it simplifies the complexity of troubleshooting in the experimental box;

3) The design concept of "core board + experimental bottom box" greatly facilitates the subsequent upgrade of the experimental box. The core board can be changed flexibly. The upgrade of the entire experimental box can be completed only by replacing the core board, which can maximize the extension of the equipment. The service life is longer, and the design and manufacturing process is simplified, saving a lot of money;

4) The core board can be used independently. The design of the core board considers the convenience of use, and an independent power supply system is designed on the board, so that the core board can be directly used for secondary development (such as scientific research projects, student electronic design competitions), The core board is small in size, rich in interfaces, and easy to carry around. It can be combined with the experiment box for classroom learning, and students can take it back to continue learning after class;

5) In addition to the design of independent modules and independent core boards, which makes it easy to replace modules and core boards, the experiment box also reserves a set of expansion buses, which makes the experiment box have strong expansion performance. The previous experiment box can only Basic teaching cannot meet the requirements of innovative training; the new box allows students to master strong electrical hardware design skills and programming capabilities through the design of various extended function modules, not only have theoretical knowledge, but also have the ability to control physical objects.

Claims (5)

1. a separate FPGA experimental box, comprising a core board and a base plate installed in the casing; it is characterized in that: the core board and the base plate adopt a separate structure, and the core board includes an FPGA chip and configuration chips connected to it respectively, multiple A memory chip, a USB controller, a network controller, 50MHZ crystal oscillator, 5V power interface, USB interface, UART interface, VGA interface, PS2 interface, AS download port, JTAG download port, reset button, configuration button, pin J5 , pin J6; the base plate includes a liquid crystal display module, a digital tube display module, an LED display, a serial AD module, a serial DA module, a plurality of user IO unit modules, a plurality of DIP switch unit modules, LED lights Output unit module, single pulse source module, RS232 interface unit module, RS485 interface unit module, keyboard module, continuously adjustable pulse unit module, stepper motor module, traffic light module composed of red, yellow and green LEDs, power supply module , an expansion interface slot, and a system IO jack; the core board leads a plurality of pins to the base board, and the core board is used independently or connected with the core board, and the base board adopts a modular design, and each module is structurally and functionally independent of each other. 2. a kind of separate FPGA experimental box according to claim 1, is characterized in that: described FPGA chip adopts Cyclone III EP3C25F324C8N type FPGA chip; Described configuration chip adopts the EPCS16SI16N type configuration chip of 16Mb; Described Multiple memory chips include two 256MB HY57V561620CT-6KOR SDRAMs, two 16MB AM29LV160DB-90EC FLASHs and two IS61LV25616AL-10TL SRAMs; the USB controller is composed of one CY7C68013A-56 and one 24C02 E2PROM USB 2.0 controller; the network controller adopts 10M/100M network controller composed of DM9000AE; the UART interface adopts MAX3232; the VGA interface adopts CY7C68013A-56PVXC, pin J5 and pin J6 are both double-row 42 Pin. 3. A separate FPGA experiment box according to claim 2, characterized in that: one piece of 16MB AM29LV160DB-90EC type FLASH, one piece of IS61LV25616AL-10TL type SRAM, one piece of 256MB HY57V561620CT-6KOR type SDRAM and two rows of 42 A pin J5 and a pin J6 are arranged on the back of the core board, and other modules are arranged on the front of the core board. 4. A kind of separate FPGA experiment box according to claim 1, characterized in that: the liquid crystal display module adopts Chinese liquid crystal display module LCM12864ZK, the digital tube display module adopts 8 red common cathode digital tube display modules, and the LED display adopts The 16×16 LED dot matrix display adopts, the serial AD module adopts a 10-bit serial AD module, the serial DA module adopts a 10-bit serial DA module, there are 16 IO unit modules, and the dial switch unit module has 16, the lamp output unit module adopts 8-bit LED lamp output module, the single pulse source module has 4 groups, the keyboard module adopts 4×4 matrix keyboard, the stepper motor module adopts 28YBJ-48 stepper motor, and the traffic light module is composed of red It is composed of three kinds of yellow and green LEDs. The power module is composed of LT1086CM-3.3, AS1117-2.5 and AMS1117-1.2. The expansion interface slot adopts 16PIN expansion interface slot, and the system IO jack adopts 24-bit system IO jack. 5. a kind of separate FPGA experimental box according to claim 4, is characterized in that: the pin of 16 row lines of liquid crystal display module and traffic light module and 16X16 dot matrix display screen in the base plate has been connected with the FPGA of core board The chip pins are fixedly connected, and other modules have external IO jacks.

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