CN103354053A - Divided FPGA (Field Programmable Gate Array) experimental box - Google Patents
Divided FPGA (Field Programmable Gate Array) experimental box Download PDFInfo
- Publication number
- CN103354053A CN103354053A CN2013102879150A CN201310287915A CN103354053A CN 103354053 A CN103354053 A CN 103354053A CN 2013102879150 A CN2013102879150 A CN 2013102879150A CN 201310287915 A CN201310287915 A CN 201310287915A CN 103354053 A CN103354053 A CN 103354053A
- Authority
- CN
- China
- Prior art keywords
- module
- adopts
- interface
- experimental box
- core board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Electrically Operated Instructional Devices (AREA)
Abstract
The invention discloses a divided FPGA experimental box, relating to FPGA experimental boxes for teaching. A core plate is divided from a base plate in the experimental box, multiple pins are led from the base plate to the core plate, the core plate can be used independently or connected with another core plate, and the base plate employs a modularized design in which different modules are structurally and functionally independent from each other. The divided FPGA experimental box has the advantages that the experimental box can be used for teaching, scientific research and S&T competition of college students; is practical, advanced, pertinent and general; is helpful for training learning initiative, divergent thinking and operational ability of the students; and is easy and convenient to maintain/upload, wide in use range, flexible in operation and high in openness.
Description
Technical field
The present invention relates to a kind of teaching FPGA experimental box, specifically a kind of separate type FPGA experimental box is applicable to the Design of Digital System experiment usefulness that college teaching is used.
Background technology
The development of computer technology and microelectronic technique, so that the design of Modern Digital System and application have entered the new stage, traditional method for designing is progressively replaced by the chip design based on advanced EDA technology.At present, association's Design of Digital System technology is used extensive, ultra-large programmable logic device (PLD) FPGA and CPLD, and grasp Modern EDA Technology and hardware description language have become is engaged in the basic capacity that the Electronic Design personnel must have.In order to adapt to this development, each is special, these engineering and polytechnic universities offer " Design of Digital System " course one after another.The Design of Digital System experimental box then is to be the matching used requisite experimental provision of this course.
Because different colleges and universities are different to the objectives of personnel training, so identical course, the content of courses and focal points also can differ widely.Such as, the Design of Digital System course that academy offers lays particular emphasis on the cultivation of students ' actual situation functipnal capability more, and universities and colleges of undergraduate course are mainly with grasp and the ability training of pioneering and inventing of paying attention to student's basic theoretical knowledge.For this reason, corresponding experimental facilities is directly purchased or made by oneself to each high school meeting attended by all faculty and students according to the demand of self.
The complete Design of Digital System experiment device for teaching of selling on the market, although of a great variety, advanced technology because will take into account most of users' requirement of experiment, thereby possesses ubiquity, but does not possess the strong specific aim in conjunction with the field research requirement.This is so that the user when buying, can face a lot of selection difficulties.Relatively, colleges and universities make this experimental provision by oneself, and generally according to the teaching emphasis of own department and take into account cost and various expense is carried out the experimental box global design, this is only applicable to the court's teaching so that the experimental provision usable range is narrow, has significant limitation.
In addition, the Design of Digital System Teaching Experiment Box of selling on the market at present on structural design more adopts integrated (closed) design (namely, core board and backplane pin binding), this structure can reduce dirigibility, versatility and the extendability of experimental box allomeric function greatly, thereby be unfavorable for the cultivation of Students ' Learning initiative, open up thinking and innovation ability, and later period maintenance is all relatively more difficult with upgrading.
Summary of the invention
In order to solve the shortcoming of above-mentioned prior art, the invention provides a kind of separate type FPGA experimental box, usable range is wide, flexible operation, open high, easy to maintenance, upgrading easily
The present invention realizes with following technical scheme: a kind of separate type FPGA experimental box, core board and base plate adopt separate type, and described core board comprises fpga chip and connected configuring chip, a plurality of storage chip, a USB controller, network controller, 50MHZ crystal oscillator, 5V power interface, USB interface, UART interface, VGA interface, PS2 interface, an AS download mouth, JTAG download mouth, reset key, configuration button, contact pin J5, contact pin J6 respectively;
Described base plate comprises LCD MODULE, the charactron display module, LED display, the serial AD module, serial D A module, individual user IO unit module, a plurality of toggle switch unit modules, LED lamp output unit module, the single pulse source module, RS232 interface unit module, RS485 interface unit module, Keysheet module, continuous adjustable pulse unit module, the stepper motor module, the traffic lights module that is consisted of by the green three kinds of LED of reddish yellow, power module, the expansion interface slot, and the IO of system jack.
Described core board is drawn a plurality of pins to base plate, and core board independently uses or is connected use with core board, and described base plate adopts modular design, and each module is independent mutually on 26S Proteasome Structure and Function.
The invention has the beneficial effects as follows: can be used in teaching, scientific research and the contest of university student's science and technology, has practicality with advanced, pointed and versatility is conducive to the cultivation of Students ' Learning initiative, divergent thinking and manipulative ability again, and it is simple and convenient to keep in repair, upgrade; Usable range is wide, flexible operation, open high.
Description of drawings
Fig. 1 is structural representation of the present invention;
Fig. 2 is core board front panel arrangenent diagram;
Fig. 3 is core board reverse side panel layout;
Fig. 4 is the control principle schematic diagram of core board;
Fig. 5 is the panel arrangement schematic diagram of base plate.
Embodiment
As shown in Figure 1, a kind of separate type FPGA experimental box comprises core board 1 and base plate 2 two parts.These two parts are separate.Core board is drawn two rows totally 84 pins to base plate, link to each other with the corresponding slot of base plate by these 84 pins, by Software for Design emulation and USB BLASTER emulator, design circuit is burnt the core board master chip, and the common function that realizes designed circuit of the corresponding module of base plate; Be used for the contest of scientific research and university student science and technology: core board can independently use, and by the mass storage of outfit and abundant interface circuit, can be used for scientific research and scientific and technological contest.
As shown in Figures 2 and 3, described core board comprises fpga chip and respectively connected type configuring chip, a plurality of storage chip, USB controller, network controller, 50MHZ crystal oscillator, 5V power interface, USB interface, UART interface, VGA interface, PS2 interface, an AS download mouthful, JTAG downloads mouth, reset key 3, configures button 4, contact pin J5, contact pin J6.
Wherein, described fpga chip adopts Cyclone III EP3C25F324C8N type fpga chip, described configuring chip adopts the EPCS16SI16N type configuring chip of 16Mb, described a plurality of storage chip comprises the HY57V561620CT-6KOR type SDRAM of two 256MB, the AM29LV160DB-90EC type FLASH of two 16MB and two IS61LV25616AL-10TL type SRAM, described USB controller adopts USB 2.0 controllers that are made of a slice CY7C68013A-56 and a slice 24C02 E2PROM, described network controller adopts the 10M/100M network controller that is made of DM9000AE, the 5V power interface, USB interface, the UART interface adopts MAX3232, and the VGA interface adopts CY7C68013A-56PVXC; Contact pin J5 and contact pin J6 all adopt double each 42 contact pin.
The AM29LV160DB-90EC type FLASH of a slice 16MB, the HY57V561620CT-6KOR type SDRAM of a slice IS61LV25616AL-10TL type SRAM, a slice 256MB and double each 42 contact pin J5 and contact pin J6 are arranged in the back side of core board, and all the other each module arrangement are in the front of core board.
Described core board is the individual core core, both can be used in combination with described base plate, also can independently use.The utility model core board considers to require the occasion of mass storage, is furnished with a plurality of storage chips (HY57V561620CT-6KOR type SDRAM of two 256MB, the AM29LV160DB-90EC type FLASH of two 16MB and two IS61LV25616AL-10TL type SRAM) and a FPGA configuring chip EPCS16SI16N, and comprise the UART interface, USB interface, the VGA interface, the PS2 interface, AS downloads mouth, JTAG downloads mouth, network interfaces etc. can be used for secondary development (scientific research at interior abundant external interface, Electronic Design Competition etc.) and behind the students in class voluntarily study use.The principle of work schematic diagram of described core board as shown in Figure 3, because Cyclone III EP3C25F324C8N type fpga chip has the characteristic of the easy obliterated data of power down, so be equipped with the EPCS16SI16N chip so that when adopting the AS downloading mode, the configuring chip of using as storage program is with the mutual swap data of FPGA.Simultaneously, needing the occasion of mass storage, it is mutual that SDRAM and FLASH and FPGA carry out data double-way, in addition, EP3C25F324C8N type fpga chip is controlled other functional chips as control chip and is realized corresponding function, comprising: UART, VGA, USB, PS2, DM9000 etc.
It is to be noted, because Cyclone III EP3C25F324C8N type fpga chip inside carries small-capacity memory, so when being used in combination with base plate, except the AD/DA experiment, need to use outside these outer storeies of joining, other infrastest does not all need to use these configuring chips.But needing the occasion of mass storage, then be absolutely necessary.
As shown in Figure 4, LCD MODULE adopts Chinese fonts lcd module LCM12864ZK, the charactron display module adopts 8 red common cathode charactron display modules, LED display adopts 16 * 16 LED dot matrix display screens to adopt, the serial AD module adopts 10 bits serial A/D modules, described serial D A module adopts 10 bit serial DA modules, the IO unit module has 16, the toggle switch unit module has 16, lamp output unit module adopts 8 LED lamp output modules, the single pulse source module has 4 groups, Keysheet module adopts 4 * 4 matrix keyboards, the stepper motor module adopts the 28YBJ-48 stepper motor, the traffic lights module is made of the green three kinds of LED of reddish yellow, power module is by LT1086CM-3.3, AS1117-2.5 and AMS1117-1.2 consist of, the expansion interface slot adopts the expansion interface slot of 16PIN, and system IO jack adopts 24 IO of system jacks.
In the base plate, except the pin of LCD MODULE and 16 lines of traffic lights module and 16X16 dot matrix display screen is fixedly connected with the fpga chip pin of core board, other module all has the IO jack of externally drawing, this implementation, so that whole chest opening is high, the student can distribute pin voluntarily according to the wish of oneself, from main electrical scheme, helps the cultivation of Students ' Learning initiative and divergent thinking.
When carrying out Design of Digital System, eda software (supporting each version of QUARTUSII) with the exploitation digital display circuit carries out circuit design at first on computers, PC is linked to each other with the experimental box core board by the USB mouth with USB BLASTER line, and link to each other with the jack of floor module with the jack of drawing of wire with core board on experimental box by designing requirement, then carry out at computer software and download programmed tasks, after downloading successfully, the circuit that can will design on computers burns in the master chip by communication port, and whether the function of test circuit meets the demands on experimental box base plate or NIOS software at last.
Separate type Cyclone-3C25 type FPGA Teaching Experiment Box provided by the invention, select Cyclone III EP3C25F324C8N cake core to serve as CPU, adopt " individual core core+base plate " and the method for designing of " floor module " of original creation, so that this experimental box has advance and practicality, the while is pointed and versatility again; Have perfect in shape and function, dirigibility is high, open good, extendability is strong, and for ease of maintenaince with upgrading etc. advantage.
1) all IO mouths of experimental box are all opened the student, and the student can attempt the dissimilar control method of design module, helps to disperse student's mentality of designing.IO mouth Full-open is greatly improved the dirigibility of whole system, has increased the space of starting the when student does experiment;
2) design of floor module, the equal modularization of each hardware circuit, the at utmost very high resistance to overturning of system, each several part is relatively independent simultaneously, can not affect because of the damage of a part of hardware the normal operation of whole experimental box.Simplified simultaneously experimental box malfunction elimination complexity;
3) design concept of " core board+experiment under casing ", greatly facilitate the follow-up upgradability of experimental box, core board can be changed flexibly, only needs replacing core board just can be finished the upgrading to whole experimental box, to greatest extent tenure of use of extension device and simplified and design and produce technique, save substantial contribution;
4) core board can independently use, consider easy to use during the core board design, designed onboard independently electric supply system, so just can directly take core board to carry out secondary development (such as scientific research project, student's Electronic Design Competition), the core board size is little, rich interface, be convenient to carry, can accomplish that the classroom learns in conjunction with experimental box, can allow after class student's continue studying of taking home;
5) except the design of standalone module and individual core core, so that outside module and the core board replacing conveniently, experimental box has also been reserved one group of expansion bus, so that this experimental box has stronger scalability, experimental box in the past can only carry out elementary teaching, can not satisfy the requirement of innovation real training; New chest not only has theoretical knowledge so that the student can grasp stronger electric class hardware design technical ability and programming capability by the various extended function modules of design, also possesses control ability in kind simultaneously.
Claims (5)
1. a separate type FPGA experimental box comprises being installed in casing kernel core and base plate; It is characterized in that: core board and base plate adopt separate type, and described core board comprises fpga chip and connected configuring chip, a plurality of storage chip, a USB controller, network controller, 50MHZ crystal oscillator, 5V power interface, USB interface, UART interface, VGA interface, PS2 interface, an AS download mouth, JTAG download mouth, reset key, configuration button, contact pin J5, contact pin J6 respectively; Described base plate comprises LCD MODULE, the charactron display module, LED display, the serial AD module, serial D A module, a plurality of user IO unit modules, a plurality of toggle switch unit modules, LED lamp output unit module, the single pulse source module, RS232 interface unit module, RS485 interface unit module, Keysheet module, continuous adjustable pulse unit module, the stepper motor module, the traffic lights module that is consisted of by the green three kinds of LED of reddish yellow, power module, the expansion interface slot, and the IO of system jack; Core board is drawn a plurality of pins to base plate, and described core board independently uses or is connected use with core board, and described base plate adopts modular design, and each module is independent mutually on 26S Proteasome Structure and Function.
2. a kind of separate type FPGA experimental box according to claim 1 is characterized in that: described fpga chip employing Cyclone III EP3C25F324C8N type fpga chip; Described configuring chip adopts the EPCS16SI16N type configuring chip of 16Mb; Described a plurality of storage chip comprises AM29LV160DB-90EC type FLASH and two IS61LV25616AL-10TL type SRAM of the HY57V561620CT-6KOR type SDRAM of two 256MB, two 16MB; Described USB controller adopts USB 2.0 controllers that are made of a slice CY7C68013A-56 and a slice 24C02 E2PROM; Described network controller adopts the 10M/100M network controller that is made of DM9000AE; The UART interface adopts MAX3232; The VGA interface adopts CY7C68013A-56PVXC, and contact pin J5 and contact pin J6 all adopt double each 42 contact pin.
3. a kind of separate type FPGA experimental box according to claim 2, it is characterized in that: the AM29LV160DB-90EC type FLASH of a slice 16MB, the HY57V561620CT-6KOR type SDRAM of a slice IS61LV25616AL-10TL type SRAM, a slice 256MB and double each 42 contact pin J5 and contact pin J6 are arranged in the back side of core board, and all the other each module arrangement are in the front of core board.
4. a kind of separate type FPGA experimental box according to claim 1, it is characterized in that: LCD MODULE adopts Chinese fonts lcd module LCM12864ZK, the charactron display module adopts 8 red common cathode charactron display modules, LED display adopts 16 * 16 LED dot matrix display screens to adopt, the serial AD module adopts 10 bits serial A/D modules, described serial D A module adopts 10 bit serial DA modules, the IO unit module has 16, the toggle switch unit module has 16, lamp output unit module adopts 8 LED lamp output modules, the single pulse source module has 4 groups, Keysheet module adopts 4 * 4 matrix keyboards, the stepper motor module adopts the 28YBJ-48 stepper motor, the traffic lights module is made of the green three kinds of LED of reddish yellow, power module is by LT1086CM-3.3, AS1117-2.5 and AMS1117-1.2 consist of, the expansion interface slot adopts the expansion interface slot of 16PIN, and system IO jack adopts 24 IO of system jacks.
5. a kind of separate type FPGA experimental box according to claim 4, it is characterized in that: the pin of LCD MODULE and 16 lines of traffic lights module and 16X16 dot matrix display screen is fixedly connected with the fpga chip pin of core board in the base plate, and other module all has the IO jack of externally drawing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102879150A CN103354053A (en) | 2013-07-09 | 2013-07-09 | Divided FPGA (Field Programmable Gate Array) experimental box |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102879150A CN103354053A (en) | 2013-07-09 | 2013-07-09 | Divided FPGA (Field Programmable Gate Array) experimental box |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103354053A true CN103354053A (en) | 2013-10-16 |
Family
ID=49310415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102879150A Pending CN103354053A (en) | 2013-07-09 | 2013-07-09 | Divided FPGA (Field Programmable Gate Array) experimental box |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103354053A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN104882053A (en) * | 2015-06-12 | 2015-09-02 | 安徽师范大学 | Multifunctional teaching apparatus |
| CN111554163A (en) * | 2020-06-18 | 2020-08-18 | 苏州东奇信息科技股份有限公司 | Modular universal electrical teaching experiment platform based on custom bus |
| CN113658494A (en) * | 2021-08-26 | 2021-11-16 | 浙江理工大学科技与艺术学院 | Experimental teaching device based on embedded development |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020095619A (en) * | 2001-06-15 | 2002-12-28 | 주식회사 마이다스엔지니어링 | ASIC design trainer |
| JP2003156995A (en) * | 2001-11-20 | 2003-05-30 | Andor System Support Co Ltd | Remote education system for experiment and practice of digital circuit |
| CN2891165Y (en) * | 2006-05-23 | 2007-04-18 | 武汉大学 | Embedded automatic electronic design multi-functional innovative experiment platform |
| CN2916813Y (en) * | 2006-06-05 | 2007-06-27 | 杭州浙大辰光科技有限公司 | Integrated experiment table for numerical control system |
| CN201100900Y (en) * | 2007-09-17 | 2008-08-13 | 北京博创兴业科技有限公司 | Built-in system teaching instrument based on programmable system chip |
| CN201319226Y (en) * | 2008-10-31 | 2009-09-30 | 北京奥尔斯电子科技有限公司 | Embedded teaching experimental system |
| CN201820383U (en) * | 2010-09-16 | 2011-05-04 | 深圳信息职业技术学院 | FPGA (field programmable gate array) teaching system |
| CN202110705U (en) * | 2011-03-10 | 2012-01-11 | 天津芯慧鸿业科技发展有限公司 | Portable design detection experiment platform for single-chip microcomputer system |
| CN202473034U (en) * | 2011-08-26 | 2012-10-03 | 北京亿旗创新科技发展有限公司 | Multi-project modularized electronic design comprehensive innovation training platform |
| CN202917070U (en) * | 2012-10-26 | 2013-05-01 | 中国电子科技集团公司第四十七研究所 | Extensible interface type FPGA verification and development board |
| CN203397577U (en) * | 2013-07-09 | 2014-01-15 | 江苏师范大学 | Separated FPGA experiment case |
-
2013
- 2013-07-09 CN CN2013102879150A patent/CN103354053A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020095619A (en) * | 2001-06-15 | 2002-12-28 | 주식회사 마이다스엔지니어링 | ASIC design trainer |
| JP2003156995A (en) * | 2001-11-20 | 2003-05-30 | Andor System Support Co Ltd | Remote education system for experiment and practice of digital circuit |
| CN2891165Y (en) * | 2006-05-23 | 2007-04-18 | 武汉大学 | Embedded automatic electronic design multi-functional innovative experiment platform |
| CN2916813Y (en) * | 2006-06-05 | 2007-06-27 | 杭州浙大辰光科技有限公司 | Integrated experiment table for numerical control system |
| CN201100900Y (en) * | 2007-09-17 | 2008-08-13 | 北京博创兴业科技有限公司 | Built-in system teaching instrument based on programmable system chip |
| CN201319226Y (en) * | 2008-10-31 | 2009-09-30 | 北京奥尔斯电子科技有限公司 | Embedded teaching experimental system |
| CN201820383U (en) * | 2010-09-16 | 2011-05-04 | 深圳信息职业技术学院 | FPGA (field programmable gate array) teaching system |
| CN202110705U (en) * | 2011-03-10 | 2012-01-11 | 天津芯慧鸿业科技发展有限公司 | Portable design detection experiment platform for single-chip microcomputer system |
| CN202473034U (en) * | 2011-08-26 | 2012-10-03 | 北京亿旗创新科技发展有限公司 | Multi-project modularized electronic design comprehensive innovation training platform |
| CN202917070U (en) * | 2012-10-26 | 2013-05-01 | 中国电子科技集团公司第四十七研究所 | Extensible interface type FPGA verification and development board |
| CN203397577U (en) * | 2013-07-09 | 2014-01-15 | 江苏师范大学 | Separated FPGA experiment case |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104616574A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | FPGA (field programmable gate array) removable high-speed operation verification development board |
| CN104616574B (en) * | 2015-01-28 | 2017-11-10 | 山东华翼微电子技术股份有限公司 | A kind of FPGA is dismantled and assembled and the checking development board of high-speed cruising |
| CN104882053A (en) * | 2015-06-12 | 2015-09-02 | 安徽师范大学 | Multifunctional teaching apparatus |
| CN104882053B (en) * | 2015-06-12 | 2017-10-17 | 安徽师范大学 | A kind of multifunction teaching instrument |
| CN111554163A (en) * | 2020-06-18 | 2020-08-18 | 苏州东奇信息科技股份有限公司 | Modular universal electrical teaching experiment platform based on custom bus |
| CN113658494A (en) * | 2021-08-26 | 2021-11-16 | 浙江理工大学科技与艺术学院 | Experimental teaching device based on embedded development |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202563782U (en) | Singlechip experiment teaching development system | |
| CN201117149Y (en) | Programmable experiment development device of modularization design | |
| CN203520727U (en) | Portable STM32 one-chip microcomputer teaching experiment instrument | |
| CN103354053A (en) | Divided FPGA (Field Programmable Gate Array) experimental box | |
| CN203397577U (en) | Separated FPGA experiment case | |
| CN104778885A (en) | Digital circuit experiment system and method based on programmable logic device | |
| CN204990931U (en) | Singlechip experimental apparatus with wireless sensor network transmit system | |
| CN103093672A (en) | Portable electronic technology experimental box | |
| CN203376909U (en) | Novel microcomputer principle and interface experiment system based on FPGA | |
| CN201984696U (en) | Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board | |
| CN202502660U (en) | Programmable digital logic circuit basic experiment plate | |
| CN217306014U (en) | Non-code hand-held programming device | |
| CN201177909Y (en) | Experiment circuit developing platform based on programmable logic device | |
| CN201100900Y (en) | Built-in system teaching instrument based on programmable system chip | |
| CN203706496U (en) | Double layer combined type single chip microcomputer learning board | |
| CN202534200U (en) | Experiment system based on CPLD/FPGA module | |
| CN202171889U (en) | Portable universal CPLD/FPGA teaching experimental instrument | |
| CN202650370U (en) | Design and teaching platform for embedded system | |
| CN202171892U (en) | Teaching platform for digital system design | |
| CN202956971U (en) | Novel singlechip practical training box | |
| CN201156341Y (en) | Multifunctional experiment development and teaching apparatus based on DSP chip | |
| CN210091512U (en) | Replaceable modular FPGA (field programmable Gate array) experiment board for core board | |
| CN202373179U (en) | Novel microcomputer interface experiment platform based on PCI and FPGA | |
| CN202258050U (en) | Novel digital electronic technology and single chip comprehensive experiment box | |
| CN203535872U (en) | Experiment platform integrated with DSP, single-chip microcomputer and CPLD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131016 |