CN201984696U - Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board - Google Patents

Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board Download PDF

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Publication number
CN201984696U
CN201984696U CN2011200203629U CN201120020362U CN201984696U CN 201984696 U CN201984696 U CN 201984696U CN 2011200203629 U CN2011200203629 U CN 2011200203629U CN 201120020362 U CN201120020362 U CN 201120020362U CN 201984696 U CN201984696 U CN 201984696U
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China
Prior art keywords
module
communication
download
programmable logic
display module
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CN2011200203629U
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Chinese (zh)
Inventor
徐成
王奕
曾娟丽
方凯晴
刘彦
杨志邦
田峥
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湖南大学
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Priority to CN2011200203629U priority Critical patent/CN201984696U/en
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Publication of CN201984696U publication Critical patent/CN201984696U/en

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Abstract

The utility model relates to a portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board which comprises a universal serial bus interface, a drive circuit module, an electrically-erasable module, a communication/downloading module, a frequency adjustable clock module, a dial switch module, a field programmable gate array, a pulse switch module, a diode display module and a nixie tube display module. The drive circuit module connected with the universal serial bus interface is in two-way connection with the electrically-erasable module and the communication/downloading module respectively, the communication/downloading module is in two-way connection with field programmable gate array and the frequency adjustable clock module, the frequency adjustable clock module, the frequency adjustable clock module and the pulse switch module are all connected with the field programmable gate array, and the field programmable gate array is also connected with the diode display module and the nixie tube display module. The universal serial bus interface integrates a power supply, downloading and communication, and a communication function module enables the portable universal digital logic design and EDA comprehensive experimental board to carry out data interaction on other universal microcontrollers as a coprocessor.

Description

Portable general Logical Design and EDA Comprehensive Experiment plate
Technical field
The utility model belongs to the application of electronic technology field, relates to the experiment porch of a kind of portable general Logical Design and EDA comprehensive Design.
Background technology
DLC (digital logic circuit) is the basic course that computing machine, electronics, communication class specialty are crossed the threshold aspect electronic technology.This course has system and the very strong practicality of himself.DLC (digital logic circuit) is a subject of the storage of research digital signal, conversion and computing, so this course not merely requires the student to grasp its substance and requires the student that stronger practical operation and manipulative ability are arranged.The content of courses of DLC (digital logic circuit) course is in the bottom in the computing machine hierarchical structure, belongs to the kernel of computing machine, is the basis that constitutes computing machine and other digital display circuit.And the development of logical device plays decisive role to the development and the update of computing machine.Along with the fast development of EDA and FPGA technology, DLC (digital logic circuit) curriculum experiment link has now developed into experiment porch based on FPGA from original bread board, gate circuit and simple combinatorial logic chip.Advantage based on the experiment porch of FPGA is, it is erasable, reusable to programme, to can intuitively be implemented on the FPGA after the logical design compiling, reduced is the danger of experiment porch with the bread board before, and can allow the student recognize the overall process of complicated circuit design, these are irreplaceable based on the experiment porch institute of simple combinatorial logic chip before all being.
In recent years, the experiment porch based on FPGA is selected by increasing colleges and universities in the experimental teaching of Logical Design, but present experiment porch has a lot of deficiencies: (1) volume is big, carries inconvenience, can only experimentize in fixing laboratory; (2) inconvenience of communicating by letter with PC needs external communication switching card; (3) cost height need to be bought supporting power lead, is downloaded line and communication switching card, for the student everyone one require cost too high.
Traditional EDA experiment porch often can only be used for program and download checking, and the micro controller of can not directly communicating by letter with other is carried out data interaction because communication is inconvenient.When for example designing a wave filter and verifying with FPGA, if there is not communication function, then a large amount of input data of wave filter can't direct control and checking with the output result.
Simultaneously, colleges and universities are for realizing cultivating this target of the novelty talent, constantly advance the reform and the innovation of teaching pattern in recent years, enlarge university student's engineering design and innovation training scale, with the chain-type practical teaching talents cultivating mode that forms " teachining only the essential and ensure plenty of practice-learning by doing-the innovation training " efficient hardening students ' practical ability, cultivates the innovation talent.Yet, in traditional teaching Process of experiment, a plurality of students use an experimental box, the continuous expansion and the experiment porch price of propelling, enrollment scale of adding the practice innovation teaching pattern is more expensive, experimental facilities has been in state in short supply comparatively speaking, can not satisfy one of each student's demand at all.
The utility model content
The technical problems to be solved in the utility model is, at the existing problem of existing Experiment of Digital Logic platform, these problems comprise needs purchase specific download line, the power source special line, the trouble and the extra cost that need dependence communication switching to stick into row communication and bring, volume carries inconvenience greatly, the cost height can't satisfy one of each student's in the present novelty teaching reform demand, design a kind of portable general Logical Design and EDA Comprehensive Experiment plate, its download, communication only needs a UBS line with power supply, has coprocessor functions, small and exquisite portable, the cost performance height, simple and practical.
The technical scheme that the utility model adopted is: described portable general Logical Design comprises USB (universal serial bus) (USB), drive circuit module, electrically-erasable module with EDA Comprehensive Experiment plate, communicates by letter/download module, frequency adjustable clock module, toggle switch module, field programmable logic array (FPLA) (FPGA), pulse switch module, diode display module and charactron display module; Its design feature is, the drive circuit module that connects USB (universal serial bus) is respectively with electrically-erasable module and the two-way connection of communication/download module, communication/download module is with the two-way connection of field programmable logic array (FPLA), the frequency adjustable clock module of the two-way connection of communication/download module and toggle switch module, pulse switch module all insert field programmable logic array (FPLA) together, field programmable logic array (FPLA) also is connected to diode display module and charactron display module, and the toggle switch module connects diode display module.
Below the utility model made further specify.
The utility model is provided with field programmable logic array (FPLA) (FPGA); FPGA has been connected to communication protocol integrated and FPGA downloads communicating by letter/download module of logic, and this module with communication function makes it can be used as coprocessor and other general micro controller are carried out data interaction; And the driving of USB (universal serial bus) is solidificated in the drive circuit module that joins with USB, the download of USB interface collection FPGA net meter file, serial data communication and single power supply are powered at one and do not need extra specific download line.
Characteristics of the present utility model have:
(1) volume is little, and (the about 12cm*8cm of area) easy to carry avoided going fixing laboratory to do the trouble of experiment thereby can experimentize at dormitory, saved the laboratory expense simultaneously, is particularly suitable for promoting opening experiment in the undergraduate course teaching;
(2) cost is low, does not need to buy power source special line, specific download line and communication switching card, and cost is lower than 150 yuan, can satisfy the demand of one of student's staff fully, helps guiding and promote the student to participate in the interest of practical training;
(3) download of USB interface collection FPGA net meter file, serial data communication and single power supply are powered at one, need not external power source special line and download line, and be easy to use, and the student only needs a USB connecting line can use this utility model;
(4) coprocessor/element characteristics, the USB interface of utility model directly can be used for its with PC between communicate by letter, do not need to connect the communication switching card, therefore, this utility model can also be carried out data interaction as coprocessor and other general micro controller except the functional verification that can be used for experimental design;
(5) the frequency adjustable clock module combines with the pulse switch module, and the pulse switch module can manually generate clock signal and provide convenience for the commissioning test program, and the frequency adjustable clock signal provides convenience for the design of complex digital system;
(6) logical resource is abundant, be specially adapted to computing machine, communication speciality, the I/O interface of FPGA all adopts with the input and output device fixedlys connected, under FPGA limited resources condition, connect to greatest extent and go up input and output device as much as possible, make this experiment porch can satisfy contrived experiment fully, and extend on the innovation training problems such as expanding to the integrated electronics design always from simple digital circuit to the complex digital system.
Developing thought of the present utility model is, at Logical Design education experiment, engineering design, innovation training and scientific and technological contest active demand to portable low-cost experiment porch, a portable EDA experiment porch of design, one of each student can be satisfied fully, colleges and universities' experiment porch problem in short supply can be solved well.
The more important thing is, the communication of USB interface collection, download and the single power supply of the utility model design are powered at one, do not need to buy power source special and specific download line, this utility model makes it can be used as coprocessor by communicating between USB interface and the PC simultaneously, and as the proof of algorithm coprocessor: the result exported PC to after PC was sent to experimental data algorithm among the FPGA and carried out computing.Therefore it is compared with traditional EDA experiment porch, the USB interface collection communication of this utility model, download and be powered at one, make its cost reduce, use convenient greatly, and volume is little, easy to carry and make the student experimenting place may extend to dormitory, do experiment and needn't arrive special laboratory, saved breadboard expense to a great extent.
As known from the above, the utility model is a kind of portable general Logical Design and EDA Comprehensive Experiment plate, its download, communication and power supply only USB line of need, have coprocessor functions, small and exquisite portable, cost performance is high, simple and practical.
Description of drawings
Fig. 1 is a circuit structure diagram of the present utility model;
Fig. 2 is a theory structure block diagram of the present utility model;
Fig. 3 is an Application Design FB(flow block) of the present utility model;
Fig. 4 uses 1 for the utility model: with PC data interaction structural drawing;
Fig. 5 uses 2 for the utility model: the Design of Digital Clock structural drawing.
Embodiment
As shown in Figure 1: portable general Logical Design of the present utility model comprises USB (universal serial bus) (USB), drive circuit module, electrically-erasable module with EDA Comprehensive Experiment plate, communicates by letter/download module, frequency adjustable clock module, toggle switch module, field programmable logic array (FPLA) (FPGA), pulse switch module, diode display module and charactron display module; Its design feature is, the drive circuit module that connects USB (universal serial bus) is respectively with electrically-erasable module and the two-way connection of communication/download module, communication/download module is with the two-way connection of field programmable logic array (FPLA), the frequency adjustable clock module of the two-way connection of communication/download module and toggle switch module, pulse switch module all insert field programmable logic array (FPLA) together, field programmable logic array (FPLA) also is connected to diode display module and charactron display module, and the toggle switch module connects diode display module.
Wherein, described USB (universal serial bus) adopts collection communication, download and single power supply to be powered at the USB interface of one; Drive circuit module adopts the FT245BL chip; Communication/download module adopts the CPLD chip; The electrically-erasable module adopts the 93C46 chip; Field programmable logic array (FPLA) (FPGA) adopts the fpga chip of altera corp; The frequency adjustable clock module comprises 4 frequency adjustable clocks; The toggle switch module comprises 24 switches; The pulse switch module comprises 8 switches; Diode display module comprises 48 LED; The charactron display module comprises 8 charactrons.
The utility model is an acp chip with the FPGA of altera corp, USB (universal serial bus) driven be solidificated in driving circuit (FT245BL) module, and communication protocol is integrated in the CPLD (CPLD) with FPGA download logic realized communicating by letter and download function.
The connection of USB (universal serial bus) can be utility model power supply is provided, undertaken alternately by the USB (universal serial bus) (USB) of connection utility model and data or the file in the PC simultaneously, drive circuit module has solidified the communication function of the transmission/reception of data, drive circuit module and electrically-erasable module be used for that common control is communicated by letter and download function between switching, when the user was set in download state, the utility model was finished the download of FPGA net meter file; When the user is set in communications status, the utility model finish or etc. pending data and PC mutual, data input or output field programmable logic array (FPLA) by communication/download module, the clock signal that is input to field programmable logic array (FPLA) can be by frequency adjustable clock module or pulse switch module settings, the user can be provided with input of different frequency clock signal or pulse clock input signal, the net result of design can be implemented on diode display module or the charactron display module conveniently to be observed, the user can be provided with input signal by the toggle switch module according to demand simultaneously, and input signal can be presented at the convenient input data of observing on diode display module or the charactron display module simultaneously.
During experiment, select corresponding function to download to hardware design among the FPGA or realize communicating by letter between PC and the utility model by download/communication switch; Fig. 2 is the utility model design concept block diagram, specific design is that the driving with USB (universal serial bus) is solidificated in drive circuit module, and communication protocol and FPGA are downloaded logic be integrated in and communicate by letter/download module, the clocked logic of frequency adjustable and master chip I/O resource are joined for design provides a plurality of clocks source, only needing to have realized a USB (universal serial bus) to be connected with the USB interface of utility model and just can carry out the function that the download of FPGA net meter file, serial data communication and single power supply are powered.
Utilize this utility model to carry out the flow process of engineering design, as shown in Figure 3: the hardware design part, utilize the EDA developing instrument to carry out after logical design, the compiling logical design net table being downloaded in the field programmable logic array (FPLA); The software design part is utilized SDK (Software Development Kit) to carry out advanced language programming on PC and is realized the interactive operation interface; Interactive interface is connected with utility model by general serial general line interface, can realize communicating by letter between PC and this utility model.
Fig. 4 uses 1 for the utility model: with PC data interaction structural drawing, design is implemented in the field programmable logic array (FPLA) (FPGA), its design module has the interactive operation interface in adjustable clock, scan control, counter, clock control, LED demonstration, charactron demonstration, data communication and the PC in the kernel circuitry, after hardware design successfully is downloaded to FPGA, switch to communication function, open in the PC communication terminal can and this utility model between communicate, use the coprocessor functions of utility model.
Fig. 5 uses 2 for the utility model: the Design of Digital Clock structural drawing, module, time block, timing module, scan module and charactron display module when comprising frequency division module, school, to download to this utility model, the functional checking that can design after the hardware design compiling.
The experiment content that the utility model can carry out comprises following four big classes: (1) logical device test experiments: sequential detector, trigger etc.; (2) module experiment and design: memory read write circuit, LED charactron dynamic scan decoding scheme, counter, microcontroller bus interface experiment etc.; (3) digital display circuit experiment and design: digital clock, taxi meter, controller of automatic vending machine, intellectual contest device to rob the answer, simple CPU design etc.; (4) Electronic Design Competition and innovation training design.

Claims (3)

1. portable general Logical Design and EDA Comprehensive Experiment plate comprise USB (universal serial bus), drive circuit module, electrically-erasable module, communication/download module, frequency adjustable clock module, toggle switch module, field programmable logic array (FPLA), pulse switch module, diode display module and charactron display module; It is characterized in that, the drive circuit module that connects USB (universal serial bus) is respectively with electrically-erasable module and the two-way connection of communication/download module, communication/download module is with the two-way connection of field programmable logic array (FPLA), the frequency adjustable clock module of the two-way connection of communication/download module and toggle switch module, pulse switch module all insert field programmable logic array (FPLA) together, field programmable logic array (FPLA) also is connected to diode display module and charactron display module, and the toggle switch module connects diode display module.
2. according to described portable general Logical Design of claim 1 and EDA Comprehensive Experiment plate, it is characterized in that described USB (universal serial bus) adopts USB interface, this USB interface current collection source power supply, program download and communication function are in one.
3. according to described portable general Logical Design of claim 1 and EDA Comprehensive Experiment plate, it is characterized in that drive circuit module adopts the FT245BL chip; Communication/download module adopts the complex programmable logic device (CPLD) chip; The electrically-erasable module adopts the 93C46 chip; Field programmable logic array (FPLA) FPGA adopts the fpga chip of altera corp; The frequency adjustable clock module comprises 4 frequency adjustable clocks; The toggle switch module comprises 24 switches; The pulse switch module comprises 8 switches; Diode display module comprises 48 LED; The charactron display module comprises 8 charactrons.
CN2011200203629U 2011-01-21 2011-01-21 Portable universal digital logic design and EDA (Electronic Design Automation) comprehensive experimental board CN201984696U (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102831805A (en) * 2012-06-13 2012-12-19 清华大学 Experimental device for computer hardware series course
CN103065529A (en) * 2012-12-25 2013-04-24 重庆邮电大学 Circuit dynamic restructuring electronic design automation (EDA) comprehensive experiment system
CN103150952A (en) * 2013-03-12 2013-06-12 广西生态工程职业技术学院 Reconfigurable electronic design automation (EDA) experimental platform
CN103810013A (en) * 2012-11-13 2014-05-21 中科英华湖州工程技术研究中心有限公司 Programming auxiliary processing device and method based on dial switch array
CN105976678A (en) * 2015-12-23 2016-09-28 徐建桥 Loose-leaf electronic control technology teaching experiment device
CN109900751A (en) * 2019-02-27 2019-06-18 北京航空航天大学 A kind of portable capacitance chromatography imaging measuring device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102831805A (en) * 2012-06-13 2012-12-19 清华大学 Experimental device for computer hardware series course
CN103810013A (en) * 2012-11-13 2014-05-21 中科英华湖州工程技术研究中心有限公司 Programming auxiliary processing device and method based on dial switch array
CN103810013B (en) * 2012-11-13 2016-12-21 中科英华湖州工程技术研究中心有限公司 Programming Auxiliary Processing Unit based on toggle switch array and method
CN103065529A (en) * 2012-12-25 2013-04-24 重庆邮电大学 Circuit dynamic restructuring electronic design automation (EDA) comprehensive experiment system
CN103150952A (en) * 2013-03-12 2013-06-12 广西生态工程职业技术学院 Reconfigurable electronic design automation (EDA) experimental platform
CN103150952B (en) * 2013-03-12 2015-06-17 广西生态工程职业技术学院 Reconfigurable electronic design automation (EDA) experimental platform
CN105976678A (en) * 2015-12-23 2016-09-28 徐建桥 Loose-leaf electronic control technology teaching experiment device
CN109900751A (en) * 2019-02-27 2019-06-18 北京航空航天大学 A kind of portable capacitance chromatography imaging measuring device
CN109900751B (en) * 2019-02-27 2020-12-04 北京航空航天大学 Portable capacitance tomography measuring device

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C14 Grant of patent or utility model
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110921

Termination date: 20130121