CN108648780A - A kind of memory testing system, method and storage medium - Google Patents
A kind of memory testing system, method and storage medium Download PDFInfo
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- CN108648780A CN108648780A CN201711373726.XA CN201711373726A CN108648780A CN 108648780 A CN108648780 A CN 108648780A CN 201711373726 A CN201711373726 A CN 201711373726A CN 108648780 A CN108648780 A CN 108648780A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
A kind of memory testing system of the present invention, method and storage medium, the system include host computer, configuration memory, memory to be measured, master control FPGA and verification FPGA.Host computer realizes selection, configuration, erasing operation to memory to be measured by sending order to master control FPGA；Master control FPGA selects logic according to host computer order request, by the inside of FPGA, and memory to be measured is completed to the level of pin DONE signals with serial ports, verification the FPGA configuration for connecting, and receiving verification FPGA, reset operation is carried out to verification FPGA；Configuration memory is for configuring master control FPGA.The present invention can meet the test request of the memory circuit configured for FPGA long-time heat preservation at low ambient temperatures, solve the problems, such as that automatic test equipment existence time limits.Improve testing efficiency and accuracy of the configuration memory under the conditions of long period keeping low-temperature test.
Description
Technical field
It is special the present invention relates to a kind of the test system and its implementation of the memory circuit for SRAM type FPGA configurations
It is not the test for memory circuit at low ambient temperatures, belongs to technical field of integrated circuits.
Background technology
SRAM type FPGA is to determine its specific function by spreading all over the SRAM configuration bits of FPGA circuitry, these configuration bits
Code stream set is referred to as code stream (bitstream).Memory circuit for SRAM type FPGA configurations is that one kind can be wiped repeatedly
It writes, non-volatile online programmable memory circuit, FPGA configuration bit streams can be stored to wherein, for realizing to FPGA circuitry
Functional configuration.It is generally matched with FPGA in application system.
The memory bank of memory circuit for SRAM type FPGA configurations is by polylith Flash module composition Flash arrays.Control
System and jtag interface circuit realize the software communication for supporting 1149.1 agreements of IEEE.It goes here and there and interface control circuit sends signal, it is complete
At data parallel-serial conversion.Flash control circuits send control signal to realize configuration, erasing, readback and the data to Flash
Read control function.Flash storage units show as changes of threshold afterwards before programming, and threshold value is relatively low before programming, after making alive
It is able to detect that firing current, can determine whether out that storage value is " 1 " after Current amplifier comparator.Threshold value is higher after programming,
It still cannot be opened after making alive, leakage current is very small, can determine whether out that storage value is " 0 " after Current amplifier comparator.It reads
A reference current is needed when going out the work of Current amplifier comparator circuit, by comparing Flash units read current and reference electricity
Stream, judges whether storage value is " 1 ".The generation of reference current needs a start-up circuit, if start-up circuit cannot be opened normally
It is dynamic that stable reference current cannot be provided.The reference current of start-up circuit is easy to be influenced by process deviation and temperature, if
Exception occur can cause reading result mistake occur.This reading failure typically occurs in low temperature environment (0 DEG C or less) and time
Longer, the lower generation of temperature probability is bigger.Therefore, FPGA configurations are tested with memory circuit, need to be ensured in low temperature
It is lower to carry out and have certain cryogenic hold-time requirement.
Memory test based on FLASH generally requires the cooperation of a variety of figures, including such as full 0 vector, complete 1 vector, chess
Disk lattice vector etc..The erasing and write-in of FLASH generally requires the consumption a large amount of time, meanwhile, in order to simulate serial FPGA configurations
Process, series read-out are also required to consume a longer time.And most of test equipment itself does not have the ability for keeping low temperature, it can only
Circuit is taken out from incubator and is tested, actual test temperature is caused not to be inconsistent with test request, can not test and screen out with upper
State the memory circuit of defect.
Invention content
Present invention solves the technical problem that being：Overcome the problems, such as that the existing measuring technology low-temperature test time is insufficient, provides one
Kind memory testing system, method and storage medium, present system can realize FPGA configuration memories at low ambient temperatures
High coverage rate test, solve the problems, such as that the soaking time of automatic test equipment is insufficient, improve FPGA configuration memory circuits and exist
Test accuracy in low-temperature test and testing efficiency.
The technical scheme is that：A kind of memory testing system for SRAM type FPGA configurations, including upper meter
Calculation machine, configuration memory, master control FPGA and verification FPGA；
Host computer is communicated using serial ports with master control FPGA, and by sending order to master control FPGA, realization is treated
Survey the selection, configuration, erasing operation of memory；
Master control FPGA selects logic according to host computer order request, by the inside of FPGA, by memory to be measured with
Serial ports, verification FPGA connections, and the level of pin DONE signals is completed in the configuration for receiving verification FPGA, is answered verification FPGA
Bit manipulation；
Configuration memory is for configuring master control FPGA；
Configuration file is configured into configuration memory by jtag port using JTAG modes.
The host computer is connect by serial ports with general purpose I/O of master control FPGA；The configuration data of memory to be measured
Position pin D, configurable clock generator pin CLK, chip-select pin CE, output enable pin OE, initial configuration pin CF, JTAG input pipe
Foot TDI, JTAG clock pins TCK, JTAG output pin, JTAG mode base pin selection TMS respectively with general purpose I/O of master control FPGA
Pin connects；The reseting pin PROG_B of FPGA is verified, pin DONE is completed in configuration, and initialization is completed pin INIT, matched parallel
Data pins D0-D7 is set to connect with the general purpose I of master control FPGA/O pins；Verify global clock pin GCLK1 and the master control of FPGA
The global clock pin GCLK2 of the global clock pin GCLK1 connections of FPGA, configurable clock generator pin CCLK and master control FPGA connects
It connects.
A method of it is tested according to above-mentioned test system, steps are as follows：
(1), test starts, and is configured to configuration memory and carries out System self-test；
Specific implementation is as follows：System is normally after the power is turned on.If system is to use for the first time, need to be made by host computer
Configuration operation is carried out to configuration memory by jtag port using specialized configuration device with memory specialized configuration software.If not
It uses for the first time, may skip this step.After the completion of powering on, system enters self-test state, if fail self-test, host computer feedback error disappears
Breath, test stop.If system testing can be started after self-test success.It is sent out to master control FPGA by serial ports using external host computer
Send 8 binary system configuration orders.
(2), master control FPGA is communicated with specified memory formation to be measured.
Specific implementation is as follows：Master control FPGA is required according to 8 binary system configuration orders, and specified to order is to be measured
TCK, TDI, TMS of memory are connected with TDO pins by master control FPGA internal wirings, are communicated with serial ports formation.8 binary systems
Order specific format be：The specified memory to be measured number that need to be operated of 4-8 bit binary numbers, the number is to store
The position that device test system is put is divided, using 00001 as initial number, to different location in such a way that increment is 1
Memory to be measured is numbered.The operation that the specified selected memory to be measured of 1-3 bit binary numbers carries out, wherein 001 indicates
Memory configuration operation, 010 indicates memory test operation, and 100 indicate memory erasing operation.Life sent in this step
It enables using 00001001 as initial command, when being configured to different memory, it is only necessary to 4-8 storages to be measured in modification order
Device is numbered.
(3), using specialized configuration software to specifying memory to be measured to configure.
Specific implementation is as follows：Host computer calls memory specialized configuration software, by serial ports to configuration order
TCK, TDI, TMS, TDO pin of the memory to be tested of selection are communicated, and using JTAG configuration modes, realization is deposited to be measured
The configuration of reservoir operates.
(4), all memories to be measured are configured one by one.
Specific implementation is as follows：The step of executing (2) and (3) repeatedly sends according to the different location residing for memory
8 binary system configuration orders one by one configure specified memory to be measured using specialized configuration memory.Until that will test
Memory circuit arrangement to be tested in system in all test fixtures is completed.
(5), memory to be measured is tested.
Specific implementation is as follows：Host computer sends 8 binary storage device test commands.Sent in this step
Order using 00001010 as initial command, when testing different memory, it is only necessary to 4-8 to be measured in modification order
Memory is numbered.Master control FPGA is required according to 8 binary system test commands, to ordering matching for specified test memory
Pin is set to connect with the configuration pin of verification FPGA by the internal wiring of master control FPGA.Memory to be measured configures mould according to main string
Formula automatically configures verification FPGA.
(6), memory test result to be measured is collected.
Specific implementation is as follows：After the completion of verifying FPGA configurations, the DONE pin level for verifying FPGA is sent to master
It controls in FPGA, master control FPGA is sent to by serial ports in host computer.Host computer software is according to the level of DONE signals
Value judges the test result of simultaneously display-memory.
(7), memory test to be measured is completed, and resets verification FPGA.
Specific implementation is as follows：Master control FPGA distinguishes INIT the and PROG_B pins for verifying FPGA according to sequencing
It carries out pin level and drags down operation, after being kept for a period of time, successively carry out drawing high operation by INT and PROG_B pins, make verification
FPGA is resetted, and is configured to it convenient for remaining memory to be tested.
(8), all memories to be measured are tested one by one.
Specific implementation is as follows：The step of executing (6), (7) and (8) repeatedly, according to the different location residing for memory,
8 binary system test commands are sent, specified memory to be measured is configured one by one using specialized configuration memory.Until inciting somebody to action
Storage component part to be tested test in test system in all test fixtures is completed.
(9), all test memories are wiped,
Specific implementation is as follows：After the completion of all memory tests, host computer to master control FPGA send 8 two into
Erasing order processed.TCK, TDI, TMS, TDO pin of the memory to be tested selected to erasing order by serial ports communicate,
Host computer calls memory specialized configuration software realization erasing operation.Erasing behaviour is carried out successively to the memory of all tests
Make.Erasing order sent in this step is using 00001100 as initial command, when wiping different memory, it is only necessary to
Number can be after all memory erasure completions for 4-8 memories to be measured in modification order, and test terminates.
A kind of storage medium, for the method described in storing step (1)-step (9).
The present invention has the advantages that compared with prior art：
(1), the present invention constructs one for the low-temperature test problem of memory by using host computer and FPGA
The test system that kind can be used for testing for a long time under low temperature environment.Set test system can make memory directly be in low temperature environment
Under tested, meet test request of the memory of defined in test condition under low-temperature test environment.It eliminates due to certainly
The limitation of dynamic test equipment itself, test caused by temperature difference, which is accidentally surveyed, when causing only test under normal temperature environment asks
Topic improves testing precision of the memory circuit in low-temperature test, solves the direct test of memory at low ambient temperatures
Problem.
(2), test system of the invention may include multiple device under test, switching device under test can be controlled by software, to referring to
Fixed memory to be measured is tested one by one, and is preserved automatically according to specified path to test result, and storage is realized
The batch-automated test of device.The entire test process of memory is monitored without tester, reduces manpower testing cost.
(3), test system of the invention, by using JTAG configuration modes and main string configuration mode respectively to memory into
Row configuration and test.This two kinds of configuration modes are the main configuration mode for the memory circuit of SRAM type FPGA configurations,
Therefore the test system of the present invention is applicable in the Multiple Type memory for having this two kinds of configuration modes, and there is memory to survey
Try the advantage that range is wide, test all-purpose is strong.
(4), test system of the invention, by judge FPGA configure whether the function of good authentication memory.With it is automatic
Tester is compared in such a way that multi-pipe pin transmission excitation, reception are responded and compared, and is enormously simplified memory inside and is deposited
The test process that content is read is stored up, test development difficulty is reduced.
Description of the drawings
Fig. 1 is the system entire block diagram of the present invention.
Fig. 2 is the specific example block diagram of the present invention.
Fig. 3 is master control FPGA circuitry and configuration memory circuit connection diagram in the specific example of the present invention.
Fig. 4 is master control FPGA circuitry and memory circuit connection diagram to be measured in the specific example of the present invention.
Fig. 5 is master control FPGA circuitry in the specific example of the present invention and verification FPGA circuitry connection diagram.
Fig. 6 is the testing process of the test system of the present invention.
Specific implementation mode
Entire test system framework is as shown in Figure 1, by host computer 101, communication serial port 102, system master
FPGA103, verification FPGA104, configuration memory 105, jtag port 106 and memory to be measured 107108109 form.Wherein,
Host computer sends control command to master control FPGA103 by serial ports 102 and is operated to master control FPGA103.Master control FPGA
According to order request, controls and configured between memory and host computer 101 to be measured and verification FPGA104, wipe, test
Operation, and memory test result is fed back into host computer 101.Verification FPGA104 passes through memory 107108109 to be measured
It is configured, it is whether normal by the function of configuration result verifying memory.Configuration memory 105 is used for system electrification
Afterwards, by jtag port, master control FPGA103 is configured automatically using JTAG modes, it is made to have control function.
The present invention is described in further detail with specific example below：
As shown in Fig. 2, in specific example, using Xilinx companies FPGA and memory circuit as example elements.Its
In, XCF32P205 is as configuration memory, and XC2V3000203 is as master control FPGA, and XC2V1000204 circuits are as verification
FPGA.XC18V04207208 is as memory to be tested.
It is illustrated in figure 3 the connection diagram of XCF32P205 and XC2V3000203 in specific example.Wherein,
The JTAG clock pins TCK connections of JTAG the clock pins TCK and XC2V3000203 of XCF32P205, the JTAG of XCF32P205
The JTAG input pins TDI connections of output pin TDO and XC2V3000203, the JTAG mode base pin selection TMS of XCF32P205
It is connect with the JTAG mode base pin selection TMS of XC2V3000203.The JTAG input pin TDI pins of XCF32P205, clock pipe
Foot TCK, output pin TDO, model selection pin TMS are presented on the surface of system board in a manner of arranging needle.Use upper meter
Calculation machine 201 is configured the configuration file of XC2V3000203 into XCF32P205 by arranging needle using specialized configuration device.
Pin INIT_B connections are completed in the initialization of output the enable pin OE and XC2V3000203 of XCF32P205.XCF32P205's
Pin DONE connections are completed in the configuration of chip-select pin CE and XC2V3000203.The clock pins of configuration memory 205 with
The configurable clock generator pin CCLK connections of XC2V3000.The reset transistor of initial configuration the pin CF and XC2V3000 of XCF32P205
Foot PROG_B connections.Configuration data position pin D0, D1, D2, D3, D4, D5, D6, D7 of XCF32P205 respectively successively with
Configuration data position pin D0, D1, D2, D3, D4, D5, D6, D7 connection of XC2V3000.Using iMPACT programming softwares pair
XCF32P205 is successfully carried out with postponing, and system normally powers on, and XCF32P205 can be managed according to main string configuration mode by D0 automatically
Foot sends configuration data to XC2V3000203, completes the configuration to XC2V3000203, achieves the control work(of master control FPGA
Energy.
It is illustrated in figure 4 the connection diagram of XC2V3000203 and XC18V04207208 in specific example.
The 0th configuration data position pin D0 of XC18V04207208, configurable clock generator pin CLK, chip-select pin CE, output enable pin OE,
Initial configuration pin CF, JTAG input pin TDI, JTAG clock pins TCK, JTAG output pin, JTAG mode selecting pipe
Foot TMS is connect with the general purpose I of XC2V3000203/O pins respectively.
In system in application, the order that XC2V3000203 is sent according to host computer 101, uses XC2V3000203's
Selection logic in inside carries out signal interaction by the control pin of general purpose I/O pins and the XC18V04207208 chosen.Realization pair
The configuration and test of XC18V04207208.Configuration to XC18V04207208 calls iMPACT programming softwares using host computer,
Control and the general purpose I for the XC2V3000203 of the JTAG configuration pins of XC18V04207208 being connected/O pins, use JTAG
Mode is configured into line storage.Test to XC18V04207208, XC2V3000203, will be selected according to host computer order request
The D0 pins of the memory to be tested selected, CLK pins, CE pins, OE pins, CF pins by general purpose I/O pins with
The D0 pins of XC2V1000204, GCLK pins, DONE pins, INIT pins, the connection of PROG_B pins.Mould is configured using main string
Formula carries out configuration testing to XC2V1000204.After being completed, erasable operation is carried out to XC18V04207208.Host computer
101 call iMPACT softwares, and by serial ports, the general purpose I being connect with the JTAG configuration pins of XC18V04207208/O pins carry out
Signal interaction completes the erasable operation of XC18V04207208.The general purpose I of master control FPGA/O number of pin limit values are to be tested to be deposited
The quantity of reservoir, can be according to the batch production quantity of memory, according to the number of pin of the FPGA SRAM type that flexibly selection is suitble to
Master control FPGA.
It is illustrated in figure 5 the connection diagram of XC2V3000203 and XC2V1000204 in specific example.XC2V1000204
Reseting pin PROG_B, configuration complete pin DONE, initialization complete pin INIT, parallel configuration data pin D0-D7 with
The general purpose I of XC2V3000203/O pins connection.Global clock the pin GCLK1's and XC2V3000203 of XC2V1000204 is complete
The GCLK1 connections of office clock pin, the GCLK2 connections of configurable clock generator pin CCLK and XC2V3000203.The master of XC2V1000204
It is that test memory test configures it to act on, and the configuration of memory is judged by the configuration result of XC2V1000204
Whether function is normal.Configuration to XC2V1000204, XC2V3000203, will according to the order request of host computer
The D0 pins of XC2V1000204, GCLK pins, DONE pins, INIT pins, PROG_B pins are by general purpose I/O pins, with survey
D0 pins, CLK pins, CE pins, OE pins, the CF pins for trying memory connect.Memory to be tested configures mould using main string
Formula automatically configures XC2V1000204.After the completion of configuration, if configuration successful, pin is completed in the configuration of XC2V1000204
DONE becomes high level, if loss of configuration, pin DONE is completed in the configuration of XC2V1000204 becomes low level.Configuration result meeting
By XC2V3000203, feed back to host computer 101 using serial ports, host computer 101 this result can be carried out record and
It preserves.Test result feedback is completed, and is carried out reset operation to XC2V1000204, is configured to it convenient for memory to be measured.
XC2V3000203 initializes pin using the reset configuration pin PROG_B and configuration of general purpose I/O controls XC2V1000204
INIT.PROG_B pins and INIT pins be successively pulled to low level, after continuing for some time, successively by PROG_B pins and
INIT pins are pulled to high level, realize that the reset to XC2V1000204 operates.
The testing process of the specific example of this system is as shown in Figure 6.External power supply is powered for this system, and system normally powers on
Enter self-test state, if fail self-test, host computer feedback error message after 301.It can start system testing after detection is normal.
Test starts, and host computer 101 sends 8 binary orders 302 by serial ports.XC2V3000203 is ordered according to 8 binary systems
It enables and requiring, the XC18V04303 to be tested being connect with its general purpose I/O is chosen by internal logic.Host computer calls iMPACT to match
Software is set, configuration 304 is completed by the signal transmission of serial ports and the JTAG configuration pins of XC18V04207208 to be tested.Configuration
After the completion, iMPACT softwares can feed back to configuration result in upper computer software 101, judge whether BQ18V04207208 succeeds
Complete configuration 305.If configuration failure, system can record fail result.System continues to select other to be measured according to test request
XC18V04 is tried, configuration order is sent and is configured.All XC18V04207208 to be tested are carried out according to 302 to 305 steps
Configuration.
Proceed by memory test.Host computer sends 8 binary system test commands 306, extremely by serial ports
In XC2V3000203.XC2V3000203 according to order request, by XC18V04207208 to be tested by internal logic with
The main string configuration pin connection 307 of XC2V1000204.XC18V04207208 can be automatically according to main string configuration mode pair
XC2V1000204 is configured.After the completion of XC2V1000204 configurations, configuration can be completed the level feed-back of pin DONE extremely
308 in XC2V3000203.If XC2V1000204 configuration successfuls, pin DONE is completed in configuration will be presented high level state.If
XC2V1000204 configuration failures, pin DONE is completed in configuration will be presented low level state.XC2V3000203 will by serial ports
XC2V1000204 configuration results are fed back to 309 in host computer, the test result of host computer record storage.
XC2V3000203 is resetted XC2V1000204 by the operation of PROG pins and INIT pins to XC2V1000204
310, it is configured convenient for other XC18V04 to be measured.Hereafter, step 306 is executed repeatedly and arrive step 310, will own
XC18V04 is tested.
After the completion of all memory tests, host computer 101 will record test result 312, and send 8 binary systems and wipe
Except order, memory specialized configuration software is called, all test memories 207208 are subjected to erasing operation 313.Erasing finishes
Afterwards, testing process terminates.
The above, best specific implementation mode only of the invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the known technology of professional and technical personnel in the field.
Claims (10)
1. a kind of memory testing system for SRAM type FPGA configurations, it is characterised in that：Including host computer (101),
Configuration memory (105), master control FPGA (103) and verification FPGA (104)；Host computer (101) is completed by serial ports (102)
With the communication of master control FPGA (103)；Master control FPGA (103) passes through the inside of FPGA according to host computer (101) order request
Logic is selected, memory to be measured is connect with serial ports (102), verification FPGA (104), and receive the configuration of verification FPGA (104)
The level for completing pin DONE signals carries out reset operation to verification FPGA (104)；Configuration memory (105) is used for master control
FPGA (103) is configured.
2. a kind of memory testing system for SRAM type FPGA configurations according to claim 1, it is characterised in that：Institute
Host computer (101) is stated to connect with general purpose I/O of master control FPGA (103) by serial ports (102)；Match the 0th of memory to be measured
Set data bit pin D0, configurable clock generator pin CLK, chip-select pin CE, output enable pin OE, initial configuration pin CF,
JTAG input pin TDI, JTAG clock pins TCK, JTAG output pin, JTAG mode base pin selection TMS respectively with master control
The general purpose I of FPGA (103)/O pins connection；The reseting pin PROG_B of FPGA (104) is verified, pin DONE is completed in configuration, just
General purpose I/O pins that beginningization completes pin INIT, parallel configuration data pin D0-D7 and master control FPGA (103) are connect；Verification
The global clock pin GCLK1 of the global clock pin GCLK1 and master control FPGA (103) of FPGA (104) are connect, configurable clock generator pipe
Foot CCLK is connect with the global clock pin GCLK2 of master control FPGA (103).
3. a kind of a kind of memory testing system for SRAM type FPGA configurations using described in claims 1 or 22 is surveyed
The method of examination, it is characterised in that steps are as follows：
(1) test starts, and is configured to configuration memory (105) and carries out System self-test；
(2) master control FPGA (103) is communicated with specified memory foundation to be measured；
(3) all memories to be measured are configured one by one；
(4) all memories to be measured are tested one by one；
(5) memory test result to be measured is collected；
(6) memory test to be measured is completed, and resets verification FPGA；
(7) all test memories are wiped.
4. a kind of method for testing memory for SRAM type FPGA configurations according to claim 3, it is characterised in that：Institute
The specific method for stating step (1) is：
System after the power is turned on, if system is to use for the first time, need to normally carry out configuration memory (105) by host computer (1)
Configuration operation；After the completion of powering on, system enters self-test state, if fail self-test, host computer feedback error message, test stops；
If system testing can be started after self-test success；Using external host computer (101) by serial ports (102) to master control FPGA
(103) 8 binary system configuration orders are sent.
5. a kind of method for testing memory for SRAM type FPGA configurations according to claim 4, it is characterised in that：Institute
The specific method for stating step (2) is：
Master control FPGA (103) is required according to 8 binary system configuration orders, TCK, TDI of the to be measured memory specified to order,
TMS with TDO pins are connected by master control FPGA (103) internal wiring, are communicated with serial ports formation.
6. a kind of method for testing memory for SRAM type FPGA configurations according to claim 3, it is characterised in that：Institute
The specific method for stating step (4) is：Host computer (101) sends 8 binary storage device test commands, master control FPGA
(103) according to 8 binary system test command requirements, to ordering the configuration pin of specified test memory to pass through master control FPGA
(103) internal wiring is connect with the configuration pin of verification FPGA (104)；Memory to be measured is according to main string configuration mode, to testing
Card FPGA (104) is configured.
7. a kind of method for testing memory for SRAM type FPGA configurations according to claim 3, it is characterised in that：Institute
The specific method for stating step (4) is：After the completion of verifying FPGA (104) configurations, the DONE pin level that will verify FPGA (104) is sent out
It gives in master control FPGA (203), master control FPGA (103) is sent to by serial ports (102) in host computer (101)；Upper meter
Calculation machine (1) judges the test result of simultaneously display-memory according to the level value of DONE signals.
8. a kind of method for testing memory for SRAM type FPGA configurations according to claim 3, it is characterised in that：Institute
The specific method for stating step (7) is：After the completion of all memory tests, host computer (1) sends 8 to master control FPGA (103)
Position binary system erasing order；Pass through TCK, TDI, TMS, TDO pipe for the memory to be tested that serial ports (102) selects erasing order
Foot is communicated, and host computer calls memory specialized configuration software realization erasing operation；To the memories of all tests according to
Secondary carry out erasing operation.
9. a kind of method for testing memory for SRAM type FPGA configurations according to claim 4, it is characterised in that：Institute
The specific format for stating 8 binary system configuration orders is：The specified memory to be measured that need to be operated of 4-8 bit binary numbers is compiled
Number, which is divided with the position that memory testing system is put, using 00001 as initial number, the side for being 1 with increment
The memory to be measured of different location is numbered in formula；The behaviour that the specified selected memory to be measured of 1-3 bit binary numbers carries out
Make, wherein 001 indicates memory configuration operation, 010 indicates memory test operation, and 100 indicate memory erasing operation.
10. a kind of storage medium, it is characterised in that：For storing the method described in step in claim 3 (1)-step (7).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109669802A (en) * | 2018-11-13 | 2019-04-23 | 北京时代民芯科技有限公司 | A kind of configurable memory verifying system for EDAC verifying |
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