CN105551528A - Testing apparatus and method of high-speed large-capacity multi-chip Flash module based on ATE - Google Patents
Testing apparatus and method of high-speed large-capacity multi-chip Flash module based on ATE Download PDFInfo
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- CN105551528A CN105551528A CN201510906033.7A CN201510906033A CN105551528A CN 105551528 A CN105551528 A CN 105551528A CN 201510906033 A CN201510906033 A CN 201510906033A CN 105551528 A CN105551528 A CN 105551528A
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- chip
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- flash module
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56016—Apparatus features
Abstract
The invention provides a testing apparatus and method of a high-speed large-capacity multi-chip Flash module based on ATE. The testing apparatus of the high-speed large-capacity multi-chip Flash module based on ATE includes automatic test equipment (ATE), a test patch circuit, and a test controller, wherein the test patch circuit is used for connecting the automatic test equipment to a to-be-tested Flash module, and the test controller controls the automatic test equipment for test.
Description
Technical field
The present invention relates to ic test technique, especially use the device and method that ATE (automatic test equipment) (being called for short ATE) T5385ES carries out space flight high speed, Large Copacity multi-chip Flash modules A CT-F512K32-070P7Q tests.
Background technology
ACT-F512K32-070P7Q is a high speed, Large Copacity multi-chip Flash module, comprises 4 chips altogether, and each chip comprises 8 sectors, the capacity of one single chip is 512K × 8, total volume is 16Mbit, and voltage power supply scope is 4.5V to 5.5V, and packing forms is PGA-68.
Memory test is normally based upon on the fault model of storage unit, and common fault model mainly contains (1) fault model based on fixed cell; (2) based on the memory test fault model of bridge defects; (3) based on the memory test fault model of association defect; (4) decoding fault model; (5) data preserve fault model etc.The fault mode that these fault models show mainly contains: (1) is fixed as the hard failure of " 1 "/" 0 " or soft actual effect; (2) open circuit or short trouble; (3) address decoder faults; (4) multiplely number is write; When writing several to certain storage unit, these data write a lot of unit simultaneously; (5) figure sensitive fault: when some resolution chart, storer can not reliably working; (6) regeneration was lost efficacy: store loss of data at the minimum regeneration period internal storage of regulation.When testing storer, mainly through writing different resolution charts for above fault model, above fault mode is tested.
But efficient, the fast measurement technique that lack in prior art Large Copacity, multi-chip Flash module.
Summary of the invention
The problem that the present invention solves lacks efficient, the fast measurement technique to Large Copacity, multi-chip Flash module in prior art; For solving described problem, the invention provides based on the high-speed high capacity of ATE, the proving installation of multi-chip Flash module and method.
The proving installation of the high-speed high capacity multi-chip Flash module based on ATE provided by the invention comprises: ATE (automatic test equipment), test adaptor circuit, testing and control machine; Described built-up circuit, for connecting ATE (automatic test equipment) and Flash module to be measured, controls ATE (automatic test equipment) test by described testing and control machine.
Further, in described testing and control machine, testing software is installed, is called the test resource in ATE (automatic test equipment) by described testing software.
Further, the model of described Flash module is ACT-F512K32-070P7Q.
Further, described ATE (automatic test equipment) adopts Japanese Advantest Corporation to design the VLSI (very large scale integrated circuit) memory testing system T5385ES produced.
The present invention also provides the described method of testing based on the high-speed high capacity of ATE, the proving installation of multi-chip Flash module, comprising:
Step one, making built-up circuit connect described ATE (automatic test equipment) and Flash module to be tested;
Step 2, by described testing and control machine operational testing.
Further, described test comprises: complete " 0 ", complete " 1 " validation test, the erasing of one single chip of full chip erase and checking, full chip-stored unit are tested with the erasing of checking, the single sector of single-chip and checking, the full chessboard pattern of chip-stored unit, full the deagonal pattern of chip test.
Advantage of the present invention comprises:
T5385ES has abundant, powerful test resource, T5385ES develops the test procedure of ACT-F512K32-070P7Q and writes dependence test figure, can meet test request preferably.
Accompanying drawing explanation
Fig. 1 is the composition structural representation of T5385ES.
Embodiment
Hereinafter, the present invention is further elaborated in conjunction with the accompanying drawings and embodiments.
Sayed as background technology, ACT-F512K32-070P7Q is a high speed, Large Copacity multi-chip Flash module, because Flash module comprises 4 chips, each chip 8 sectors, so lack technology that is efficient, Quick Measurement ACT-F512K32-070P7Q in prior art.Inventor studies for the problems referred to above, provides a kind of proving installation and method of the high-speed high capacity multi-chip Flash module based on ATE in the present invention.
The proving installation of the high-speed high capacity multi-chip Flash module based on ATE provided by the invention comprises: ATE (automatic test equipment), test adaptor circuit, testing and control machine; Described built-up circuit, for connecting ATE (automatic test equipment) and Flash module to be measured, controls ATE (automatic test equipment) test by described testing and control machine.
Described ATE (automatic test equipment) adopts Japanese Advantest Corporation to design the VLSI (very large scale integrated circuit) memory testing system T5385ES produced.Figure 1 shows that the composition structural representation of T5385ES.And write special resolution chart for ACT-F512K32-070P7Q, described resolution chart is stored in testing and control machine, to complete the test to ACT-F512K32-070P7Q, detects the failure mode that it may exist.The resolution chart write mainly comprises: full chip erase figure (erase_all_chip.pat), single-chip erasing figure (erase_one_chip.pat), sector erasing figure (erase_sector.pat), single-chip list sector erasing figure (erase_chip3_sector4.pat), full chip reads figure (read_all_chip.pat), figure (read_sector.pat) is read in sector, full chip read-write figure (write_read_all_chip.pat), chessboard pattern (checkboard.pat) and deagonal pattern (diagonal.pat) etc.By calling above resolution chart in test procedure, realize following test target: deagonal pattern verification and testing of the erasing of (1) full chip and complete " 0 ", complete " 1 " validation test of checking, (2) full chip-stored unit, the erasing of (3) one single chip and the erasing of checking, the single sector of (4) single-chip and checking, (5) the chessboard pattern verification and testing of chip, (6) chip entirely entirely.Described testing and control machine also stores other softwares for testing.
The test process of T5385ES to Flash modules A CT-F512K32-070P7Q is adopted to comprise:
1. the erasing of full chip and checking.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call full chip erase figure (erase_all_chip.pat), to device write erasing instruction, complete the erasing of chip, then call and read complete " 1 " figure (read_all_chip.pat) and read " 1 " entirely to chip and operate, whether the erase feature of proofing chip is correct.
2. complete " 0 ", complete " 1 " validation test of full chip-stored unit.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call full chip read-write figure (write_read_all_chip), successively " 0 " and write complete " 1 " are entirely read to full chip-stored space write complete " 0 ", then read complete " 1 ".
3. the erasing of one single chip and checking.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call single-chip erasing figure (erase_one_chip.pat), to some chip write erasing instruction of device inside, complete erasing, then carry out read operation to chip, whether the single-chip erase feature of verifying parts is correct.
4. the erasing of the single sector of single-chip and checking.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call the erasing figure (erase_chip3_sector4.pat) of the single sector of single-chip, to the 4th sector write erasing instruction of the 3rd chip block of device inside, complete erasing, then carry out read operation to being wiped free of sector, whether the erase feature of the single sector of single-chip of verifying parts is correct.
5. the chessboard pattern verification and testing of full chip-stored unit.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call chessboard pattern (checkboard.pat), successively " 55 " and write " AA " are read to full chip-stored space write " 55 ", then read " AA ".
6. the deagonal pattern verification and testing of full chip.The value of setting device working power, incoming level, output level, datum, load current, the order that powers on of setting device, sets the distribution of the data layout of the address signal of device, control signal and data-signal, sequential, passage and control register.Call full chip deagonal pattern (diagonal.pat), first to full chip-stored space write deagonal pattern, then read operation is carried out to full chip-stored space, the writing and reading of full chip deagonal pattern are verified.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection domain of technical solution of the present invention.
Claims (6)
1. based on the proving installation of the high-speed high capacity multi-chip Flash module of ATE, it is characterized in that, comprising: ATE (automatic test equipment), built-up circuit, testing and control machine; Described built-up circuit, for connecting ATE (automatic test equipment) and Flash module to be measured, controls ATE (automatic test equipment) test by described testing and control machine.
2., according to the proving installation of the high-speed high capacity multi-chip Flash module based on ATE according to claim 1, it is characterized in that, in described testing and control machine, testing software is installed, is called the test resource in ATE (automatic test equipment) by described testing software.
3. according to the proving installation of the high-speed high capacity multi-chip Flash module based on ATE according to claim 1, it is characterized in that, the model of described Flash module is ACT-F512K32-070P7Q.
4. according to the proving installation of the high-speed high capacity multi-chip Flash module based on ATE according to claim 1, it is characterized in that, described ATE (automatic test equipment) adopts Japanese Advantest Corporation to design the VLSI (very large scale integrated circuit) memory testing system T5385ES produced.
5. the method for testing of the proving installation of the high-speed high capacity multi-chip Flash module based on ATE that any one provides in Claims 1-4, is characterized in that, comprising:
Step one, making built-up circuit connect described ATE (automatic test equipment) and Flash module to be tested;
Step 2, by described testing and control machine operational testing.
6. according to the method for testing of the high-speed high capacity multi-chip Flash module based on ATE according to claim 5, it is characterized in that, described test comprises: complete " 0 ", complete " 1 " validation test, the erasing of one single chip of full chip erase and checking, full chip-stored unit are tested with the erasing of checking, the single sector of single-chip and checking, the full chessboard pattern of chip-stored unit, full the deagonal pattern of chip test.
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| CN106526454A (en) * | 2016-11-24 | 2017-03-22 | 上海精密计量测试研究所 | ATE-based method for testing FPGA configuration chip |
| CN106847343A (en) * | 2016-12-08 | 2017-06-13 | 上海精密计量测试研究所 | The method of testing of the mram memory based on ATE |
| CN108345752A (en) * | 2018-02-24 | 2018-07-31 | 北京智芯微电子科技有限公司 | The life characteristic appraisal procedure of wafer scale nonvolatile memory |
| CN109901650A (en) * | 2017-12-07 | 2019-06-18 | 北京确安科技股份有限公司 | A kind of a reference source method for repairing and regulating of embedded flash chip |
| WO2021179600A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Memory testing method and related device |
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