CN112530508B - NAND FLASH memory parallel test and bad block write-back method - Google Patents
NAND FLASH memory parallel test and bad block write-back method Download PDFInfo
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- CN112530508B CN112530508B CN201910873960.1A CN201910873960A CN112530508B CN 112530508 B CN112530508 B CN 112530508B CN 201910873960 A CN201910873960 A CN 201910873960A CN 112530508 B CN112530508 B CN 112530508B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
Abstract
The application discloses a NAND FLASH memory parallel test and bad block write-back method, which comprises the following steps: reading a plurality of memory IDs, comparing the memory IDs with preset IDs, and judging whether each memory is preliminarily qualified or not; judging whether the 0 th block of each LUN in the preliminarily qualified storage is a non-bad block or not; determining the initial bad block number of each LUN in each memory respectively; judging whether the memory of which each 0 th block is a non-bad block is an empty chip or not; identifying the newly generated bad blocks in the test process, respectively determining the number of the newly generated bad blocks of each logic unit in the memory which is an empty chip, and carrying out write-back on the newly generated bad blocks according to a preset rule; and judging whether the corresponding storage is qualified or not based on the initial bad block number and the newly generated bad block number of each LUN. The method can realize parallel testing of a plurality of NAND FLASH memories, can effectively identify bad blocks and write back, improves testing efficiency, and protects the preset original flag bit.
Description
Technical Field
The application relates to the technical field of electronic component detection, in particular to a NAND FLASH memory parallel test and bad block write-back method.
Background
NAND FLASH is a nonvolatile memory and has the characteristic of no data loss after power failure. Compared with the traditional NOR FLASH, NAND FLASH has the advantages of large capacity, high cost performance, more erasing times, long storage life and the like, but NAND FLASH has the disadvantages that bad blocks exist in a storage array, and the number of the bad blocks increases along with the increase of the use frequency.
The test logic of the common memory such as SRAM, EPROM and NOR FLASH is as follows: and writing data into all the memory arrays according to a certain rule, reading after finishing writing, comparing whether the read data is consistent with the written data, and judging that the memory is unqualified if the read data is inconsistent with the written data. The test process can obtain a test conclusion by directly comparing the data without jumping and multiple judgment. NAND FLASH in actual test, the quality of the block to be tested needs to be judged for many times in the whole test process, and the next test content needs to be determined according to the judgment result each time; moreover, due to the difference of memories, the addresses of the bad blocks are different, so that the length and the content of the test pattern vector are not identical, namely the test patterns of different memories with the same model are not necessarily identical.
Therefore, NAND FLASH cannot be tested by using the unified random pattern vector method, and the existing test technology can only test one NAND FLASH alone and cannot test a plurality of NAND FLASH in parallel. However, the capacity of NAND FALSH is typically several GB, and both the writing operation and the erasing operation need to wait for a certain period of time, and with the increasing of the capacity, the test cost of testing 1 NAND FALSH alone is too high, and at the same time, a great waste of resources is caused.
Disclosure of Invention
In order to solve the above problems, the present application provides a method for parallel testing of NAND FLASH memories and bad block write-back, which solves the problem that the parallel testing of a plurality of NAND FLASH memories cannot be performed in the prior art.
The application adopts the following technical scheme:
a NAND FLASH memory parallel test and bad block write back method, the method comprising:
reading a plurality of memory IDs, comparing the memory IDs with preset IDs, and judging whether each memory is preliminarily qualified according to a comparison result;
judging whether the 0 th block of each logic unit in the memory which is preliminarily qualified is a non-bad block or not under the condition that the memory is preliminarily qualified;
determining the initial bad block number of each logic unit in each memory according to the memory of which the 0 th block of each logic unit is a non-bad block;
judging whether the memory of which each 0 th block is a non-bad block is an empty chip or not;
identifying the bad blocks newly generated in the test process under the condition that the memory of which each 0 th block is a non-bad block is an empty block, respectively determining the number of the bad blocks newly generated in each logic unit in the memory of which the empty block is an empty block, and writing back the bad blocks newly generated according to a preset rule;
and judging whether the corresponding memory is qualified or not based on the initial bad block number of each logic unit in the memory which is empty and the newly generated bad block number.
Preferably, determining whether each memory is preliminarily qualified according to the comparison result includes: if the memory ID is matched with the preset ID, judging that the memory matched with the ID is preliminarily qualified; if the memory ID is not matched with the preset ID, the memory with the unmatched ID is judged to be preliminarily disqualified.
Preferably, the method further comprises: reading data matched with the invalid pin; and positioning the memory with inconsistent data of the matched invalid pin and the data of the preset ID as a preliminarily failed memory.
Preferably, determining whether the 0 th block of each logical unit in the preliminarily qualified memory is a non-bad block comprises: reading data of the 0 th block of each logic unit in the preliminarily qualified memory; verifying whether the 0 th block is empty based on the read data; writing data to the 0 th block of each logic unit in each memory where the 0 th block is empty; and reading the written data, judging whether the written data is consistent with the read data, if so, determining that the 0 th block is a non-bad block, otherwise, determining that the 0 th block is a bad block.
Preferably, determining the initial number of bad blocks for each logical unit in each memory includes: reading pre-marked bad block bytes in each logic unit in each memory; and accumulating the times of reading the bad block bytes to obtain the number of the bad blocks of each logic unit in each memory.
Preferably, determining whether each memory of which the 0 th block is a non-bad block is a empty block includes: performing full-slice reading of all blocks on all logic units of the memory with each 0 th block being a non-bad block, wherein the full-slice reading is traversing the blocks from the 0 th block to the Z th block; judging whether the currently traversed block is an initial bad block or not; under the condition that the currently traversed block is not an initial bad block, data reading is carried out; under the condition that the currently traversed block is an initial bad block, data reading is not performed, and after the data reading of the currently traversed block is completed by other memories, the data reading of the next block is synchronously performed; if the data of all the blocks of all the logic units in the memory are read to be empty, the memory with all the blocks of the data being empty is an empty slice; if the data of any one block of any one logic unit in the memory is non-empty, the memory with the data of any one block being non-empty is a non-empty slice.
Preferably, identifying the newly generated bad blocks in the test process, determining the number of the newly generated bad blocks of each logic unit in the memory which is the empty chip, and writing back the newly generated bad blocks according to a predetermined rule includes: judging whether each block of each logic unit of each memory is an initial bad block or not; under the condition that the current block is an initial bad block, no identification operation is performed, and after the identification operation of the current block is completed by other memories, the identification operation of the next block is synchronously performed; accumulating the number of the identified newly generated bad blocks to obtain the number of the newly generated bad blocks of each logic unit in the memory which is an empty chip; writing back the identified newly generated bad blocks according to a preset rule; wherein the identifying operation comprises: under the condition that the current block is not an initial bad block, writing and reading data; judging whether the written data are consistent with the read data or not, if so, the current block is a non-bad block, otherwise, the current block is a newly generated bad block; and erasing data of the newly generated bad blocks.
Preferably, the writing data format comprises all 0 s, checkerboards and anti-checkerboards, and the writing, reading and erasing of the data in the former format are performed after the writing, reading and erasing of the data in the next format are performed.
Preferably, the method further comprises: after the data in the previous format is written, read and erased, judging whether the data in the current block is empty, and if the data in the current block is empty, carrying out the writing, reading and erasing of the data in the next format.
Preferably, determining whether the memory is acceptable based on the initial number of bad blocks and the newly generated number of bad blocks for each logical unit in the memory that is empty includes: if the sum of the number of the initial bad blocks of each logic unit and the number of the newly generated bad blocks in the memory which is the empty slice is not more than a preset number, judging that the memory is qualified; if the sum of the number of the initial bad blocks of any logic unit in the memory which is the empty slice and the number of the newly generated bad blocks exceeds the preset number, the memory is judged to be unqualified.
The application provides a NAND FLASH memory parallel test and bad block write-back method, which comprises the steps of firstly reading a plurality of memory IDs to judge whether each memory is preliminarily qualified, judging whether the 0 th block of each logic unit in the preliminarily qualified memory is a non-bad block or not under the condition that the memory is preliminarily qualified, respectively determining the initial bad block number of each logic unit in each memory under the condition that the 0 th block is the non-bad block, recognizing the bad block newly generated in the test process under the condition that the memory of each 0 th block is an empty chip, writing back the newly generated bad block according to a preset rule, and finally judging whether the memory is qualified or not based on the initial bad block number of each logic unit in the empty chip and the newly generated bad block number. The NAND FLASH memory parallel test and bad block write-back method can realize parallel test of a plurality of NAND FLASH memories, can effectively identify a bad block newly generated in the test process and write back, improves the test efficiency, and protects the preset original flag bit.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a flow chart of a method for parallel testing and bad block write-back of NAND FLASH memory according to the present application.
FIG. 2 is a schematic flow chart of step one in an embodiment of the present application.
FIG. 3 is a flow chart of the second step in the embodiment of the application.
Fig. 4 is a schematic flow chart of step three in the embodiment of the present application.
FIG. 5 is a flow chart of step four in an embodiment of the present application.
FIG. 6 is a flow chart of step five in an embodiment of the present application.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the application, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
FIG. 1 is a flow chart of a method for parallel testing and bad block write-back of NAND FLASH memory according to the present application. Referring to fig. 1, the present application proposes a NAND FLASH memory parallel test and bad block write-back method, which includes: step one, reading a plurality of memory IDs, comparing the memory IDs with preset IDs, and judging whether each memory is preliminarily qualified according to a comparison result; step two, judging whether the 0 th block of each Logic Unit (LUN) in the preliminarily qualified memory is a non-bad block or not under the condition that the memory is preliminarily qualified; step three, aiming at the 0 th block of each LUN as a non-bad block memory, respectively determining the initial bad block quantity of each LUN in each memory; judging whether the memory of which each 0 th block is a non-bad block is an empty piece or not; identifying the bad blocks newly generated in the test process under the condition that the memory of which each 0 th block is a non-bad block is an empty block, respectively determining the number of the bad blocks newly generated in each LUN in the memory of which the empty block is an empty block, and writing back the bad blocks newly generated according to a preset rule; and step six, judging whether the corresponding storage is qualified or not based on the initial bad block number of each LUN in the storage which is an empty piece and the newly generated bad block number.
In the first step of the application, if the memory ID is matched with the preset ID, the memory matched with the preset ID is judged to be preliminarily qualified; if the memory ID is not matched with the preset ID, the memory which is not matched with the preset ID is judged to be preliminarily disqualified. And then the memory with inconsistent data of the matched invalid pin and the data of the preset ID is positioned as the preliminarily failed memory by reading the data of the matched invalid pin.
In the second step of the present application, judging whether the 0 th block of each LUN in the preliminarily qualified storage is a non-bad block comprises the following steps: reading data of a 0 th block of each LUN in the preliminarily qualified memory; verifying whether the 0 th block is empty based on the read data; writing data into the 0 th block of each LUN in each memory with the 0 th block being empty; and reading the written data, judging whether the written data is consistent with the read data, if so, determining that the 0 th block is a non-bad block, otherwise, determining that the 0 th block is a bad block.
In the third step of the present application, determining the number of initial bad blocks of each LUN in each storage includes the following steps: reading a pre-marked bad block byte in each LUN in each memory; and accumulating the times of reading the bad block bytes to obtain the number of bad blocks of each LUN in each memory.
In the fourth step of the present application, judging whether the memory of which each 0 th block is a non-bad block is an empty block or not comprises the following steps: performing full-slice reading of all blocks on all LUNs of the memory with each 0 th block being a non-bad block, wherein the full-slice reading is traversing the blocks from the 0 th block to the Z-th block; judging whether the currently traversed block is an initial bad block or not; under the condition that the currently traversed block is not an initial bad block, data reading is carried out; under the condition that the currently traversed block is an initial bad block, data reading is not performed, and after the data reading of the currently traversed block is completed by other memories, the data reading of the next block is synchronously performed; if the data of all the blocks of all the LUNs read in the memory are empty, the memory with all the blocks of the data being empty is an empty slice; if the data of any block of any LUN read into the memory is non-empty, the memory of which the data of any block is non-empty is a non-empty slice.
In the fifth step of the present application, identifying the newly generated bad blocks in the testing process, determining the number of the newly generated bad blocks of each LUN in the empty memory, and writing back the newly generated bad blocks according to a predetermined rule includes: judging whether each block of each LUN of each memory is an initial bad block or not; under the condition that the current block is an initial bad block, no identification operation is performed, and after the identification operation of the current block is completed by other memories, the identification operation of the next block is synchronously performed; accumulating the number of the identified newly generated bad blocks to obtain the number of the newly generated bad blocks of each LUN in the memory which is an empty chip; writing back the identified newly generated bad blocks according to a preset rule; wherein the identifying operation comprises: under the condition that the current block is not an initial bad block, writing and reading data; judging whether the written data are consistent with the read data or not, if so, the current block is a non-bad block, otherwise, the current block is a newly generated bad block; and erasing data of the newly generated bad blocks.
In the sixth step of the present application, judging whether the memory is qualified based on the initial bad block number of each LUN in the memory which is empty and the newly generated bad block number comprises the following steps: if the sum of the number of the initial bad blocks of each LUN in the memory which is the empty sheet and the number of the newly generated bad blocks does not exceed the preset number, judging that the memory is qualified; if the sum of the number of the initial bad blocks of any LUN in the empty memory and the number of the newly generated bad blocks exceeds a preset number, judging that the memory is unqualified.
The writing data formats in the steps of the application comprise all 0 s, checkerboards and reverse checkerboards, and the writing, reading and erasing of the data in the former format are performed after the writing, reading and erasing of the data in the next format are performed. After the data in the previous format is written, read and erased, judging whether the data in the current block is empty, and if the data in the current block is empty, carrying out the writing, reading and erasing of the data in the next format.
In the method, the data reading operation is executed by a block reading module, the data writing operation is executed by a block programming module, the data erasing operation is executed by a block erasing module, the reading of bad block bytes is executed by a byte random reading module, and the writing back of bad blocks is executed by a byte random writing module; determining the number of the initial bad blocks through an initial bad block accumulation module; determining the number of the newly generated bad blocks to be executed by a new bad block accumulation module; the pulling-up operation of the bad block memory chip select signal is performed by a bad block processing module.
For ease of illustration, two embodiments of parallel testing of NAND FLASH memories and bad block write back are presented. FIG. 2 is a schematic flow chart of step one in an embodiment of the present application. Step one, reading a plurality of memory IDs and judging whether each memory is preliminarily qualified. Referring to fig. 2, a plurality of memory IDs are read, and if the memory ID does not match the preset ID, the memory that does not match the preset ID is determined to be preliminarily failed. And positioning the memory with inconsistent data of the matched invalid pin and the data of the preset ID as a preliminarily failed memory by reading the data of the matched invalid pin.
FIG. 3 is a flow chart of the second step in the embodiment of the application. And (3) assuming that the two memories are both preliminarily qualified, performing a step two, and judging whether the 0 th block of each LUN in the two preliminarily qualified memories is a non-bad block. Referring to fig. 3, through the block reading module, five byte entry addresses are addressed to the 0 th address of the 0 th block, the 0 th page, of the first LUN in the two memories, all data of the 0 th block are read, if all data of the 0 th block are all full high (FFH), the 0 th block is determined to be empty, the test is continued, and if all data of the 0 th block are not all FFH, the 0 th block is determined to be non-empty, and the test is terminated.
For the memory with the 0 th block of the first LUN being empty, addressing the 0 th address of the 0 th page 0 of the 0 th block of the first LUN in the two memories by the five byte entry addresses through the block programming module, and writing all data with the format of 0 th block into all 0; the method comprises the steps that through a block reading module, five byte inlet addresses are addressed to a 0 th address of a 0 th block and a 0 th page of a first LUN in two memories, all data of the 0 th block are read, and if all the data of the 0 th block are all 0, through a block erasing module, the five byte inlet addresses are addressed to the 0 th address of the 0 th block and the 0 th page of the first LUN in the two memories, all the data of the 0 th block are erased; then, through the block reading module, the five byte entry addresses are addressed to the 0 th block, the 0 th page and the 0 th address of the first LUN of each of the two memories, all data of the 0 th block are read, if all the data of the 0 th block are FFH, the 0 th block is judged to be empty, and then the data with the checkerboard format and the data with the anti-checkerboard format are respectively written in the mode. The test of block 0 of the next LUN is then performed on each of the two memories. Fig. 3 shows only the testing procedure of the first LUN of each of the two memories, the testing procedure of the other LUNs being identical to the testing procedure of the first LUN. If the writing and reading of the data in any format are inconsistent in the test process, the 0 th block of the corresponding memory is judged to be a bad block, and the memory to which the bad block belongs terminates the test. By reading the data of the failed pin, whether the failed memory is the first memory or the second memory is located, and the testing of the failed memory is terminated.
The writing data format in the application comprises all 0, checkerboard and anti-checkerboard, the writing, reading and erasing of the data in the former format are performed after the writing, reading and erasing of the data in the next format, the format sequence of the three writing data is not limited, and the three writing data can be interchanged. Wherein the format of the data is all 0, i.e. the written data are all 0. After the data in the previous format is written, read and erased, judging whether the data in the current block is empty, and if the data in the current block is empty, carrying out the writing, reading and erasing of the data in the next format. The fault coverage rate of the memory test depends on the format of the written data, and the data in three formats of all 0, checkerboard and reverse checkerboard are used for traversing respectively, so that common memory faults such as solid 0, solid 1, address decoding faults, short circuits, open circuits and the like can be covered, and the test fault coverage rate is increased to the greatest extent in the allowable range of test time.
Fig. 4 is a schematic flow chart of step three in the embodiment of the present application. Referring to fig. 4, assuming that the 0 th block of each LUN of the two memories is a non-bad block, step three is performed to determine the initial bad block number of each LUN in the two memories. Because the NAND FLASH memory contains an initial bad block, when leaving the factory, a manufacturer marks whether the block is a bad block or not on the flag bit of each block, namely the 0 th redundant byte of the 0 th page of the block, so that the subsequent use and test are convenient; if the data of the block flag bit is FFH, the block is a non-initial bad block, and if the data of the block flag bit is 00H, the block is an initial bad block.
And (3) addressing the 0 th redundant address of the 0 th block and the 0 th page of the 0 th block of the first LUN in the two memories through the byte random reading module, if the data is FFH, continuing to pass through the byte random reading module, addressing the 1 st block and the 0 th page of the 0 th redundant address of the first LUN in the two memories through the five byte inlet address, reading the data of the 0 th redundant address of the 1 st block and the 0 th page of the first LUN according to the FFH, sequentially performing testing on the 2 nd block to the X-1 th block of the first LUN according to the method until the data of the 0 th redundant address of the 0 th page of the X block and the 0 th page of the first LUN in the two memories is read through the byte random reading module, if the data is FFH, judging the source marked by the initial bad block module, if the initial bad block is from the first memory, adding 1 st bad block number register of the first memory, namely adding 1+ to the first block and M+ to the first block, namely, and adding the 1 st block to the first block and the 0 th block of the first LUN, and then performing testing on the first block and the Z+ to the first block until the data of the first block is the 0 th block and the 0 th block is accessed according to the 0 th block of the first buffer, and the first buffer is Z+Z. And then determining the initial bad block number of the next LUN according to the method. Fig. 4 shows only the testing procedure of the first LUN of each of the two memories, and the testing procedure of the other LUNs is the same as the testing procedure of the first LUN. By reading the data of the failed pin, whether the failed memory is the first memory or the second memory is located, and the testing of the failed memory is terminated. Wherein M1 represents an initial bad block number of the first memory; m1++ represents the initial bad block number register of the first memory plus 1; m2 represents the initial bad block number of the second memory; m2++ represents the initial bad block number register of the second memory plus 1; the Z-th block represents the last block.
FIG. 5 is a flow chart of step four in an embodiment of the present application. Referring to fig. 5, determining in step four whether each memory of which the 0 th block is a non-bad block is a null slice includes: the method comprises the steps of addressing five byte inlet addresses to 0 th redundant address of 0 th block and 0 th page of a first LUN in two memories through a byte random reading module, reading data of 0 th redundant byte of 0 th block and 0 th page of the 0 th LUN in the two memories, if the data is FFH, addressing five byte inlet addresses to 0 th address of 0 th block and 0 th page of the first LUN in the two memories through a block reading module, reading all data of the 0 th block, judging all data of the 0 th block to be FFH, then addressing five byte inlet addresses to 0 th redundant address of 1 st block and 0 th redundant byte of 1 st block and 0 th page of the 1 st block through a byte random reading module, if the data is FFH, the five byte entry addresses are addressed to the 0 th address of the 1 st block and the 0 th page of the first LUN in the two memories, all data of the 1 st block are read, all data of the 1 st block are judged to be FFH, then testing of the 2 nd block to the X-1 st block of the first LUN is sequentially carried out according to the method until the 0 th redundant address of the 0 th page of the X th block and the 0 th page of the first LUN in the two memories is addressed through a byte random reading module, data of the 0 th redundant byte of the X th block are read, if the data is 00H, the source of bad block labeling is judged through a bad block processing module, if the bad block is from the first memory, a chip selection signal CE1 of the first memory is pulled up until X+1 block is detected, and a control signal is assigned; if the bad block comes from the second memory, pulling up a chip selection signal CE2 of the second memory until an X+1 block is detected, and assigning a value to the control signal; then sequentially testing the X+1th block to the Y-1 th block of the first LUN according to the method until the five byte entry addresses are addressed to the 0 th redundant address of the 0 th page of the Y block of the first LUN in the two memories through the byte random reading module, reading the data of the 0 th redundant byte of the 0 th page of the Y block, if the data is FFH, the five byte entry addresses are addressed to the 0 th address of the 0 th page of the Y block of the first LUN in the two memories through the block reading module, reading all the data of the Y block, judging that all the data of the Y block are not FFH, and stopping the test, wherein the memory of the Y block containing all the data not FFH is a non-empty piece, and the other memory continues the test; and sequentially testing the Y+1th block to the Z-1 th block of the first LUN according to the method until the five byte entry addresses are addressed to the 0 th redundant address of the 0 th page of the Z th block of the first LUN in the two memories through the byte random reading module, reading the data of the 0 th redundant byte of the 0 th page of the Z th block, if the data is FFH, the five byte entry addresses are addressed to the 0 th address of the 0 th page of the Z th block of the first LUN in the two memories through the block reading module, reading all the data of the Z th block, and judging that all the data of the Z th block are FFH, thereby completing the test of all the blocks of the first LUN of the two memories. Each block of the next LUN is then tested for empty as described above. Fig. 5 shows only the testing procedure of the first LUN of each of the two memories, and the testing procedure of the other LUNs is the same as the testing procedure of the first LUN. By reading the data of the failed pin, whether the failed memory is the first memory or the second memory is located, and the testing of the failed memory is terminated.
FIG. 6 is a flow chart of step five in an embodiment of the present application. Referring to fig. 6, assuming that the two memories whose 0 th block is a non-bad block are empty, step five is performed to identify bad blocks newly generated in the testing process, determine the number of bad blocks newly generated in each LUN in the two memories, and write back the new bad blocks according to a predetermined rule. The method comprises the steps that through a byte random reading module, five byte inlet addresses are addressed to a 0 th redundant address of a 0 th block and a 0 th page of a first LUN in two memories, data of the 0 th redundant byte of the 0 th block and the 0 th page of the 0 th page are read, if the data are FFH, the five byte inlet addresses are addressed to the 0 th address of the 0 th block and the 0 th page of the first LUN in the two memories through a block programming module, and the data are all written into the 0 th block in a format of all 0; the method comprises the steps that through a block reading module, five byte inlet addresses are addressed to a 0 th address of a 0 th block and a 0 th page of a first LUN in two memories, all data of the 0 th block are read, and if all the data of the 0 th block are all 0, through a block erasing module, the five byte inlet addresses are addressed to the 0 th address of the 0 th block and the 0 th page of the first LUN in the two memories, all the data of the 0 th block are erased; then, addressing the five byte entry addresses to the 0 th block, the 0 th page and the 0 th address of the first LUN in the two memories through a block reading module, reading all data of the 0 th block, judging that the 0 th block is empty if all the data of the 0 th block are FFH, and then respectively writing data with a checkerboard format and data with an inverse checkerboard format in the mode; then sequentially testing the 1 st block to the X-1 st block of the first LUN according to the method until the five byte entry addresses are addressed to the 0 th redundant address of the 0 th page of the X th block of the first LUN in the two memories through a byte random reading module, reading the data of the 0 th redundant byte of the 0 th page of the X th block, judging the source of bad block marking through a bad block processing module if the data is 00H, and pulling up a chip selection signal CE1 of the first memory if the bad block is from the first memory until the control signal is assigned when X+1 block is detected; if the bad block comes from the second memory, pulling up a chip selection signal CE2 of the second memory until an X+1 block is detected, and assigning a value to the control signal; then sequentially testing the X+1th block to the Y-1 th block of the first LUN according to the method until the five byte entry addresses are addressed to the 0 th redundant address of the 0 th page of the Y-th block of the first LUN in the two memories through a byte random reading module, reading the data of the 0 th redundant byte of the 0 th page of the Y-th block, and if the data is FFH, addressing the 0 th address of the 0 th page of the Y-th block of the first LUN in the two memories through a block programming module, wherein all writing formats of the data are all 0 for the Y-th block; the method comprises the steps that through a block reading module, five byte inlet addresses are addressed to a 0 th address of a 0 th page of a Y-th block of a first LUN in two memories, all data of the Y-th block are read, if all the data of the Y-th block are not all 0, a source of a new generation bad block label is judged through a new bad block number accumulation module, if the new generation bad block is from the first memory, a new generation bad block number register of the first memory is added with 1, namely N1++, and if the new generation bad block is from the second memory, a new generation bad block number register of the second memory is added with 1, namely N2++; then erasing the newly generated bad block of the invalid memory by a block erasing module, writing the flag bit of the block back to 00H by a byte random writing module, and finally pulling up the chip selection signal CE of the block until a Y+1 block is detected, and assigning a value to the control signal; and then testing the Y+1st block to the Z block of the first LUN in sequence according to the method, so as to finish testing all blocks of the first LUNs of the two memories. The next LUN test is then performed as described above. Fig. 6 shows only the testing procedure of the first LUN of each of the two memories, and the testing procedure of the other LUNs is the same as the testing procedure of the first LUN.
In the sixth step, determining whether the corresponding storage is qualified based on the initial number of bad blocks and the newly generated number of bad blocks of each LUN in the storage that is empty includes: if the sum of M1 plus N1 of each LUN in the empty memory is not more than the preset number, judging that the first memory is qualified; if the sum of the number M1 of the initial bad blocks of any LUN in the empty memory and the number N1 of the newly generated bad blocks exceeds a preset number, the first memory is judged to be unqualified. If the sum of M < 2+ > and N < 2 > of each LUN in the empty memory is not more than the preset number, judging that the second memory is qualified; if the sum of the number M2 of the initial bad blocks of any LUN in the empty memory and the number N2 of the newly generated bad blocks exceeds a preset number, the second memory is judged to be unqualified.
Although the above embodiment describes parallel test write back of two memories, it is merely exemplary and not intended to limit the present application. Specifically, the method is also applicable to parallel testing of three or more memories and bad block write-back.
According to the embodiment, the parallel test and bad block write-back method for the NAND FLASH memory can realize the parallel test of a plurality of NAND FLASH memories, can effectively identify the bad blocks newly generated in the test process and write back, improves the test efficiency, and protects the preset original flag bits.
In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present application.
The foregoing is merely illustrative of the embodiments of the present application, and the scope of the present application is not limited thereto, and any changes or substitutions that may be made by those skilled in the art without departing from the inventive concept are intended to be included within the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope defined by the claims.
Claims (10)
1. A NAND FLASH memory parallel test and bad block write back method, the method comprising:
reading a plurality of memory IDs, comparing the memory IDs with preset IDs, and judging whether each memory is preliminarily qualified according to a comparison result;
judging whether the 0 th block of each logic unit in the memory which is preliminarily qualified is a non-bad block or not under the condition that the memory is preliminarily qualified;
determining the initial bad block number of each logic unit in each memory according to the memory of which the 0 th block of each logic unit is a non-bad block;
judging whether the memory of which each 0 th block is a non-bad block is an empty chip or not;
identifying the bad blocks newly generated in the test process under the condition that the memory of which each 0 th block is a non-bad block is an empty block, respectively determining the number of the bad blocks newly generated in each logic unit in the memory of which the empty block is an empty block, and writing back the bad blocks newly generated according to a preset rule;
and judging whether the corresponding memory is qualified or not based on the initial bad block number of each logic unit in the memory which is empty and the newly generated bad block number.
2. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: judging whether each memory is preliminarily qualified according to the comparison result comprises the following steps:
if the memory ID is matched with the preset ID, judging that the memory matched with the ID is preliminarily qualified;
if the memory ID is not matched with the preset ID, the memory with the unmatched ID is judged to be preliminarily disqualified.
3. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 2, wherein: the method further comprises the steps of:
reading data matched with the invalid pin;
and positioning the memory with inconsistent data of the matched invalid pin and the data of the preset ID as a preliminarily failed memory.
4. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: the determining whether the 0 th block of each logic unit in the preliminarily qualified memory is a non-bad block includes:
reading data of the 0 th block of each logic unit in the preliminarily qualified memory;
verifying whether the 0 th block is empty based on the read data;
writing data to the 0 th block of each logic unit in each memory where the 0 th block is empty;
and reading the written data, judging whether the written data is consistent with the read data, if so, determining that the 0 th block is a non-bad block, otherwise, determining that the 0 th block is a bad block.
5. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: the determining the initial bad block number of each logic unit in each memory includes:
reading pre-marked bad block bytes in each logic unit in each memory;
and accumulating the times of reading the bad block bytes to obtain the number of the bad blocks of each logic unit in each memory.
6. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: the determining whether the memory of each 0 th block is a non-bad block is a null slice includes:
performing full-slice reading of all blocks on all logic units of the memory with each 0 th block being a non-bad block, wherein the full-slice reading is traversing the blocks from the 0 th block to the Z th block;
judging whether the currently traversed block is an initial bad block or not;
under the condition that the currently traversed block is not an initial bad block, data reading is carried out;
under the condition that the currently traversed block is an initial bad block, data reading is not performed, and after the data reading of the currently traversed block is completed by other memories, the data reading of the next block is synchronously performed;
if the data of all the blocks of all the logic units in the memory are read to be empty, the memory with all the blocks of the data being empty is an empty slice;
if the data of any one block of any one logic unit in the memory is non-empty, the memory with the data of any one block being non-empty is a non-empty slice.
7. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: the identifying the newly generated bad blocks in the testing process, determining the number of the newly generated bad blocks of each logic unit in the memory which is the empty chip respectively, and writing back the newly generated bad blocks according to a preset rule comprises the following steps:
judging whether each block of each logic unit of each memory is an initial bad block or not;
under the condition that the current block is an initial bad block, no identification operation is performed, and after the identification operation of the current block is completed by other memories, the identification operation of the next block is synchronously performed;
accumulating the number of the identified newly generated bad blocks to obtain the number of the newly generated bad blocks of each logic unit in the memory which is an empty chip;
writing back the identified newly generated bad blocks according to a preset rule;
wherein the identifying operation comprises:
under the condition that the current block is not an initial bad block, writing and reading data;
judging whether the written data are consistent with the read data or not, if so, the current block is a non-bad block, otherwise, the current block is a newly generated bad block;
and erasing data of the newly generated bad blocks.
8. A NAND FLASH memory parallel test and bad block write back method according to any one of claims 4 or 7, wherein: the writing data format comprises all 0, checkerboard and reverse checkerboard, and the writing, reading and erasing of the data in the former format are performed after the writing, reading and erasing of the data in the next format are performed.
9. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 8, wherein: the method further comprises the steps of: after the data in the previous format is written, read and erased, judging whether the data in the current block is empty, and if the data in the current block is empty, carrying out the writing, reading and erasing of the data in the next format.
10. The method for parallel testing and bad block write-back of NAND FLASH memory of claim 1, wherein: the determining whether the memory is qualified based on the initial bad block number and the newly generated bad block number of each logic unit in the memory which is empty comprises the following steps:
if the sum of the number of the initial bad blocks of each logic unit and the number of the newly generated bad blocks in the memory which is the empty slice is not more than a preset number, judging that the memory is qualified;
if the sum of the number of the initial bad blocks of any logic unit in the memory which is the empty slice and the number of the newly generated bad blocks exceeds the preset number, the memory is judged to be unqualified.
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