CN113176970B - System and method for managing bad blocks of nor flash based on FPGA - Google Patents

System and method for managing bad blocks of nor flash based on FPGA Download PDF

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CN113176970B
CN113176970B CN202110716395.5A CN202110716395A CN113176970B CN 113176970 B CN113176970 B CN 113176970B CN 202110716395 A CN202110716395 A CN 202110716395A CN 113176970 B CN113176970 B CN 113176970B
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block
flash
bad block
backup
bad
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CN113176970A (en
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汪亨
刘明星
吴志强
张文帅
赵洋
魏荣超
谌志强
徐孝芬
陈起
水璇璇
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Nuclear Power Institute of China
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2094—Redundant storage or storage space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention discloses a system and a method for managing a nor flash bad block based on an FPGA (field programmable gate array), comprising a main nor flash module, a backup nor flash module and a nor flash controller; when a block in the main nor flash module fails, the nor flash controller constructs a mapping relation between the failed block and an available backup block in the backup nor flash module, and replaces the failed block with the available backup block according to the mapping relation. The invention aims to provide a system and a method for managing a bad block of a nor flash based on an FPGA (field programmable gate array), which can automatically manage the bad block when the nor flash is abnormal in storage operation and solve the problems of aging and accidental block faults of the nor flash due to long-time use.

Description

System and method for managing bad blocks of nor flash based on FPGA
Technical Field
The invention relates to the technical field of safety-level digital control of nuclear power plants, in particular to a system and a method for managing a nor flash bad block based on an FPGA (field programmable gate array).
Background
The digital control system of the nuclear power plant and other systems with higher safety level require high safety of data storage, and the normal operation of the whole storage chip cannot be influenced by accidental faults. However, after a long time of use, the nor flash chip is frequently written and erased many times, and it is difficult to avoid some block failures inside the chip. The nor flash chip can only report faults and does not process an error correction mechanism, which is unacceptable for a system with higher safety requirement.
Disclosure of Invention
The invention aims to provide a system and a method for managing a bad block of a nor flash based on an FPGA (field programmable gate array), which can automatically manage the bad block when the nor flash is abnormal in storage operation and solve the problems of aging and accidental block faults of the nor flash due to long-time use.
The invention is realized by the following technical scheme:
the NOR flash bad block management system based on the FPGA comprises a main NOR flash module, a backup NOR flash module and a NOR flash controller; when a block in the main nor flash module fails, the nor flash controller constructs a mapping relation between the failed block and an available backup block in the backup nor flash module, and replaces the failed block with the available backup block according to the mapping relation.
Preferably, the main nor flash module comprises a main nor flash, a bad block flag table and a bad block number table;
the bad block mark table is used for identifying a fault block in the main nor flash; the available spare blocks which are in mapping relation with the fault blocks are recorded;
and the bad block number table is used for numbering the fault blocks identified in the bad block mark table.
Preferably, the bad block flag table includes a flag bit and a number bit;
the flag bit is used for identifying the fault block in the primary nor flash;
the number bit is used for identifying the available backup blocks which have mapping relation with the fault blocks.
Preferably, the backup nor flash comprises a backup nor flash and a bad block replacement table; and the bad block replacement table is used for identifying the positions of the available backup blocks in the backup nor flash.
The use method of the nor flash bad block management system based on the FPGA comprises the following steps:
s1: obtaining a bad block replacement table;
s2: constructing a bad block mark table and a bad block number table;
s3: constructing a mapping relation according to the bad block replacement table and the bad block number table;
s4: and writing the position of the available backup block corresponding to the fault block into the bad block mark table according to the mapping relation.
Preferably, the bad block replacement table includes one-to-one corresponding mark bits and address bits;
the mark bit is used for identifying the position of the available backup block in the backup nor flash;
the address bits are used for identifying the block address of the available backup blocks.
Preferably, the S1 includes the following substeps:
s11: obtaining an available backup block in the backup nor flash;
s12: marking the position of the available backup block in the backup nor flash at the reference number bit;
s13: and identifying the block address of the available backup block at the address bit corresponding to the label bit.
Preferably, the S2 includes the following substeps:
s21: judging whether a block in the primary nor flash fails, and if the current block is a failure block, executing S22;
s22: identifying the fault block to obtain the bad block mark table;
s22: identifying the fault block to obtain the bad block mark table;
s23: and marking the fault blocks in the bad block mark table to obtain the bad block number table.
Preferably, the S21 includes the following substeps:
s211: performing read operation, write operation and erase operation on the blocks in the main nor flash;
s212: if the read operation, the write operation and the erase operation can be completed, the block is a normal block; otherwise, it is a failure block.
Preferably, the bad block flag table includes a flag bit and a number bit;
the flag bit is used for identifying the fault block in the primary nor flash;
the number bit is used for identifying the available backup blocks which have mapping relation with the fault blocks.
Compared with the prior art, the invention has the following advantages and beneficial effects:
by replacing the available backup block in the backup nor flash and the fault block in the main nor flash which actually runs, the normal work of the nor flash can be ensured when the accidental block fault occurs, the use reliability of the nor flash is improved, and the service life of the nor flash is prolonged.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
FIG. 1 is a general schematic diagram of a nor flash bad block management system according to the present invention;
FIG. 2 is a diagram of the management system of the nor flash bad block after initialization;
FIG. 3 is a diagram illustrating a case where there is no faulty block in front of a block where a primary nor flash is running;
fig. 4 is a schematic diagram of the present invention when a fault block exists in front of a block in which a primary nor flash is running.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.
Example 1
The NOR flash bad block management system based on the FPGA comprises a main NOR flash module, a backup NOR flash module and a NOR flash controller; when a block in the main nor flash module fails, the nor flash controller constructs a mapping relation between the failed block and an available backup block in the backup nor flash module, and replaces the failed block with the available backup block according to the mapping relation.
In this embodiment, the available backup block refers to a block that has no failure in the backup nor flash, that is: blocks that can perform read, write, and erase operations.
Specifically, in this embodiment, the primary nor flash module includes a primary nor flash, a bad block flag table, and a bad block number table;
a bad block flag table, including a flag bit and a number bit, where the flag bit is used to identify a fault block in a primary nor flash, as shown in fig. 1 and 2, in fig. 1, the fault block in the primary nor flash is represented by 0, and a good block (a block without fault) is represented by 1; the number bits are used to identify the available backup blocks that have a mapping relationship with the failed block, and as shown in fig. 2 and fig. 3, the number bits of the good block are marked as 0xff, and the number bits of the failed block are marked as the number corresponding to the available backup blocks.
And the bad block number table is used for numbering the fault blocks identified in the bad block mark table. The bad block number table is constructed by two methods:
the first construction method comprises the steps that numbers are stored in advance in a bad block number table, the numbers are sequentially increased from small to large, when a current block in a main nor flash fails, the current block is the second fault block in the main nor flash, and the fault blocks correspond to the numbers in the bad block number table one by one; for example, the numbers 0, 1, 2, 3, and.
In the second construction method, the bad block number table is empty, and when a fault block is detected in the main nor flash, the bad block number table is filled in sequence, so that a one-to-one correspondence relationship is formed; for example, when a fault block is detected in the primary nor flash, a number 0 is filled in the bad block flag table, and when a fault block is detected in the primary nor flash again, a number recorded last in the bad block flag table is added with 1, so as to form a corresponding relationship.
When the second construction method is used, the nor flash controller is required to construct a mapping relation with the bad block mark table in real time according to the bad block number table, the workload of the system is increased, and the operation efficiency is reduced.
The backup nor flash comprises a backup nor flash and a bad block replacement table; and the bad block replacement table is used for identifying the positions of the available backup blocks in the backup nor flash.
Specifically, in this embodiment, the bad block replacement table includes a one-to-one correspondence of a flag bit and an address bit, and in an initial state, both the flag bit and the address bit are empty; when a bad block replacement table needs to be constructed, reading, writing and erasing operations are performed on each block in the backup nor flash, whether the block in the backup nor flash has a fault is checked, if the block in the backup nor flash does not have the fault, the block is considered to be an available backup block, the position of the available backup block in the backup nor flash is recorded in a label bit, and the block address of the available backup block is written in an address bit, so that one-to-one corresponding label bit and address bit are formed, as shown in fig. 1 to 4, and the position of the available backup block is represented by a sequence number in fig. 1 to 4.
According to the scheme, the positions and block addresses of available backup blocks are recorded in a bad block replacement table, the numbers of fault blocks are recorded in a bad block number table, the positions of the fault blocks and the positions of the available backup blocks form a one-to-one correspondence relationship by constructing the mapping relationship between the bad block replacement table and the bad block number table, when a block in a main nor flash fails, the available backup blocks in the backup main nor flash can be used for replacing the corresponding fault blocks according to the mapping relationship, and therefore the phenomenon that the main nor flash cannot work normally due to the abnormity is solved.
The following explains a specific implementation process of the scheme:
when no fault block exists in front of the block in which the main nor flash is running:
firstly, initializing a bad block mark table and a bad block replacement table, as shown in fig. 2;
initializing a bad block flag table:
since the state (good block or failure block) of each block in the primary nor flash is unknown in advance, each block defaulted as the primary nor flash is a good block and is denoted by 1 at the time of initialization, that is: all the flag bits in the bad block flag table are 1, and all the number bits in the bad block flag table are 0 xff;
initializing a bad block replacement table:
the method comprises the following steps that a nor flash manager and an interface drive automatically search for available backup blocks in a backup nor flash, namely, a series of operations such as reading, writing and erasing are carried out on each block of the backup nor flash, whether the block in the backup nor flash has a fault is reported is checked, if yes, the block is considered to be a bad block, if not, the block is considered to be an available backup block, and the block address and the position of the available backup block are stored in a bad block replacement table;
and after the bad block replacement table and the bad block mark table are initialized, the nor flash controller constructs a mapping relation according to the bad block replacement table and the bad block mark table.
After the initialization is completed, the system starts normal work, as shown in fig. 3, if the main nor flash encounters a fault in the running operation (reading, writing or erasing), that is, a block in the main nor flash has a fault, after the last operation is completed, 0 is written in the flag bit corresponding to the bad block flag table, and meanwhile, a corresponding relationship is formed according to the number of the fault block and the number in the bad block number table, and then the number of the corresponding available backup block is searched in the bad block replacement table according to the number corresponding to the fault block, and the number bit in the bad block flag table is written in; and finally, replacing the address of the bad block and the chip selection signal in the main nor flash by an available backup block, and performing the same operation (reading, writing or erasing) on the available backup block again.
When a fault block exists in front of a block in which the primary nor flash is running:
firstly, initializing a bad block mark table and a bad block replacement table, as shown in fig. 2;
initializing a bad block flag table:
since the state (good block or failure block) of each block in the primary nor flash is unknown in advance, each block defaulted as the primary nor flash is a good block and is denoted by 1 at the time of initialization, that is: all the flag bits in the bad block flag table are 1, and all the number bits in the bad block flag table are 0 xff;
reading a last stored bad block mark table, correcting a mark bit in a current bad block mark table by using the last established bad block mark table, if a certain block is a fault block, carrying out bad block replacement table addressing on the fault block according to a serial number bit in the last established bad block mark table, finding the position of an available backup block, and automatically replacing a block operation address and a chip selection signal of a main nor flash fault block; if it is a good block, no operation is performed.
Initializing a bad block replacement table:
the method comprises the steps that a nor flash manager and an interface drive automatically search for a good block in a backup nor flash, namely, a series of operations such as reading, writing and erasing are carried out on each block of the backup nor flash, whether the block in the backup nor flash has a fault is reported is checked, if yes, the block is considered to be a bad block, if not, the block is considered to be an available backup block, and the block address of the available backup block is stored in a bad block replacement table
After the initialization is completed, normal work is started, as shown in fig. 3, if the main nor flash encounters a fault in the running operation (reading, writing or erasing), that is, a block in the main nor flash fails, after the last operation is completed, 0 is written in the flag bit corresponding to the bad block flag table, and meanwhile, the fault block is numbered according to the bad block number table, and then the number of the available backup block corresponding to the bad block replacement table is searched according to the bad block number table and written in the bad block flag table; and finally, replacing the address of the bad block and the chip selection signal in the main nor flash by an available backup block, and performing the same operation (reading, writing or erasing) on the available backup block again.
Example 2
The embodiment provides a use method of a nor flash bad block management system based on an FPGA, which comprises the following steps:
s1: obtaining a bad block replacement table;
in this embodiment, the bad block replacement table includes a one-to-one correspondence of a flag bit and an address bit, and in an initial state, both the flag bit and the address bit are empty; when a bad block replacement table needs to be constructed, reading, writing and erasing operations are performed on each block in the backup nor flash, whether the block in the backup nor flash has a fault is checked, if the block in the backup nor flash does not have the fault, the block is considered to be an available backup block, the position of the available backup block in the backup nor flash is recorded in a label bit, and the block address of the available backup block is written in an address bit, so that one-to-one corresponding label bit and address bit are formed, as shown in fig. 1 to 4, and the position of the available backup block is represented by a sequence number in fig. 1 to 4.
S2: constructing a bad block mark table and a bad block number table;
the bad block flag table in this embodiment includes a flag bit and a number bit, where the flag bit is used to identify a fault block in a primary nor flash, as shown in fig. 1 and 2, in fig. 1, the fault block in the primary nor flash is represented by 0, and a good block (a block that does not have a fault) is represented by 1; the number bits are used to identify the available backup blocks that have a mapping relationship with the failed block, and as shown in fig. 2 and fig. 3, the number bits of the good block are marked as 0xff, and the number bits of the failed block are marked as the number corresponding to the available backup blocks.
And the bad block number table is used for numbering the fault blocks identified in the bad block mark table. The bad block number table is constructed by two methods:
the first construction method comprises the steps that numbers are stored in advance in a bad block number table, the numbers are sequentially increased from small to large, when a current block in a main nor flash fails, the current block is the second fault block in the main nor flash, and the fault blocks correspond to the numbers in the bad block number table one by one; for example, the numbers 0, 1, 2, 3, and.
In the second construction method, the bad block number table is empty, and when a fault block is detected in the main nor flash, the bad block number table is filled in sequence, so that a one-to-one correspondence relationship is formed; for example, when a fault block is detected in the primary nor flash, a number 0 is filled in the bad block flag table, and when a fault block is detected in the primary nor flash again, a number recorded last in the bad block flag table is added with 1, so as to form a corresponding relationship.
When the second construction method is used, the nor flash controller is required to construct a mapping relation with the bad block mark table in real time according to the bad block number table, the workload of the system is increased, and the operation efficiency is reduced.
S3: constructing a mapping relation according to the bad block replacement table and the bad block number table;
s4: and writing the available backup blocks corresponding to the fault blocks into the bad block mark table according to the mapping relation.
The positions and block addresses of available backup blocks are recorded in a bad block replacement table, the numbers of fault blocks are recorded in a bad block number table, the positions of the fault blocks and the positions of the available backup blocks form a one-to-one correspondence relationship by constructing the mapping relationship between the bad block replacement table and the bad block number table, and when a block in a main nor flash fails, the corresponding fault block can be replaced by the available backup block in the backup main nor flash according to the mapping relationship, so that the phenomenon that the main nor flash cannot work normally due to the abnormity is solved.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. The system for managing the bad blocks of the nor flash based on the FPGA is characterized by comprising a main nor flash module, a backup nor flash module and a nor flash controller; when a block in the main norflash module fails, the norflash controller constructs a mapping relation between the failed block and an available backup block in the backup norflash module, and replaces the address and the chip selection signal of the bad block in the main norflash module with the available backup block according to the mapping relation;
the main nor flash module comprises a main nor flash, a bad block mark table and a bad block number table;
the bad block mark table is used for identifying a fault block in the main nor flash; further operable to identify the available backup blocks that have a mapping relationship with the failed block;
the bad block number table is used for numbering the fault blocks identified in the bad block mark table;
the bad block mark table comprises a mark bit and a number bit;
the flag bit is used for identifying the fault block in the primary nor flash;
the number bit is used for identifying the available backup blocks with mapping relation with the fault blocks;
the backup nor flash comprises a backup nor flash and a bad block replacement table; and the bad block replacement table is used for identifying the position of the available backup block in the backup nor flash.
2. The method for using the FPGA-based nor flash bad block management system according to claim 1, comprising the steps of:
s1: obtaining a bad block replacement table;
s2: constructing a bad block mark table and a bad block number table;
s3: constructing a mapping relation according to the bad block replacement table and the bad block number table;
s4: and writing the position of the available backup block corresponding to the fault block into the bad block mark table according to the mapping relation.
3. The method for using the FPGA-based nor flash bad block management system according to claim 2, wherein the bad block replacement table includes a one-to-one correspondence of a mark bit and an address bit;
the mark bit is used for identifying the position of the available backup block in the backup nor flash;
the address bits are used for identifying the block address of the available backup blocks.
4. The method for using the FPGA-based nor flash bad block management system according to claim 3, wherein the S1 comprises the following sub-steps:
s11: obtaining an available backup block in the backup nor flash;
s12: marking the position of the available backup block in the backup nor flash at the reference number bit;
s13: and identifying the block address of the available backup block at the address bit corresponding to the label bit.
5. The method for using the FPGA-based nor flash bad block management system according to claim 2, wherein the S2 comprises the following sub-steps:
s21: judging whether a block in the primary nor flash fails, and if the current block is a failure block, executing S22;
s22: identifying the fault block to obtain the bad block mark table;
s23: and marking the fault blocks in the bad block mark table to obtain the bad block number table.
6. The method for using the FPGA-based nor flash bad block management system according to claim 2, wherein the S21 comprises the following sub-steps:
s211: performing read operation, write operation and erase operation on the blocks in the main nor flash;
s212: if the read operation, the write operation and the erase operation can be completed, the block is a normal block; otherwise, it is a failure block.
7. The use method of the FPGA-based nor flash bad block management system according to claim 6, wherein the bad block flag table comprises a flag bit and a number bit;
the flag bit is used for identifying the fault block in the primary nor flash;
the number bit is used for identifying the available backup blocks which have mapping relation with the fault blocks.
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