CN113299335B - Test method, test system and test equipment for memory device - Google Patents
Test method, test system and test equipment for memory device Download PDFInfo
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- CN113299335B CN113299335B CN202110566367.XA CN202110566367A CN113299335B CN 113299335 B CN113299335 B CN 113299335B CN 202110566367 A CN202110566367 A CN 202110566367A CN 113299335 B CN113299335 B CN 113299335B
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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Abstract
The application provides a test method, a test system and a test device of a storage device, comprising the following steps: obtaining bad block information of a first logic unit and a second logic unit; performing burn-in test on a first logic unit and a second logic unit in the memory device by using the same enable signal; according to the bad block information, the enabling signal is coded to obtain a mask of the first logic unit and the second logic unit; and outputting the mask. Therefore, the test method of the memory device provided by the embodiment of the application can encode the enable signal by using the same enable signal and the bad block information to obtain the masks respectively corresponding to the first logic unit and the second logic unit, and can intuitively know whether the bad pixels exist in the first logic unit and the second logic unit according to the output result of the masks.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a test method, a test system, and a test apparatus for a memory device.
Background
Currently, burn-in testing is performed on a memory device, and a plurality of logic units can be tested one by one to obtain the burn-in condition of the memory device over the use time. Each Logical Unit has a Logical Unit Number (LUN), which is a Number used to identify one Logical Unit.
Because the aging test is carried out on the storage device at present, one LUN is adopted to be tested and then another LUN is tested continuously, and if the LUN has a dead pixel, the recording is carried out, so that the aging test method has long test time. If two parallel LUNs are used for testing, the testing time can be saved, but the defective pixel of which LUN can appear cannot be output, namely, the defective pixel information cannot be accurately output when the parallel LUNs are tested.
That is to say, the current storage device aging test method cannot save test time and accurately output LUN bad block information.
Disclosure of Invention
In view of this, an object of the present application is to provide a method, a system and a device for testing a storage device, which can save testing time and accurately output LUN bad block information.
The embodiment of the application provides a method for testing a memory device, which comprises the following steps:
obtaining bad block information of a first logic unit and a second logic unit;
performing burn-in test on a first logic unit and a second logic unit in the memory device by using the same enable signal;
according to the bad block information, the enabling signal is coded to obtain a mask of the first logic unit and the second logic unit;
and outputting the mask.
Optionally, the aging test includes a process of data erasing, data reading, data writing and data reading performed in a cycle;
further comprising:
storing bad block information obtained by performing aging test on the first logic unit and the second logic unit last time;
the obtaining the bad block information of the first logic unit and the second logic unit includes:
and obtaining the bad block information of the first logic unit and the second logic unit stored in the last aging test.
Optionally, the mask corresponds to a waveform.
Optionally, the outputting the mask includes:
if the first logic unit has a bad block, the mask is output to be a high level at a position corresponding to the first logic unit, and if the first logic unit does not have a bad block, the mask is output to be a low level at a position corresponding to the first logic unit;
if the second logic unit has a bad block, the mask is output at a high level at a position corresponding to the second logic unit, and if the second logic unit does not have a bad block, the mask is output at a low level at a position corresponding to the second logic unit.
Optionally, the mask and the enable signal jointly drive the first logic unit and the second logic unit to work.
Optionally, the memory device is a NAND device.
An embodiment of the present application provides a test system for a memory device, including: the device comprises a mask unit, a control unit, a bad block information storage unit, a first logic unit and a second logic unit;
the mask unit is used for providing an enable signal to provide the same enable signal for the first logic unit and the second logic unit, and coding the same enable signal to obtain a mask of the same enable signal;
the control unit is used for controlling the first logic unit and the second logic unit to work according to the same enable signal and the mask;
the bad block information storage unit is used for storing the bad block information of the first logic unit and the second logic unit obtained by the last aging test.
Optionally, the mask unit is specifically configured to encode the same enable signal according to the bad block information of the first logic unit and the second logic unit stored in the bad block information storage unit to obtain a mask of the first logic unit and the second logic unit.
Optionally, the bad block information storage unit is specifically configured to store an address and bad block information of the first logic unit, and store an address and bad block information of the second logic unit.
Optionally, the number of masks is equal to the number of addresses.
The embodiment of the application provides a test device of a storage device, and the storage device is tested by adopting the test system in any one of the test system embodiments.
The method for testing the memory device provided by the embodiment of the application comprises the following steps: obtaining bad block information of a first logic unit and a second logic unit; performing burn-in test on a first logic unit and a second logic unit in the memory device by using the same enable signal; according to the bad block information, coding the enabling signal to obtain a mask of the first logic unit and the second logic unit; and outputting the mask.
Therefore, the method for testing the memory device provided by the embodiment of the application can encode the enable signal by using the same enable signal and the bad block information to obtain the masks respectively corresponding to the first logic unit and the second logic unit, and can intuitively know whether the first logic unit and the second logic unit have the bad point according to the output result of the masks.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating a method of testing a memory device according to the prior art;
FIG. 2 is a flow chart illustrating a method for testing a memory device according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating a method for testing a memory device according to an embodiment of the present application;
FIG. 4 is a block diagram illustrating a test system for a memory device according to an embodiment of the present application.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the device structures are not enlarged partially in general scale for the sake of illustration, and the drawings are only examples, which should not limit the scope of protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background, burn-in testing refers to repeating the process of data erasing, data reading, data writing, and data reading for a memory device in order to observe changes in the performance of the memory device over time. Currently, burn-in testing is performed on a memory device, and a plurality of logic units can be tested one by one so as to obtain the burn-in condition of the memory device along with the use time. Each Logical Unit has a Logical Unit Number (LUN), which is a Number used to identify a Logical Unit.
Because the aging test is carried out on the storage device at present, one LUN is adopted to be tested and then another LUN is tested continuously, and if the LUN has a dead pixel, the recording is carried out, so that the aging test method has long test time. Referring to fig. 1, which is a schematic diagram illustrating a testing method of a memory device in the prior art, CE in fig. 1 is an enable signal, and when the enable signal is at a low level, the signal is active and can drive a logic unit LUN to operate. Transfer Time in fig. 1 is a process of transferring data into a buffer, and Program Time is a process of transferring data from the buffer to a storage area. When the enable signal is valid, the mask of the enable signal is synchronously output in the driving process to output the information whether the LUN has the bad block, and the information of the LUN bad block at this time is recorded for storage.
If two parallel LUNs are used for testing, that is, program times of the two LUNs are simultaneously performed, test Time can be saved, but it is impossible to output which LUN has a dead pixel, that is, when parallel LUN testing is performed, a mask of an enable signal cannot accurately output dead pixel information or the mask of the enable signal cannot distinguish which LUN has a dead pixel, and at this Time, the dead block information of the LUN cannot be correctly recorded and stored.
That is, the current storage device aging test method cannot save test time and accurately output and record LUN bad block information.
Based on this, an embodiment of the present application provides a method for testing a memory device, including: obtaining bad block information of a first logic unit and a second logic unit; performing burn-in test on a first logic unit and a second logic unit in the memory device by using the same enable signal; according to the bad block information, the enabling signal is coded to obtain a mask of the first logic unit and the second logic unit; and outputting the mask.
Therefore, the method for testing the memory device provided by the embodiment of the application can encode the enable signal by using the same enable signal and the bad block information to obtain the masks respectively corresponding to the first logic unit and the second logic unit, can intuitively know whether the bad blocks exist in the first logic unit and the second logic unit according to the output result of the masks, and can correctly record and store the bad block information of the aging test according to the masks, so that the bad block information of the time can be used for guiding the mask output of the next time.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a flowchart of a testing method of a memory device according to an embodiment of the present application is provided, where the method may include:
s201, bad block information of the first logic unit LUN0 and the second logic unit LUN1 is obtained.
In the embodiment of the present application, the burn-in test is a test that cycles the storage device over a period of time, and the burn-in test includes processes of data erasing, data reading, data writing, and data reading that are performed cyclically, so that the bad block information of the logic unit LUN obtained in the last burn-in test can be used to instruct the next logic unit LUN to perform the burn-in test. If the aging test is performed for the first time, each logic unit can be tested one by one to obtain bad block information of each logic unit, and the bad block information is recorded and stored, and the first stored bad block information is used for guiding the aging test for the second time. When performing the second aging test, the Program times of the two logic units can be performed simultaneously, that is, the data of the two LUNs are transmitted from the buffer to the storage area simultaneously, so as to save the test Time. Specifically, the address information of the two LUNs can be used to distinguish the two LUNs for different data transmission.
In practical application, the Bad Block information of the LUN may be stored by using a Bad Block information storage unit (BBM), and the address information of the LUN may be used to store the Bad Block information corresponding to the LUN during storage. That is, the address of LUN0 corresponds to the bad block information of LUN0, and the address of LUN1 corresponds to the bad block information of LUN 1. The BBM can simultaneously record the bad block information of a plurality of LUNs at one time.
In embodiments of the present application, the memory device may be a NAND device, for example, a planar NAND device, or a 3D NAND device. The embodiment of the present application does not particularly limit the kind of the memory device.
S202, the first logic unit LUN0 and the second logic unit LUN1 in the storage device are burn-in tested by using the same enable signal CE.
Referring to fig. 3, a schematic diagram of a method for testing a storage device according to an embodiment of the present invention may perform Program Time for two LUNs simultaneously, that is, data of two LUNs are simultaneously transferred from a buffer to a storage area. And performing aging test on the two logic units LUN by using the same enabling signal, wherein the enabling signal CE starts to be effective when the logic units perform Transfer Time. The same CE respectively drives the data of the LUN0 to be transmitted to the buffer area at different time, drives the data of the LUN1 to be transmitted to the buffer area, and then drives the data of the LUN0 and the data of the LUN1 to be transmitted to the storage area from the buffer area at the same time.
S203, according to the bad block information, the enable signal is encoded to obtain the mask of the first logic unit and the second logic unit.
In the embodiment of the present application, according to the bad block information stored in the last aging test, the enable signal of the present aging test may be encoded to obtain a Mask (Mask) corresponding to the first logic unit LUN and a Mask (Mask) corresponding to the second logic unit LUN. That is, CE can be encoded according to the LUN0 and LUN1 bad block information stored in the BBM, and different CE Mask signals are output, so as to obtain LUN0 and LUN1 bad block information according to the different CE Mask signals.
In practical applications, the Mask may be a waveform, and the level of the waveform is used to specifically display whether the first logical unit LUN0 unit or the second logical unit LUN1 has bad block information. Specifically, the output number of the Mask masks is equal to the address number of the logical unit LUN, that is, one LUN corresponds to one Mask signal.
In the embodiment of the present application, the Mask and the enable signal CE drive the first logic unit LUN0 and the second logic unit LUN1 together to work, that is, the Mask and the enable signal CE make the first logic unit LUN0 and the second logic unit LUN1 enter Transfer Time and Program Time together.
And S204, outputting the Mask.
In the embodiment of the present application, the Mask corresponding to each logical unit LUN is output at a corresponding position or Time period of each logical unit LUN, for example, a waveform corresponding to each Transfer Time corresponding to each logical unit LUN is output, and a high-low level of the waveform can reflect whether each logical unit LUN has bad block information.
In practical applications, referring to fig. 3, if a bad block exists in the first logic unit LUN0, the Mask is output at a high level in a position or Time period corresponding to the first logic unit LUN, for example, the Transfer Time of the first logic unit LUN0, and if a bad block does not exist in the first logic unit LUN0, the Mask is output at a low level in a position or Time period corresponding to the first logic unit LUN0, for example, the Transfer Time of the first logic unit LUN 0.
If the second logic unit LUN1 has a bad block, the Mask is output at a high level in a position or in a Time period corresponding to the second logic unit LUN1, for example, a Transfer Time of the second logic unit LUN1, and if the second logic unit LUN1 has no bad block, the Mask is output at a low level in a position or in a Time period corresponding to the second logic unit LUN1, for example, a Transfer Time of the second logic unit LUN 1.
The embodiment of the present application is not limited to outputting the Mask signal, and specifically, whether the low level or the high level represents the bad block information, and the setting may be set by a person skilled in the art.
The embodiment of the application provides a method for testing a memory device, which is characterized by comprising the following steps: obtaining bad block information of a first logic unit and a second logic unit; performing burn-in test on a first logic unit and a second logic unit in the memory device by using the same enable signal; according to the bad block information, coding the enabling signal to obtain a mask of the first logic unit and the second logic unit; and outputting the mask.
Therefore, the method for testing the memory device provided by the embodiment of the application can encode the enable signal by using the same enable signal and the bad block information to obtain the masks respectively corresponding to the first logic unit and the second logic unit, can intuitively know whether the bad blocks exist in the first logic unit and the second logic unit according to the output result of the masks, and can correctly record and store the bad block information of the aging test according to the masks, so that the bad block information of the time can be used for guiding the mask output of the next time.
Based on the test method of the memory device provided by the above embodiment, an embodiment of the present application further provides a test system of the memory device, including: the device comprises a mask unit, a control unit, a bad block information storage unit, a first logic unit and a second logic unit.
In an embodiment of the present application, the Mask unit is configured to provide an enable signal CE to provide the same enable signal for the first logic unit LUN0 and the second logic unit LUN1, and encode the same enable signal CE to obtain a Mask of the same enable signal. The mask unit may encode the same enable signal CE to obtain masks of the first logic unit LUN0 and the second logic unit LUN1 according to the bad block information of the first logic unit LUN0 and the second logic unit LUN1 stored in the bad block information storage unit. Each LUN has its address to distinguish, and the number of Mask outputs is equal to the number of LUN addresses.
In practical applications, the Mask unit may be a part of a hardware unit, for example, the Mask unit may be a part of a Direct Mask module. The Mask function of a plurality of LUNs can be directly realized on a hardware level, the testing time is shortened, and the testing efficiency is improved.
The bad block information storage unit BBM is configured to store the bad block information of the first logic unit LUN0 and the second logic unit LUN1 obtained in each aging test, so that the next aging test can be guided by the bad block information of the LUN0 and LUN1 obtained in the previous aging test. The bad block information storage unit BBM may store the address and the bad block information of the first logical unit, and store the address and the bad block information of the second logical unit, that is, the address of LUN0 corresponds to the bad block information of LUN0, and the address of LUN1 corresponds to the bad block information of LUN 1. The BBM can simultaneously record the bad block information of a plurality of LUNs at one time.
The control unit is used for controlling the first logic unit and the second logic unit to work according to the same enable signal and the mask, namely the control unit controls the LUN0 and the LUN1 to complete data transmission.
In the embodiment of the application, the Mask unit continuously outputs Mask signals corresponding to LUN0 and LUN1 according to the bad block information stored in the BBM, and the control unit completes data transmission of LUN0 and LUN1 in a time period of outputting the Mask signals, thereby implementing parallel operation of two LUNs.
Based on the test system for the memory device provided by the above embodiment, an embodiment of the present application further provides a test apparatus for a memory device, and the test system in any one of the above test system embodiments is adopted to test the memory device.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application are still within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.
Claims (10)
1. A method of testing a memory device, comprising:
obtaining bad block information of a first logic unit and a second logic unit, wherein the bad block information is obtained from the last aging test of the first logic unit and the second logic unit;
performing a second burn-in test on the first logic unit and the second logic unit in the memory device by using the same enable signal;
according to the bad block information, coding the enabling signal to obtain mask signals of the first logic unit and the second logic unit, wherein the mask signals carry the bad block information of the first logic unit and the second logic unit;
and outputting the mask signal.
2. The test method according to claim 1, wherein the burn-in test comprises a process of data erasing, data reading, data writing and data reading which are performed cyclically;
further comprising:
storing bad block information obtained by performing aging test on the first logic unit and the second logic unit last time;
the obtaining the bad block information of the first logic unit and the second logic unit includes:
and obtaining the bad block information of the first logic unit and the second logic unit stored in the last aging test.
3. The test method of claim 1, wherein the mask corresponds to a waveform.
4. The test method of claim 3, wherein the outputting the mask signal comprises:
if the first logic unit has a bad block, the mask signal is output at a high level at a position corresponding to the first logic unit, and if the first logic unit does not have a bad block, the mask signal is output at a low level at a position corresponding to the first logic unit;
if the second logic unit has a bad block, the mask signal is output at a high level at a position corresponding to the second logic unit, and if the second logic unit does not have a bad block, the mask signal is output at a low level at a position corresponding to the second logic unit.
5. The method of claim 1, wherein the mask signal and the enable signal jointly drive the first logic unit and the second logic unit to operate.
6. The method of claim 1, wherein the memory device is a NAND device.
7. A test system for a memory device, comprising: the device comprises a mask unit, a control unit, a bad block information storage unit, a first logic unit and a second logic unit;
the mask unit is used for providing an enable signal to provide the same enable signal for the first logic unit and the second logic unit, and coding the same enable signal to obtain a mask signal of the same enable signal;
the control unit is used for controlling the first logic unit and the second logic unit to work according to the same enable signal and the mask signal;
the bad block information storage unit is used for storing the bad block information of the first logic unit and the second logic unit obtained by the last aging test;
the mask unit is specifically configured to perform a second aging test on the first logic unit and the second logic unit by using the same enable signal, and encode the same enable signal according to the bad block information of the first logic unit and the second logic unit stored in the bad block information storage unit to obtain a mask signal of the first logic unit and the second logic unit, where the mask signal carries the bad block information of the first logic unit and the second logic unit.
8. The test system of claim 7, wherein the bad block information storage unit is specifically configured to store the address and the bad block information of the first logical unit, and store the address and the bad block information of the second logical unit.
9. The test system of claim 8, wherein the number of masks is equal to the number of addresses.
10. A test device for a memory device, characterized in that the memory device is tested with a test system according to any of claims 7-9.
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| US7103814B2 (en) * | 2002-10-25 | 2006-09-05 | International Business Machines Corporation | Testing logic and embedded memory in parallel |
| US8700961B2 (en) * | 2011-12-20 | 2014-04-15 | Sandisk Technologies Inc. | Controller and method for virtual LUN assignment for improved memory bank mapping |
| CN103149529B (en) * | 2013-03-08 | 2015-11-25 | 龙芯中科技术有限公司 | Polycaryon processor and method of testing thereof and device |
| CN112530508B (en) * | 2019-09-17 | 2023-10-20 | 北京振兴计量测试研究所 | NAND FLASH memory parallel test and bad block write-back method |
| CN110967591B (en) * | 2020-01-03 | 2021-12-31 | 中国船舶重工集团公司第七0七研究所 | Online parallel test system and test method for conductive slip ring |
| CN111833948A (en) * | 2020-07-16 | 2020-10-27 | 浪潮(北京)电子信息产业有限公司 | Method, device, equipment and medium for testing erasing and writing capability of NAND flash memory |
| CN112216338A (en) * | 2020-10-16 | 2021-01-12 | 苏州浪潮智能科技有限公司 | Method and device for analyzing bad blocks generated by solid state disk aging |
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