CN109859788B

CN109859788B - Method for testing bit error rate of resistive memory

Info

Publication number: CN109859788B
Application number: CN201910134609.0A
Authority: CN
Inventors: 赵毅; 高世凡; 陈冰
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2019-02-23
Filing date: 2019-02-23
Publication date: 2021-04-16
Anticipated expiration: 2039-02-23
Also published as: CN109859788A

Abstract

The invention discloses a method for testing the bit error rate of a resistive memory. It is significant to speed up the process since the commercial use of memory is required to ensure extremely low bit error rates, and this test requires a large number of iterations and analyses, and thus a large amount of time. The invention utilizes an arbitrary waveform generator to adjust the length of the read waveform to be a specific value, thereby generating a specific waveform only containing read information after dot product of the selected signal and the read waveform in an oscilloscope. The specific waveform allows the waveforms except the read information to be filtered after the sampling rate of the oscilloscope is adjusted, so that the redundancy of the information is reduced to the theoretical minimum value, and the flux of the bit error rate test is increased.

Description

Method for testing bit error rate of resistive memory

Technical Field

The present invention generally belongs to the field of memory testing, and more particularly, to reliability testing of resistive memories.

Background

Resistive memory based on resistance value is a common non-volatile memory, which is a technology capable of recording data for a long time under a passive condition. There are two basic operations for resistive memory, erase and read. Due to the randomness caused by the thermodynamics and self mechanism of the device, the erasing operation and the reading operation can cause a certain bit error rate. For the erasure process, the error code appears as a write failure, i.e., the state of the memory cell does not change before and after erasure. For the reading process, the error code shows that the writing is successful, i.e. the state of the memory cell changes before and after the reading. For a commercial resistive memory, a bit Error rate below a certain threshold is acceptable due to the use of Error Correction codes (Error Correction codes). This bit error rate threshold is recognized to be 10^-6I.e., one bit error per million operations. Bit error rate testing is a critical reliability datum for any memory commercialization, but this requirement implies an extremely large data volume and correspondingly extremely long test times. It is therefore very interesting to reduce the time of this critical test considerably. Conventional bit error rate analysis uses a fixed read time duration that is consistent with the timing in the actual circuit, usually a much smaller value than the length of the write sequence elements. Therefore, the oscilloscope must operate at a higher sampling rate to capture the read stepThe current on the device is segmented, and the state of the device is obtained. This high sampling rate directly increases the amount of data that would otherwise be high even further.

Disclosure of Invention

The invention aims to provide a method for testing the bit error rate of a resistive memory, aiming at the defects of the prior art.

The purpose of the invention is realized by the following technical scheme: a method for testing bit error rate of a resistive memory, the method comprising:

in a test system;

the output of the arbitrary waveform generator of the test system is two signals, namely a write signal and a selection signal;

the input of the oscilloscope of the test system is two signals, namely the excitation current of the memory signal through the resistive memory and the selection signal;

the data of the mathematical channel of the oscilloscope is the dot product result of the excitation current and the selected signal;

and receiving the dot product result in the computer, and analyzing the error rate to obtain the error rate.

Further, the test system is based on a probe station, a wafer, and a passive probe, and does not use a separate active amplifier or passive amplifier.

Furthermore, the storing and writing sequence unit of the storing and writing signal is divided into an initialization stage, a writing stage, a waiting stage and a reading stage;

the bit error rate is targeted at the write phase, and the voltage amplitude of the write phase may be an erase voltage amplitude, or a read voltage amplitude, or may be an arbitrary waveform.

Further, the time length of the read phase is approximately half of the length of the write sequence.

Further, the selection sequence unit of the selection signal is divided into a high level stage and a low level stage.

Further, the time positions of the high phase are a subset of the time positions of the read phase.

Further, the calculation operation for obtaining the dot product result is completed in a high-speed mathematical operation unit inside the oscilloscope.

Further, the sampling rate of the oscilloscope is not more than 50 times of the reciprocal of twice of the reading stage of the memory write signal; and if the sampling is positioned at the time position of the reading stage, the next sampling cannot enter the time position of the reading stage of the next storing and writing sequence unit.

Further, bit error rate analysis in the computer uses a parallel computing architecture.

Further, the bit error rate analysis uses a classifier algorithm.

The invention has the beneficial effects that: the method can realize high-flux error rate test, thereby greatly shortening the time required by the error rate test and promoting the speed of product research and development. The method effectively shields the data outside the reading stage, thereby reducing the data amount required to be processed for acquiring the error code information of single operation to the theoretical minimum, and greatly reducing the time and cost for storing and processing the data. Firstly, the invention uses the dot product of the selection signal and the storage signal, and simplifies the original complex waveform into a signal which is similar to a square wave and has unchanged reading stage and approximately zero other time positions. Because the processing is completed through the high-speed bus and the computing unit in the oscilloscope, time-consuming peripheral data transmission between devices is not needed, and therefore, a signal which is easier to process is obtained on the premise of not increasing the test time, and a foundation is laid for the next processing.

Drawings

Fig. 1 is a schematic diagram of an implementation of a method for testing the bit error rate of a resistive memory.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described in connection with one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention include such modifications and variations. Specific language (which should not be construed as limiting the scope of the appended claims) is used to describe the embodiments. The drawings are not to scale and are for illustration purposes only.

We represent the waveform using the following notation:

(time 1, amplitude 1) is defined as maintaining amplitude 1 (unit: V) for the length of time 1 (unit: ns);

[ A, B ] is fixed in the series connection of two waveforms in time sequence.

The test system comprises an arbitrary waveform generator, an oscilloscope and a computer. During testing, the resistive memory to be tested is a spin transfer torque-magnetic random access memory (STT-MRAM).

Assuming that a 50ns square wave writing error rate of 0.5V is required, the specific steps are as follows:

the sampling rate of the oscilloscope is set to 5 MS/s. The stored waveform of the arbitrary waveform generator is input into the device, and the channel 1 of the oscilloscope is connected to the device loop. The selected waveform from the arbitrary waveform generator is input into channel 2 of the oscilloscope. In the oscilloscope, the mathematical operation result is set as the dot product of the channel 1 and the channel 2, and is recorded as math 1. Save math 1 to the oscilloscope. And arranging a probe station and a probe to complete the pricking of the microwave probe and the magnetic random access memory wafer.

After completing the connection of the test loop, the write waveform is set to

[(400,-0.7),(100,0),(50,0.5),(100,0),(850,0.2)],

Setting the selected waveform to

[(700,0),(750,0.5),(50,0)]。

The next step is to access the hard disk of the oscilloscope using the gigabit lan based network to read this data. On a computer, the error rate can be handled in many ways, and two examples are given here. In the first way, the resistance-voltage relationship of the device is measured in advance, the boundary between the resistances in different states is determined, and then the high level of the square wave in the test data is compared with the predetermined boundary. In the second mode, a part of data is randomly extracted, a classifier algorithm is used for determining the boundary limit of resistors in different states, and then a trained classifier is used for judging the state of the device. The computation of this step can be accelerated using a parallel computing architecture. While data is being saved, low precision floating point numbers or integer shapes may be used to reduce the amount of data.

Through the process, the error rate of voltage measurement can be fixed, and the expected error rate can also be fixed so as to search the corresponding voltage. The former process can be realized only by continuously changing the written voltage. For the latter process, newton's method or dichotomy is used to accomplish this search, see left side of fig. 1. First, a specific implementation of the newton method will be described. A smaller write voltage, e.g., 0.1V, is set and a larger write voltage, e.g., 0.2V, is set. And performing linear extrapolation or interpolation according to the Newton method to obtain a new writing voltage, and circulating until the difference value between the actually-measured error rate and the expected error rate is smaller than a given error value. Next, a specific implementation of the dichotomy is described. Setting a smaller write voltage, such as 0.1V, and if the measured error rate is greater than the expected error rate, setting the new voltage to be twice of the original voltage until the measured error rate is less than the expected error rate. The last two times are taken as search intervals for binary search, and since this step is a basic algorithm, it is not explained in detail here.

Claims

1. A method for testing the bit error rate of a resistive memory is characterized by comprising the following steps:

in a test system;

the dot product result simplifies the original complex waveform into a signal which is unchanged in the reading stage and is similar to a square wave with the rest time position being approximately zero;

2. The method of claim 1, wherein the test system is based on a probe station, a wafer, and a passive probe, and does not use a separate active amplifier or passive amplifier.

3. The method of claim 1, wherein the unit of the memory-write sequence of the memory-write signal is divided into an initialization phase, a write phase, a wait phase, and a read phase;

4. The method of claim 3, wherein the length of time of the read phase is approximately half the length of the write sequence.

5. The method of claim 3, wherein the selected sequence of units of the selected signal is divided into a high phase and a low phase.

6. The method of claim 5, wherein the time positions of the high phase are a subset of the time positions of the read phase.

7. The method of claim 1, wherein the computing operation to obtain the dot product result is performed in a high speed mathematical operation unit internal to the oscilloscope.

8. A method as claimed in claim 3, wherein the sampling rate of the oscilloscope is no greater than 50 times the inverse of twice the read phase of the write signal; and if the sampling is positioned at the time position of the reading stage, the next sampling cannot enter the time position of the reading stage of the next storing and writing sequence unit.

9. The method of claim 1, wherein the bit error rate analysis in the computer uses a parallel computing architecture.

10. The method of claim 1, wherein the bit error rate analysis uses a classifier algorithm.