CN111223518B - Test structure and durability test method for resistive memory unit - Google Patents
Test structure and durability test method for resistive memory unit Download PDFInfo
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- CN111223518B CN111223518B CN201811424807.2A CN201811424807A CN111223518B CN 111223518 B CN111223518 B CN 111223518B CN 201811424807 A CN201811424807 A CN 201811424807A CN 111223518 B CN111223518 B CN 111223518B
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Abstract
The invention provides a test structure and a durability test method for a resistive memory unit. The test structure includes: the resistive memory unit to be tested is connected with a controllable switch device respectively, a first connecting end of each resistive memory unit to be tested is connected to one point and is connected to a first test electrode together, a second connecting end of each resistive memory unit to be tested is connected to a first connecting end of the corresponding controllable switch device respectively, a second connecting end of each controllable switch device is connected to one point and is connected to a second test electrode together, a control end of each controllable switch device is connected to a control signal electrode of each controllable switch device respectively, the first test electrode and the second test electrode are used for inputting read-write signals, and each control signal electrode is used for inputting control signals of the controllable switch devices. The invention can save the area of the layout, improve the testing efficiency and save the testing time.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a test structure and a durability test method for a resistive memory unit.
Background
In recent years, magnetic random access memory MRAM has been rapidly developed due to its excellent characteristics. MRAM, as a read/write memory device, has a high requirement for the number of read/write operations, so the Endurance test (Endurance test) is very important. In the research and development stage, in order to obtain the endurance test distribution condition of the device, the reliability of the product in the mass production stage is ensured, and more test samples are selected. Based on the reliability test sample selection theory, in order to guarantee the reliability, the number of samples is at least hundreds.
At present, for the durability test of multiple samples, the samples are generally tested one by one, and then reliability analysis is carried out on test data. Since two test pads need to be introduced for one sample, the conventional test structure occupies a large layout area. In addition, if the endurance test of one sample reaches 10^10 times, the test time is 3h, so the time spent by the conventional multi-sample endurance test is very long.
Disclosure of Invention
In order to solve the above problems, the present invention provides a test structure and a durability test method for a resistive memory cell, which can save layout area, improve test efficiency, and save test time.
In a first aspect, the present invention provides a test structure for a resistive memory cell, comprising: the resistive memory unit to be tested is connected with a controllable switch device respectively, a first connecting end of each resistive memory unit to be tested is connected to one point and is connected to a first test electrode together, a second connecting end of each resistive memory unit to be tested is connected to a first connecting end of the corresponding controllable switch device respectively, a second connecting end of each controllable switch device is connected to one point and is connected to a second test electrode together, a control end of each controllable switch device is connected to a control signal electrode of each controllable switch device respectively, the first test electrode and the second test electrode are used for inputting read-write signals, and each control signal electrode is used for inputting control signals of the controllable switch devices.
Optionally, the first test electrode and the second test electrode adopt a GS electrode structure, or the test structure further includes a third test electrode, and the third test electrode, the first test electrode and the second test electrode together form a GSG electrode structure, the second test electrode and the third test electrode are grounded, and the first test electrode inputs a pulse signal.
Optionally, the controllable switching devices are voltage-controlled switching devices, and the controllable switching devices connected to different resistive memory cells to be tested have the same or opposite switching characteristics.
Optionally, the controllable switching device is an N/PMOS transistor, a BJT, or an IGBT.
Optionally, the number of the resistive memory cells to be tested is even, and every two resistive memory cells to be tested are in one group, and the controllable switching devices connected to the two resistive memory cells to be tested in each group have opposite switching characteristics.
Optionally, the resistive memory cell is a magnetic tunnel junction MTJ.
In a second aspect, the present invention provides a durability test method based on the test structure, including:
1) sequentially applying voltage to each control signal electrode, measuring the resistance value of each resistive memory cell to be tested in the test structure, and marking the resistive memory cells to be tested with normal resistance values to obtain a sample sequence;
2) simultaneously applying voltage to control signal electrodes corresponding to the sample sequence, and measuring initial parallel resistance values of all resistive memory cells to be tested of the sample sequence;
3) keeping the application of voltage to the control signal electrodes corresponding to the sample sequence, and repeatedly executing the following processes: applying a specific excitation signal between a first test electrode and a second test electrode, measuring the parallel resistance values of all resistive memory units to be tested of a sample sequence until the difference value between the obtained parallel resistance value and the initial parallel resistance value is greater than a set threshold value, and recording the application times of the excitation signal;
4) sequentially applying voltage to the control signal electrodes corresponding to the sample sequence, measuring the resistance value of each resistive memory unit to be tested in the sample sequence, marking the resistive memory unit to be tested with normal resistance value to obtain a new sample sequence, and recording the durability test data of the resistive memory unit to be tested with abnormal resistance value as the application times of the excitation signal in the step 3);
5) and continuing to test the new sample sequence according to the steps 2) -4), and repeatedly executing the process until the new sample sequence is empty, or the application frequency of the excitation signal reaches a set upper limit value, and when the application frequency of the excitation signal reaches the set upper limit value, setting the endurance test data of the resistive memory unit to be tested with the normal resistance value to be larger than the upper limit value.
Optionally, the set threshold is 10 ohms.
The test structure for testing the durability of the resistive memory unit only needs to provide one control signal electrode and one group of read-write signal input electrodes for the controllable switch device connected with each resistive memory unit to be tested, when a test sample is K, the number of the needed test electrodes PAD in the test structure is only K +2, and the number of the needed test electrodes PAD in the existing test structure is 2K (the number of samples K in actual test is far more than 2), so that the test structure can save a large amount of layout area. In addition, according to the durability test method, the resistive memory unit to be tested and the switch device are combined to gate the device to be tested and the test signal, so that durability test can be performed on a plurality of devices simultaneously, the test efficiency is improved, and the test time is saved.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a test structure for a resistive memory cell of the present invention;
FIG. 2 is a schematic diagram of another embodiment of a test structure for a resistive memory cell of the present invention;
FIG. 3 is a schematic diagram of the external connection relationship of the test structure shown in FIG. 1;
FIG. 4 is a diagram showing the test results of an actual endurance test using the test structure of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a test structure for a resistive memory cell, including: the resistive memory unit to be tested is connected with a controllable switch device respectively, a first connecting end of each resistive memory unit to be tested is connected to one point and is connected to a first test electrode together, a second connecting end of each resistive memory unit to be tested is connected to a first connecting end of the corresponding controllable switch device respectively, a second connecting end of each controllable switch device is connected to one point and is connected to a second test electrode together, a control end of each controllable switch device is connected to a control signal electrode of each controllable switch device respectively, the first test electrode and the second test electrode are used for inputting read-write signals, and each control signal electrode is used for inputting control signals of the controllable switch devices.
Further, the controllable switch device uses a voltage controlled switch device, such as an N/PMOS transistor, BJT, IGBT, etc. It is further emphasized that the controllable switching devices connected to different resistive memory cells to be tested can be used in any combination theoretically, i.e. different types of controllable switching devices can be used, and the controllable switching devices connected to different resistive memory cells to be tested can also have the same or opposite switching characteristics.
The test structure for the resistive memory unit only needs to provide a control signal electrode and a group of read-write signal input electrodes for the switch device connected with each resistive memory unit to be tested, when a test sample is K, the number of the test electrodes PAD required in the test structure is only K +2, and the number of the test electrodes PAD required in the existing test structure is 2K (the number of samples K in actual test is far more than 2), so that a large amount of layout area can be saved.
FIG. 1 illustrates one embodiment of a test structure for a resistive memory cell of the present invention. The method comprises the following steps of testing Magnetic Tunnel Junction (MTJ) (other types of resistive memory cells such as SRAM cells can also be adopted), wherein the number of test samples is K, all controllable switching devices use NMOS tubes, one-to-one corresponding NMOS tube is designed in a lower layer circuit corresponding to each MTJ, each MTJ is connected with one NMOS tube respectively, a first connecting end of each MTJ is connected to one point through a metal wire and connected to a first test electrode PadB together, a second connecting end of each MTJ is connected with the drain electrode of each NMOS tube, the source electrodes of all the NMOS tubes are connected to one point and connected to a second test electrode PadA together, and the grid electrode of each NMOS tube is connected to a respective control signal electrode Pad1-PadK respectively; the first test electrode PadB and the second test electrode PadA are used for inputting read-write signals, and the control signal electrodes Pad1-PadK are used for inputting control signals of the controllable switching device.
It should be noted that the arrangement order of the test electrodes (PadA, PadB, Pad1-PadK) is arbitrary, fig. 1 is only an example, for example, in a general design, pads connected to the gates of MOS transistors may be inserted between PadA and PadB, and the arrangement order of pads connected to the gates of MOS transistors may be staggered.
The test structure of fig. 1, PadA, PadB are common PAD structures, which are suitable for DC testing, and if high frequency testing is to be performed, the first test electrode PadB and the second test electrode PadA need to be designed as GS (Ground-Signal) electrode structures. Alternatively, as shown in fig. 2, if a high frequency test is to be performed, a third test electrode PadC may be added to form a GSG (Ground-Signal-Ground) electrode structure together with PadA and Pad B, PadA and PadC are grounded, Pad B inputs a pulse Signal, and a Pad structure with 50 ohm impedance matching is obtained by Pad size and pitch design, and the structure is suitable for the high frequency test.
In the test structures of fig. 1 and 2, the controllable switching devices connected to the resistive memory cells to be tested have the same switching characteristics. But not limited to, the controllable switching devices connected to the resistive memory cells under test in the test structure may have different switching characteristics. For example, when the number of the test samples is an even number, every two MTJs form a group, and the two MTJs in each group are respectively connected with an NMOS tube and a PMOS tube.
Further, when the durability test is performed based on the test structure of fig. 1, the external connection relationship is as shown in fig. 3, Pad a and Pad B are respectively connected with two input ends of the pulse generator through corresponding probes; pad1 to Pad k are connected to the output end of the switch matrix through the probe, the input end of the switch matrix is connected with a voltage applying device (such as an SMU or a voltage source), and the switch of each NMOS tube can be controlled independently.
A method of performing a durability test using the test structure of fig. 3, comprising the steps of:
1. after the test structures are connected, sequentially applying voltage to each control signal electrode Pad1-PadK to enable the corresponding NMOS tube to be conducted, reading the resistance value between the first test electrode Pad B and the second test electrode Pad A, namely measuring the resistance value of each MTJ in the test structure, judging whether the MTJ is normal or not, marking the MTJ with normal resistance value to obtain an MTJ sequence;
2. simultaneously applying voltage to control signal electrodes connected with the grid electrodes of the NMOS tubes corresponding to the MTJ sequence to enable the corresponding NMOS tubes to be completely conducted, and reading the resistance value between the first test electrode Pad B and the second test electrode Pad A, namely measuring the initial parallel resistance values of all the MTJs in the MTJ sequence;
3. keeping a control signal electrode connected with a grid electrode of an NMOS tube corresponding to the MTJ sequence and applying voltage simultaneously to ensure that the corresponding NMOS tube is completely conducted, applying a pulse sequence with specific pulse width and amplitude between a first test electrode PadB and a second test electrode PadA, and applying the pulse sequence for 1 time or repeating for multiple times; then measuring the parallel resistance values of all the MTJs in the MTJ sequence, and judging whether the change value of the parallel resistance values is greater than a certain threshold value R _ jump or not; repeatedly executing the process until the change value of the parallel resistance is greater than a certain threshold value R _ jump, and recording the corresponding pulse application times as n;
4. canceling voltage applied to a control signal electrode connected with a grid electrode of an NMOS tube corresponding to the MTJ sequence, sequentially applying voltage to the control signal electrode connected with the grid electrode of the NMOS tube corresponding to the MTJ sequence to enable the corresponding NMOS tube to be conducted, measuring resistance values corresponding to all the MTJs, judging whether the MTJs are normal or not, marking the MTJs with normal resistance values to obtain a new MTJ sequence, and recording durability test data of failed MTJs as pulse applying times n in the step 3 for failed MTJs;
5. and repeating the steps 2-4 until the new sample sequence is empty, namely all the MTJs fail, or the number of applied pulses reaches a set upper limit value, and when the number of applied pulses reaches the set upper limit value, the endurance test data of the MTJs with normal resistance is set to be larger than the upper limit value.
By the testing method, the resistive memory unit to be tested and the switch device are combined to gate the device to be tested and the testing signal, so that durability testing can be performed on a plurality of devices simultaneously, testing efficiency is improved, and testing time is saved. As shown in fig. 4, taking the practical result of the parallel test of 19 MTJ devices as an example, the duration test value of a set of MTJs can be obtained. Resistance monitoring corresponds to a device pulse application number of 1.3.5.10.30.50.70.100.300.500 …, with 1 or more MTJ breakdowns (threshold voltage 10 ohms) per jump in resistance reduction in fig. 4 (a). One test can obtain the 19 MTJ entity statistics shown in fig. 4 (b).
In addition, if the test structure has both NMOS and PMOS transistors, the test method is similar to the aforementioned method and is not described again. Note that, when the state of each MTJ is detected separately, and when the state of an MTJ to which an NMOS transistor is connected is detected, the gates of the remaining other NMOS transistors are connected to a low potential, and the gates of the remaining other PMOS transistors are connected to a high potential, so that the remaining other MOS transistors are in an off state. When the resistance value of one MTJ is detected independently, the MOS tube connected with the MTJ is turned on, and other MOS tubes are turned off.
Next, the feasibility of the above test method is additionally described.
Resistance value R of MTJpGenerally above 4k omega, and the resistance R of the device after failuredownTypically less than 1k omega. With Rp＝4kΩ,RdownThe calculation is performed as 1k Ω.
If the test sample is 20 and all 20 MTJ detections are normal devices in the initial state, starting the parallel resistor
Assuming cyclic testing, there is an MTJ failure after applying N pulses, the failure criteria are:
the corresponding resistance jump value is 20 Ω, and further, if more MTJs fail at the same time, the corresponding resistance jump value is larger. Therefore, the failure process can be accurately detected by setting the threshold value R _ jump in the test step to 10 Ω.
In subsequent testing, the initial shunt resistance after removal of a failed device
Continuing the cycle test, and after applying M pulses, having an MTJ failure again, the failure criteria are:
the corresponding resistance jump value is 22.5 Ω, and further, if there are multiple MTJs failing at the same time, the resistance jump value is larger. Therefore, it is fully feasible to set the threshold value R _ jump in the test step to 10 Ω.
And as the number of times of the cycle test is increased, the subsequent test detection window is larger and larger after the failure device is excluded from the parallel circuit. The invention detects 10 omega grade change on the resistance value with 100 omega grade corresponding to the minimum detection window, and has high reliability.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A test structure for resistive memory units is characterized by comprising a plurality of resistive memory units to be tested, wherein each resistive memory unit to be tested is connected with a controllable switch device, the first connection end of each resistive memory unit to be tested is connected with a point and is commonly connected with a first test electrode, the second connection end of each resistive memory unit to be tested is connected with the first connection end of the corresponding controllable switch device, the second connection end of each controllable switch device is connected with a point and is commonly connected with a second test electrode, and the control end of each controllable switch device is respectively connected with a control signal electrode, wherein the first test electrode and the second test electrode are used for inputting read-write signals, and each control signal electrode is used for inputting control signals of the controllable switch devices.
2. The test structure of claim 1, wherein the first test electrode and the second test electrode are in a GS electrode structure, or further comprising a third test electrode, which forms a GSG electrode structure together with the first test electrode and the second test electrode, wherein the second test electrode and the third test electrode are grounded, and wherein the first test electrode inputs a pulse signal.
3. The test structure of claim 1, wherein the controllable switching devices are voltage controlled switching devices, and the controllable switching devices connected to different resistive memory cells under test have the same or opposite switching characteristics.
4. The test structure according to claim 3, wherein the controllable switching device is an N/PMOS transistor, a BJT, or an IGBT.
5. The test structure of claim 3, wherein the plurality of resistive memory cells under test is an even number, and each two of the plurality of resistive memory cells under test are in a group, and the controllable switching devices to which the two resistive memory cells under test in each group are connected have opposite switching characteristics.
6. The test structure of claim 1, wherein the resistive memory cell is a Magnetic Tunnel Junction (MTJ).
7. A method for endurance testing based on the test structure for a resistive memory cell of claim 1, comprising:
1) sequentially applying voltage to each control signal electrode, measuring the resistance value of each resistive memory cell to be tested in the test structure, and marking the resistive memory cells to be tested with normal resistance values to obtain a sample sequence;
2) simultaneously applying voltage to control signal electrodes corresponding to the sample sequence, and measuring initial parallel resistance values of all resistive memory cells to be tested of the sample sequence;
3) keeping the application of voltage to the control signal electrodes corresponding to the sample sequence, and repeatedly executing the following processes: applying a specific excitation signal between a first test electrode and a second test electrode, measuring the parallel resistance values of all resistive memory units to be tested of a sample sequence until the difference value between the obtained parallel resistance value and the initial parallel resistance value is greater than a set threshold value, and recording the application times of the excitation signal;
4) sequentially applying voltage to the control signal electrodes corresponding to the sample sequence, measuring the resistance value of each resistive memory unit to be tested in the sample sequence, marking the resistive memory unit to be tested with normal resistance value to obtain a new sample sequence, and recording the durability test data of the resistive memory unit to be tested with abnormal resistance value as the application times of the excitation signal in the step 3);
5) and continuing to test the new sample sequence according to the steps 2) -4), and repeatedly executing the process until the new sample sequence is empty, or the application frequency of the excitation signal reaches a set upper limit value, and when the application frequency of the excitation signal reaches the set upper limit value, setting the endurance test data of the resistive memory unit to be tested with the normal resistance value to be larger than the upper limit value.
8. The method of claim 7, wherein the set threshold is 10 ohms.
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| PCT/CN2019/119607 WO2020108359A1 (en) | 2018-11-27 | 2019-11-20 | Test structure for resistive storage unit, and endurance test method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102243895A (en) * | 2011-04-22 | 2011-11-16 | 杭州电子科技大学 | Method for measuring service life of unipolar resistor type memory |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| US8363449B2 (en) * | 2008-11-17 | 2013-01-29 | Seagate Technology Llc | Floating source line architecture for non-volatile memory |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
| US9653182B1 (en) * | 2016-03-01 | 2017-05-16 | Kabushiki Kaisha Toshiba | Testing method, manufacturing method, and testing device of memory device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6584589B1 (en) * | 2000-02-04 | 2003-06-24 | Hewlett-Packard Development Company, L.P. | Self-testing of magneto-resistive memory arrays |
| KR101321481B1 (en) * | 2011-11-04 | 2013-10-28 | 에스케이하이닉스 주식회사 | Semiconductor Memory Apparatus and Test Circuit Therefor |
| TWI502596B (en) * | 2012-08-15 | 2015-10-01 | Wistron Corp | Memory testing method, memory testing apparatus, and adapter thereof |
| CN103811058B (en) * | 2014-01-28 | 2016-09-07 | 华中科技大学 | Nonvolatile memory based on memristor, read-write erasing operational approach and test circuit |
| US9472247B2 (en) * | 2015-02-13 | 2016-10-18 | Taiwan Semiconductor Manufacturing Company Limited | Memory, semiconductor device including the same, and method for testing the same |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8363449B2 (en) * | 2008-11-17 | 2013-01-29 | Seagate Technology Llc | Floating source line architecture for non-volatile memory |
| CN102243895A (en) * | 2011-04-22 | 2011-11-16 | 杭州电子科技大学 | Method for measuring service life of unipolar resistor type memory |
| CN102354537A (en) * | 2011-07-06 | 2012-02-15 | 华中科技大学 | Method and system for testing chip of phase change memory |
| CN105336378A (en) * | 2014-07-03 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory unit test structure and method and phase change memory |
| US9653182B1 (en) * | 2016-03-01 | 2017-05-16 | Kabushiki Kaisha Toshiba | Testing method, manufacturing method, and testing device of memory device |
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