WO2020108359A1

WO2020108359A1 - Test structure for resistive storage unit, and endurance test method

Info

Publication number: WO2020108359A1
Application number: PCT/CN2019/119607
Authority: WO
Inventors: 何世坤; 杨晓蕾; 竹敏; 任云翔
Original assignee: 浙江驰拓科技有限公司
Priority date: 2018-11-27
Filing date: 2019-11-20
Publication date: 2020-06-04
Also published as: CN111223518B; CN111223518A

Abstract

Disclosed are a test structure for a resistive storage unit, and an endurance test method. The test structure comprises: a plurality of resistive storage units to be tested, wherein each resistive storage unit to be tested is connected to a controllable switch device, first connection ends of the resistive storage units to be tested are connected to one point and are jointly connected to a first test electrode, a second connection end of each resistive storage unit to be tested is connected to the first connection end of the corresponding controllable switch device, second connection ends of the controllable switch devices are connected to one point and are jointly connected to a second test electrode, control ends of the controllable switch devices are connected to respective control signal electrodes, the first test electrode and the second test electrode are used for inputting read/write signals, and the control signal electrodes are used for inputting control signals of the controllable switch devices. The structure and method can save on a layout area, improve testing efficiency and save on testing time.

Description

Test structure and durability test method for resistive memory cell

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a test structure and durability test method for resistive memory cells.

Background technique

In recent years, magnetic random access memory (Magnetic Random Access Memory, MRAM for short) has achieved rapid development due to its excellent characteristics. As a readable and writable memory device, MRAM has high requirements for the number of reads and writes, so its endurance test is particularly important. In order to obtain the endurance test distribution of the device in the research and development stage, and to ensure the reliability of the product in the mass production stage, there will be more test samples. Based on the theory of reliability test sample selection, in order to ensure credibility, the number of samples is at least hundreds.

At present, for the durability test of multiple samples, we generally test the samples one by one, and then perform reliability analysis on the test data. And one sample needs to introduce two test pads, so the existing test structure will occupy a larger layout area. In addition, if the durability test of one sample reaches 10^10 times, the test time is 3h, so the time taken by the existing multi-sample durability test will be very long.

Summary of the invention

To solve the above problems, the present invention provides a test structure and a durability test method for resistive memory cells, which can save layout area, improve test efficiency, and save test time.

In a first aspect, the present invention provides a test structure for a resistive memory cell, including: a plurality of resistive memory cells to be tested, each resistive memory cell to be tested is respectively connected with a controllable switching device, and each The first connection terminal of the resistive memory cell is connected at one point and is commonly connected to the first test electrode, and the second connection terminal of each resistive memory cell to be tested is respectively connected to the first connection terminal of the corresponding controllable switching device, The second connection terminal of each controllable switching device is connected at one point and is commonly connected to the second test electrode, and the control terminal of each controllable switching device is connected to the respective control signal electrode, wherein the first test electrode and the second The test electrode is used to input the read-write signal, and each control signal electrode is used to input the control signal of the controllable switching device.

Optionally, the first test electrode and the second test electrode adopt a GSG structure or a GS structure.

Optionally, the controllable switching device is a voltage-controlled switching device, and the controllable switching devices connected to different resistive memory cells to be tested have the same or opposite switching characteristics.

Optionally, the controllable switching device is an N/PMOS tube, BJT or IGBT.

Optionally, the plurality of resistive memory cells to be tested is an even number, and each two is a group, and the controllable switching devices connected to the two resistive memory cells to be tested in each group have opposite switching characteristics .

Optionally, the resistive memory unit is a magnetic tunnel junction MTJ.

In a second aspect, the present invention provides a durability test method based on the above test structure, including:

1) Apply voltage to each control signal electrode in sequence, measure the resistance of each resistive memory cell to be tested in the test structure, and mark the resistive memory cell to be tested with normal resistance to obtain a sample sequence;

2) Simultaneously apply voltage to the control signal electrodes corresponding to the sample sequence, and measure the initial parallel resistance of all the resistive memory cells to be tested in the sample sequence;

3) Keep applying voltage to the control signal electrodes corresponding to the sample sequence, and repeat the following process: apply a specific excitation signal between the first test electrode and the second test electrode, and measure the parallel resistance of all the resistive memory cells to be tested in the sample sequence Value until the difference between the obtained parallel resistance and the initial parallel resistance is greater than the set threshold, and record the number of times the excitation signal is applied;

4) Apply voltage to the control signal electrodes corresponding to the sample sequence in sequence, measure the resistance of each resistive memory cell to be tested in the sample sequence, mark the resistive memory cell to be tested with normal resistance, and obtain a new sample sequence, and Record the endurance test data of the resistive memory cell to be tested with abnormal resistance value as the number of excitation signal application in step 3);

5) Follow steps 2)-4) to continue testing the new sample sequence, and repeat the process until the new sample sequence is empty, or the number of times the excitation signal is applied reaches the set upper limit, when the number of times the excitation signal is applied When the set upper limit value is reached, the durability test data of the resistive memory cell to be tested with a normal resistance value is set to be greater than the upper limit value.

Optionally, the set threshold is 10 ohms.

The test structure for durability testing of resistive memory cells provided by the present invention only needs to provide a control signal electrode and a set of read-write signal input electrodes for each controllable switching device connected to the resistive memory cell to be tested. When the test sample is K, the number of test electrode PADs required in the test structure of the present invention is only K+2, while the number of test electrode PADs required in the existing test structure is 2K (the number of samples in actual tests is much greater than 2) Therefore, the present invention can save a lot of layout area. In addition, in the durability test method of the present invention, the combination of the resistive memory cell to be tested and the switching device can be used to select the device to be tested and the test signal, and then the durability test can be performed on multiple devices at the same time, improving the test efficiency and saving the test time.

BRIEF DESCRIPTION

1 is a schematic structural diagram of an embodiment of a test structure for resistive memory cells of the present invention;

2 is a schematic structural view of another embodiment of a test structure for resistive memory cells of the present invention;

3 is a schematic diagram of the external connection relationship of the test structure shown in FIG. 1;

FIG. 4 is a schematic diagram of a test result of actual durability testing using the test structure of the present invention.

detailed description

To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only a part of the embodiments of the present invention, but not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

An embodiment of the present invention provides a test structure for a resistive memory cell, which includes: a plurality of resistive memory cells to be tested, each of the resistive memory cells to be tested is respectively connected with a controllable switching device, and each resistive to be tested The first connection terminal of the performance memory cell is connected at one point, and is commonly connected to the first test electrode, and the second connection terminal of each resistance memory cell to be tested is respectively connected to the first connection terminal of the corresponding controllable switching device, each The second connection terminal of the controllable switching device is connected at one point, and is commonly connected to the second test electrode, and the control terminal of each controllable switching device is respectively connected to the respective control signal electrode, wherein the first test electrode and the second test electrode It is used to input read and write signals, and each control signal electrode is used to input control signals of controllable switching devices.

Further, the controllable switching devices use voltage-controlled switching devices, such as N/PMOS transistors, BJT, IGBT, etc. In addition, it is emphasized that the controllable switching devices connected to different resistive memory cells to be tested can theoretically be arbitrarily mixed, that is, different types of controllable switching devices can be used, and the controllable switching devices connected to different resistive memory cells to be tested It may also have the same or opposite switching characteristics.

The test structure for resistive memory cells provided by the present invention only needs to provide a control signal electrode and a set of read-write signal input electrodes for each switching device connected to the resistive memory cell to be tested. When the test sample is K At this time, the number of test electrode PAD required in the test structure of the present invention is only K+2, while the number of test electrode PAD required in the existing test structure is 2K (the actual number of samples K in the actual test is much greater than 2), therefore, the present invention Can save a lot of layout area.

As shown in FIG. 1, it is an embodiment of the test structure for resistive memory cells of the present invention. Test the magnetic tunnel junction MTJ (you can also use other types of resistive memory cells, such as SRAM cells). The number of test samples is K. The controllable switching devices all use NMOS tubes. Design one in the lower layer circuit corresponding to each MTJ. A corresponding NMOS tube, each MTJ is respectively connected to an NMOS tube, the first connection terminal of the MTJ is connected to a point through a metal wire, and is commonly connected to the first test electrode PadB, the second connection terminal of the MTJ is connected to the drain of the NMOS tube , The sources of all NMOS tubes are connected to one point, and are connected to the second test electrode PadA, the gate of each NMOS tube is connected to the respective control signal electrode Pad1-PadK; wherein, the first test electrode PadB and the second test The electrode PadA is used to input read-write signals, and each control signal electrode Pad1-PadK is used to input control signals of controllable switching devices.

It should be noted that the arrangement order of each test electrode (PadA, PadB, Pad1-PadK) is arbitrary, and FIG. 1 is just an example. For example, in a general design, PadA and PadB can also be inserted and connected to the MOS grid The pad order of the pads connected to the grid of the MOS transistor can also be staggered.

The test structure in Fig. 1, PadA and PadB are ordinary PAD structures. This test structure is suitable for DC testing. If high frequency testing is required, the first test electrode PadB and the second test electrode PadA need to be designed as GSG (Ground-Signal- Ground) or GS (Ground-Signal) structure. As shown in Figure 2, add PadC, PadA and PadC to ground, and Pad B input pulse signal, through the PAD size and spacing design to get a 50 ohm impedance matching PAD structure, the structure is suitable for high frequency testing.

In the test structures of FIG. 1 and FIG. 2, the controllable switching devices connected to the plurality of resistive memory cells to be tested have the same switching characteristics. However, it is not limited to this. The controllable switching devices connected to the plurality of resistive memory cells to be tested in the test structure may have different switching characteristics. For example, in particular, when the number of test samples is an even number, every two MTJs are a group, and the two MTJs in each group are respectively connected to the NMOS tube and the PMOS tube.

Further, when the durability test is performed based on the test structure of FIG. 1, the external connection relationship is shown in FIG. 3. Pad A and Pad B are respectively connected to the two input terminals of the pulse generator through corresponding probes; Pad1 to PadK pass The probe is connected to the output end of the switch matrix, the input end of the switch matrix is connected to a voltage applying device (such as an SMU or a voltage source), and the switch of each NMOS tube can be controlled separately.

The method for durability testing using the test structure of FIG. 3 includes the following steps:

1. After the test structure is connected, apply voltage to each control signal electrode Pad1-PadK in sequence to turn on the corresponding NMOS tube, read the resistance between the first test electrode Pad B and the second test electrode Pad A, that is, the measurement Corresponding to the resistance value of each MTJ in the test structure, determine whether the MTJ is normal, mark the MTJ with normal resistance value, and obtain the MTJ sequence;

2. Simultaneously apply voltage to the control signal electrode connected to the gate of the NMOS tube corresponding to the MTJ sequence to make the corresponding NMOS tube conductive, and read the resistance between the first test electrode Pad B and the second test electrode Pad A , That is, measure the initial parallel resistance of all MTJs in the MTJ sequence;

3. Maintain the control signal electrode connected to the gate of the NMOS tube corresponding to the MTJ sequence while applying voltage to make the corresponding NMOS tube fully conductive, and apply a specific pulse width and amplitude between the first test electrode PadB and the second test electrode PadA Value of the pulse sequence, the pulse sequence is applied once or repeated multiple times; then measure the parallel resistance of all MTJs in the MTJ sequence to determine whether the change in parallel resistance is greater than a certain threshold R_jump; repeat the process until the parallel resistance The change value of is greater than a certain threshold R_jump, and record the corresponding number of applied pulses as n;

4. Cancel the voltage applied to the control signal electrode connected to the gate of the NMOS tube corresponding to the MTJ sequence, and sequentially apply voltage to the control signal electrode connected to the gate of the NMOS tube corresponding to the MTJ sequence to turn on the corresponding NMOS tube. Measure the resistance value corresponding to each MTJ, determine whether the MTJ is normal, mark the MTJ with normal resistance, and obtain a new MTJ sequence. For the MTJ that has failed, record the durability test data of the failed MTJ as the applied pulse in step 3 Times n;

5. Repeat steps 2-4 until the new sample sequence is empty, that is, all MTJs are completely invalid, or the number of applied pulses reaches the set upper limit. When the number of applied pulses reaches the set upper limit, the resistance value The durability test data of a normal MTJ is set to be greater than this upper limit.

Through the above test method, the combination of the resistive memory unit to be tested and the switching device can enable the gating of the device to be tested and the test signal, and thus the durability test can be performed on multiple devices at the same time, improving test efficiency and saving test time. As shown in Figure 4, taking the actual test results of 19 MTJ devices in parallel as an example, a group of MTJ Endurance test values can be obtained. The number of device pulses corresponding to resistance monitoring is 1.3.5.10.30.50.70.100.300.500..., and each resistance reduction jump in FIG. 4(a) corresponds to (threshold voltage 10ohm) 1 or more MTJ breakdowns. One test can get 19 MTJ Endurance statistics shown in Figure 4(b).

In addition, if there are both NMOS tubes and PMOS tubes in the test structure, the test method is similar to the aforementioned method and will not be described in detail. Just note that when detecting the status of each MTJ separately, when detecting the status of the MTJ connected to the NMOS tube, the remaining other NMOS tube gates are connected to a low potential, and the remaining other PMOS tube gates are connected to a high potential, so that the remaining other MOS The tube is in the cut-off state. That is, when the resistance value of a certain MTJ is separately detected, the MOS tube connected to the MTJ is turned on, and the other MOS tubes are all turned off.

Next, supplement the feasibility of the above test methods.

The resistance value R _{p of} MTJ is generally above 4kΩ, and the resistance value R _down after device failure is generally less than 1kΩ. Take R _p = 4kΩ and R _down = 1kΩ for example.

If the test sample is 20, and the 20 MTJ detections are all normal devices in the initial state, the initial parallel resistance

Assuming a cyclic test, an MTJ fails after applying N pulses, and the failure criterion is:

The corresponding resistance jump value is 20Ω. In addition, if more MTJs fail simultaneously, the corresponding resistance jump value is larger. Therefore, the failure process can be accurately detected by setting the threshold R_jump in the test step to 10Ω.

In subsequent tests, the initial parallel resistance after removing a failed device

Continue the cyclic test. After applying M pulses, another MTJ fails. The failure criterion is:

The corresponding resistance jump value is 22.5Ω. In addition, if multiple MTJs fail simultaneously, the resistance jump value is greater. Therefore, it is completely feasible to set the threshold R_jump in the test step to 10Ω.

Moreover, as the number of cycle tests increases, and the failed device is excluded from the parallel circuit, the detection window for subsequent tests becomes larger and larger. The minimum detection window corresponding to the present invention is the detection of 10Ω level changes on the 100Ω level resistance value, and the reliability is high.

A person of ordinary skill in the art may understand that all or part of the processes in the method of the foregoing embodiments may be completed by instructing relevant hardware through a computer program, and the program may be stored in a computer-readable storage medium. During execution, the process of the above method embodiments may be included. Wherein, the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

The above are only specific embodiments of the present invention, but the scope of protection of the present invention is not limited to this. Any person familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A test structure for a resistive memory unit is characterized by comprising a plurality of resistive memory units to be tested, each resistive memory unit to be tested is respectively connected with a controllable switching device, and each resistive memory to be tested The first connection terminal of the unit is connected at one point and is commonly connected to the first test electrode. The second connection terminal of each resistive memory cell to be tested is respectively connected to the first connection terminal of the corresponding controllable switching device, each controllable The second connection terminal of the switching device is connected at one point and is commonly connected to the second test electrode, and the control terminal of each controllable switching device is connected to the respective control signal electrode, wherein the first test electrode and the second test electrode Input read-write signal, each control signal electrode is used to input control signal of controllable switch device.
The test structure according to claim 1, wherein the first test electrode and the second test electrode adopt a GSG structure or a GS structure.
The test structure according to claim 1, wherein the controllable switching device is a voltage-controlled switching device, and the controllable switching devices connected to different resistive memory cells to be tested have the same or opposite switching characteristics.
The test structure according to claim 3, wherein the controllable switching device is an N/PMOS tube, BJT or IGBT.
The test structure according to claim 3, wherein the plurality of resistive memory cells to be tested are an even number, and each two is a group, and the two resistive memory cells to be tested in each group are connected Of controllable switching devices have opposite switching characteristics.
The test structure according to claim 1, wherein the resistive memory cell is a magnetic tunnel junction MTJ.
A method for testing the durability of a test structure for resistive memory cells according to claim 1, characterized in that it includes:

1) Apply voltage to each control signal electrode in sequence, measure the resistance of each resistive memory cell to be tested in the test structure, and mark the resistive memory cell to be tested with normal resistance to obtain a sample sequence;

2) Simultaneously apply voltage to the control signal electrodes corresponding to the sample sequence, and measure the initial parallel resistance of all the resistive memory cells to be tested in the sample sequence;

3) Keep applying voltage to the control signal electrodes corresponding to the sample sequence, and repeat the following process: apply a specific excitation signal between the first test electrode and the second test electrode, and measure the parallel resistance of all the resistive memory cells to be tested in the sample sequence Value until the difference between the obtained parallel resistance and the initial parallel resistance is greater than the set threshold, and record the number of times the excitation signal is applied;

4) Apply voltage to the control signal electrodes corresponding to the sample sequence in sequence, measure the resistance of each resistive memory cell to be tested in the sample sequence, mark the resistive memory cell to be tested with normal resistance, and obtain a new sample sequence, and Record the durability test data of the resistance memory cell to be tested with abnormal resistance value as the number of times of the excitation signal application in step 3);

5) Follow steps 2)-4) to continue testing the new sample sequence, and repeat the process until the new sample sequence is empty, or the number of times the excitation signal is applied reaches the set upper limit, when the number of times the excitation signal is applied When the set upper limit value is reached, the durability test data of the resistive memory cell to be tested with a normal resistance value is set to be greater than the upper limit value.
The method according to claim 7, wherein the set threshold is 10 ohms.