CN112151102B

CN112151102B - Test structure and test method

Info

Publication number: CN112151102B
Application number: CN201910580420.4A
Authority: CN
Inventors: 何世坤; 王明; 竹敏
Original assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Current assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2022-09-27
Anticipated expiration: 2039-06-28
Also published as: CN112151102A; WO2020258822A1

Abstract

The application provides a test structure and a test method. This test structure tests at least one device group that awaits measuring, and the device group that awaits measuring includes a plurality of parallelly connected devices that hinder, and each hinders and hinders the device and include first end, second end and third end, and the first end that hinders the device is read end, and the second end that hinders the device is write-in end, and the test structure includes: the first ends of the first switches are electrically connected with the reading ends in a one-to-one correspondence manner; the first ends of the second switches are electrically connected with the writing ends in a one-to-one correspondence manner; the first testing electrodes are respectively and electrically connected with the third ends of the resistance change devices in the at least one device group to be tested; and each second test electrode is electrically connected with the second end of each first switch and the second end of each second switch in at least one device group to be tested respectively. By controlling the test structure, the read-write resistant times of a plurality of resistance change devices can be tested at one time.

Description

Test structure and test method

Technical Field

The present application relates to the field of memories, and in particular, to a test structure and a test method.

Background

Magnetic random access memory MRAM, which has been rapidly developed in recent years, has excellent characteristics: the defects of large SRAM area and large electric leakage after the size is miniaturized are overcome; the defects that the DRAM needs to be refreshed all the time and has large power consumption are overcome; the read-write time is short, the read-write times are more, and the two performances are superior to those of Flash memory by several orders of magnitude.

As a memory device, it is required to have an excellent read/write cycle, and therefore, a reliability test of the read/write cycle Endurance (Endurance) is important.

In order to obtain the Endurance reliability distribution of the device in the research and development stage and ensure the reliability of the product in the mass production stage, more test samples are selected. In the current enterprise test, samples are generally tested one by one, and then reliability analysis is performed on test data.

Generally, the testing machine has limited resources, so the time spent on reliability tests such as Endurance is very long (if the throughput of one sample reaches 10) ¹⁰ Second, the testing time is 3h), taking MTJ as an example, the corresponding failure probability in the implementation test is shown in fig. 1.

Spin Orbit Torque effect Magnetic Random Access Memory (SOT-MRAM) is mainly aimed at increasing the speed and the Endurance of MRAM, and it is expected that the Endurance test is more time-consuming than STT-MRAM, and SOT-MRAM is a three-terminal device, and the Endurance of two current paths also needs to be measured.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

The present application mainly aims to provide a test structure and a test method to solve the problem in the prior art that the time consumed for testing the read/write endurance count of a memory having a resistive device is long.

In order to achieve the above object, according to an aspect of the present application, a test structure is provided, where the test structure tests at least one device group to be tested, each device group to be tested includes a plurality of resistive devices connected in parallel, each resistive device includes a first end, a second end, and a third end, the first end of the resistive device is a read end, and the second end of the resistive device is a write end, and the test structure includes: the reading circuit comprises a plurality of first switches, a plurality of second switches and a plurality of control terminals, wherein each first switch comprises a first end, a second end and a first control end, and the first ends of the first switches are electrically connected with the reading terminals in a one-to-one correspondence manner; a plurality of second switches, each of the second switches including a first terminal, a second terminal, and a second control terminal, the first terminals of the second switches being electrically connected to the write terminals in a one-to-one correspondence; the first testing electrodes are electrically connected with the third ends of the resistive devices in the at least one device group to be tested respectively; and each second test electrode is electrically connected with the second end of each first switch and the second end of each second switch in at least one device group to be tested respectively.

Further, the test structure further comprises: a plurality of first control electrodes, where the first control electrodes are electrically connected to the first control end of one of the first switches or to the first control ends of a plurality of the first switches, respectively, and the first control electrodes are used to control the switching states of the first switches, and under the condition that the first control electrodes are electrically connected to a plurality of the first switches, any two first switches electrically connected to one of the first control electrodes are electrically connected to the read ends in different sets of devices to be tested; and under the condition that the second control electrodes are electrically connected with the plurality of second switches, any two second switches electrically connected with one second control electrode are electrically connected with the writing ends in different device groups to be tested.

Furthermore, there is one device to be tested, there is one first test electrode, there is one second test electrode, the first control electrode is electrically connected to the first control end in a one-to-one correspondence manner, and the second control electrode is electrically connected to the second control end in a one-to-one correspondence manner.

Further, the switch matrix comprises a plurality of input interfaces, a plurality of output interfaces, at least one first power interface and at least one second power interface, the plurality of output interfaces comprise a first group of output interfaces, the first group of output interfaces comprise a plurality of output interfaces, the output interfaces of the first group of output interfaces are electrically connected with the first control electrodes in a one-to-one correspondence manner, the number of the output interfaces of the first group of output interfaces is greater than or equal to the number of the first control electrodes, the first power interfaces are electrically connected with the first test electrodes in a one-to-one correspondence manner, and the second power interfaces are electrically connected with the second test electrodes in a one-to-one correspondence manner; and the voltage applying device comprises a plurality of voltage output terminals, and the voltage output terminals are electrically connected with the input interfaces in a one-to-one correspondence manner.

Furthermore, the plurality of output interfaces further include a second group of output interfaces, the second group of output structures includes a plurality of output interfaces, the output interfaces of the second group of output interfaces are electrically connected with the second control electrodes in a one-to-one correspondence manner, and the number of the output interfaces of the second group of output interfaces is greater than or equal to the number of the second control electrodes.

Further, the test structure further comprises: the encoder comprises a plurality of input ends and a plurality of output ends, the input ends correspond to the output ends one by one, each input end is electrically connected with the first control electrode or the second control electrode, each output end is electrically connected with the first control end or the second control end, the output end corresponding to the input end electrically connected with the first control electrode is electrically connected with the first control end, and the output end corresponding to the input end electrically connected with the second control electrode is electrically connected with the second control end.

Further, it is a plurality of the input includes a plurality of first inputs and second inputs, and is a plurality of the output includes a plurality of first outputs and second output, first input with first control electrode one-to-one is connected, first output with first control end one-to-one is connected, the second input with second control electrode one-to-one is connected, the second output with the second control end one-to-one is connected.

Further, the first switch and the second switch are independently selected from an NMOS transistor, a PMOS transistor, a transmission gate or a triode.

Further, the resistive switching device comprises a spin orbit torque providing line and a resistive switching structure located on the spin orbit torque providing line, and preferably, the resistive switching structure is an MTJ.

According to another aspect of the present application, there is provided a test method implemented using any one of the test structures described herein.

Further, the test method comprises a process of testing the write endurance, wherein the process of testing the write endurance comprises the following steps: a1, acquiring the initial resistance of an undamaged part in a device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently; step a2, controlling the first switch corresponding to the damaged resistive switching device to be turned off and the second switch to be turned off, controlling the second switch corresponding to the undamaged portion to be turned on and the first switch to be turned off, and applying a first predetermined number of predetermined pulse signals between the first test electrode and the second test electrode; step A3, controlling the first switch corresponding to the undamaged part to be switched on and the second switch to be switched off, applying voltage between the first test electrode and the second test electrode, and detecting the current resistance of the undamaged part; step A4, repeating steps A2 and A3 for 1 times or more in sequence, stopping applying the pulse signal until the difference value between the detected resistance of the undamaged portion and the previously detected resistance is larger than a first preset threshold value, and recording the number of times of the currently applied pulse signal; step a5, controlling the second switch corresponding to the undamaged portion to be turned off, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one first switch corresponding to the undamaged portion to be in an on state, and the other first switches to be in an off state, detecting the resistance of each resistive switching device of the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device of the undamaged portion is smaller than a second predetermined threshold value, and determining the write endurance number of the damaged resistive switching device according to the number of the pulse signals; step a6, repeatedly executing the steps a1 to a5 until all the resistive devices in the device group to be tested are damaged, or until the number of times of applying the pulse signal is equal to a second predetermined number of times, wherein the second predetermined number of times is greater than the first predetermined number of times.

Further, the step a1 includes: sequentially controlling one first switch to be in a conducting state, and the other first switches to be in a switching-off state, detecting the resistance of each resistance change device, and determining that the resistance change device is damaged under the condition that the resistance of the resistance change device is smaller than a second preset threshold value; and controlling the first switch corresponding to the damaged resistive switching device to be switched off, switching on the other first switches and switching off the second switches, applying voltage between the first test electrode and the second test electrode corresponding to one device group to be tested, and detecting the initial resistance of the undamaged part.

Further, the test method comprises a read endurance test process, wherein the read endurance test process comprises: step C1, acquiring the initial resistance of the undamaged part in the device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently; step C2, controlling the first switch corresponding to the damaged resistive switching device to be turned off and the second switch to be turned off, controlling the first switch corresponding to the undamaged portion to be turned on and the second switch to be turned off, and applying a predetermined pulse signal for a third predetermined number of times between the first test electrode and the second test electrode; step C3, keeping the first switches corresponding to the undamaged portions turned on and the second switches turned off, applying a voltage between the first test electrode and the second test electrode, and detecting the current resistance of the undamaged portions; step C4, repeating steps C2 and C3 in sequence for more than or equal to 1 time, stopping applying the pulse signal and recording the number of times of the pulse signal currently applied in the case that the difference value between the detected resistance of the undamaged portion and the resistance detected last time is more than a first predetermined threshold value; step C5, controlling the second switch corresponding to the undamaged portion to be turned off, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one first switch corresponding to the undamaged portion to be in an on state and the other first switches to be in an off state, detecting the resistance of the resistive switching device of the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device of the undamaged portion is smaller than a second predetermined threshold, and determining the read endurance frequency of the damaged resistive switching device according to the frequency of the pulse signal; and step C6, sequentially and repeatedly executing the steps C1 to C5 at least once until all the resistive devices in the device group to be tested are damaged, or until the number of times of applying the pulse signal is equal to a fourth predetermined number of times, wherein the fourth predetermined number of times is greater than the third predetermined number of times.

Further, the step C1 includes: sequentially controlling one first switch to be in a conducting state, and the other first switches to be in a switching-off state, detecting the resistance of each resistance change device, and determining that the resistance change device is damaged under the condition that the resistance of the resistance change device is smaller than a second preset threshold value; and controlling the first switch corresponding to the damaged resistive random access device to be turned off, turning on the other first switches and turning off the second switches, applying voltage between the first test electrode and the second test electrode corresponding to one device group to be tested, and detecting the initial resistance of the undamaged part.

Furthermore, the test structure further includes a plurality of first control electrodes and a plurality of second control electrodes, the first control electrode is electrically connected to the first control end of one of the first switches, and the second control electrode is electrically connected to the second control end of one of the second switches.

By applying the technical scheme of the application, in the test structure, when the voltage is applied between the first test electrode and the second test electrode and the plurality of first switches are controlled to be switched on and the plurality of second switches are controlled to be switched off, the plurality of resistance change devices can be read, and when the first switches are controlled to be switched off and the second switches are controlled to be switched on, the plurality of resistance change devices can be written. The resistance testing method comprises the steps of controlling a first switch, a second switch, a first testing electrode and a second testing electrode in the testing structure, writing and reading a plurality of resistance changing devices in at least one device group to be tested for a plurality of times, testing the resistance values of the device group to be tested after writing and reading for a plurality of times, and subsequently determining the read-resistant times and the write-resistant times of each resistance changing device according to the testing resistance values. The test structure is controlled to simultaneously test the read-write resistant times of a plurality of resistive devices at one time, and compared with the test structure which can only test one resistive device at one time in the prior art, the test structure can greatly shorten the test time of the read-write resistant times of the resistive devices.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 is a graph showing statistical relationship between the MTJ resistance times at high voltage based on 50 MTJs;

FIG. 2 shows a schematic structural diagram of a test structure according to an embodiment of the present application;

FIG. 3 shows a schematic structural diagram of a test structure according to another embodiment of the present application; and

FIG. 4 is a schematic diagram illustrating a test structure according to yet another embodiment of the present application.

Wherein the figures include the following reference numerals:

01. a resistive device; 10. a first switch; 20. a second switch; 30. a first test electrode; 40. a second test electrode; 50. a first control electrode; 60. a second control electrode; 70. a switch matrix; 80. a voltage applying device; 90. an encoder.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background art, the test of the endurance read and write times of the memory having the resistance change device in the related art takes a long time. To solve this technical problem, according to an embodiment of the present application, a test structure is provided.

Fig. 2 shows a schematic structural diagram of a test structure of an embodiment of the present application. As shown in fig. 2, the test structure tests at least one device group to be tested, each device group to be tested includes a plurality of resistive devices 01 connected in parallel, each resistive device 01 includes a first end, a second end, and a third end, the first end of the resistive device 01 is a read end, the second end of the resistive device 01 is a write end, and the test structure includes:

a plurality of first switches 10, each of the first switches 10 including a first terminal, a second terminal, and a first control terminal, the first terminals of the first switches 10 being electrically connected to the read terminals in a one-to-one correspondence, that is, the first terminal of one of the first switches 10 being electrically connected to one of the read terminals, one of the first switches 10 including only one first terminal, and one of the resistive switching devices 01 including only one of the read terminals, so that the number of the first switches 10 is the same as the number of the resistive switching devices 01, and one of the read terminals being electrically connected to only one of the first switches 10;

a plurality of second switches 20, each of the second switches 20 including a first terminal, a second terminal, and a second control terminal, the first terminals of the second switches 20 being electrically connected to the write terminals in a one-to-one correspondence, that is, the first terminal of one of the second switches 20 being electrically connected to one of the write terminals, one of the second switches 20 including only one first terminal, and one of the resistive switching devices 01 including only one of the write terminals, so that the number of the second switches is the same as the number of the resistive switching devices 01, and one of the write terminals is electrically connected to only one of the second switches 20;

at least one first test electrode 30, where each first test electrode 30 is electrically connected to a third end of each resistive device in at least one device group to be tested, that is, the third end of each resistive device in one device group to be tested is electrically connected to one first test electrode 30;

at least one second test electrode 40, each second test electrode 40 being electrically connected to the second end of each first switch 10 and the second end of each second switch 20 in at least one device group to be tested, i.e. the second end of each first switch 10 and the second end of each second switch 20 in one device group to be tested are electrically connected to one second test electrode 40.

In the test structure, when a voltage is applied between the first test electrode and the second test electrode and the plurality of first switches are controlled to be on and the plurality of second switches are controlled to be off, the plurality of resistive devices can be read, and when the first switches are controlled to be off and the second switches are controlled to be on, the plurality of resistive devices can be written. The resistance testing method comprises the steps of controlling a first switch, a second switch, a first testing electrode and a second testing electrode in the testing structure, writing and reading a plurality of resistance changing devices in at least one device group to be tested for a plurality of times, testing the resistance values of the device group to be tested after writing and reading for a plurality of times, and subsequently determining the read-resistant times and the write-resistant times of each resistance changing device according to the testing resistance values. The test structure is controlled, so that the read-write resistant times of a plurality of resistance change devices can be tested at one time, and compared with the test structure in the prior art, which can only test one resistance change device at one time, the test structure can greatly shorten the time consumption for testing the read-write resistant times of the resistance change devices.

In order to flexibly control the switch states of the plurality of first switches and the plurality of second switches, so as to improve the efficiency of the read/write endurance test, in an embodiment of the present application, as shown in fig. 2, the test structure further includes a plurality of first control electrodes 50 and a plurality of second control electrodes 60, wherein the first control electrode 50 is electrically connected to the first control terminal of one of the first switches 10 or the first control terminals of the plurality of first switches 10, respectively, that is, the first control terminal of one of the first switches 10 of one of the dut groups is electrically connected to one of the first control electrodes 50 or the first control terminal of one of the first switches 10 of each of the dut groups is electrically connected to one of the first control electrodes 50, the first control electrode 50 is used to control the switch state of the first switch 10, and in the case that the first control electrode 50 is electrically connected to the plurality of first switches 10, any two of the first switches 10 electrically connected to one of the first control electrodes 50 are electrically connected to the reading terminals in different sets of devices to be tested, that is, a plurality of first switches electrically connected to one of the first control electrodes 50 belong to different sets of devices to be tested; the second control electrode 60 is electrically connected to the second control terminal of one of the second switches 20 or the second control terminals of a plurality of the second switches 20, i.e. the second control terminal of one of the second switches 20 of one of the groups of devices to be tested is electrically connected to a second control electrode 60 or the second control terminals of one of the second switches 20 of each of the groups of devices to be tested are electrically connected to a second control electrode 60, the second control electrode 60 is used for controlling the switching state of the second switch 20, in the case where the second control electrode 60 is electrically connected to a plurality of the second switches 20, any two of the second switches 20 electrically connected to one of the second control electrodes 60 are electrically connected to the write terminals in different sets of the devices under test, that is, a plurality of second switches electrically connected to one second control electrode 60 belong to different groups of devices to be tested.

It should be noted that the test structure of the present application does not necessarily include the first control electrode and the second control electrode, that is, the switch state of the switch is not necessarily controlled by the control electrode, and any other control method capable of controlling the switch state of the switch may be adopted. In addition, the first control electrode and the second control electrode of the present application may be any suitable structure of electrodes in the prior art, and in a specific embodiment of the present application, both the first control electrode and the second control electrode are pads (Pad).

Specifically, one first control electrode can control the switching states of a plurality of first switches, any two first switches electrically connected with one first control electrode are electrically connected with the reading terminals in different sets of devices to be tested, and when the test structure tests different sets of devices to be tested, the first control electrode can control the switching states of the first switches of the corresponding set of devices to be tested through switching, so as to control the reading operation of the resistive switching devices of the corresponding set of devices to be tested; the second control electrode can control the switch states of the second switches, and when the test structure tests different device groups to be tested, the first control electrode can control the switch state of the first switch of the corresponding device group to be tested through switching, so that the writing operation of the resistive switching device of the corresponding device group to be tested is controlled.

The test structure of the present application can test one device group to be tested, and can also test a plurality of device groups to be tested, and when the test structure tests one or a plurality of device groups to be tested, the types and connection modes of the devices in the test structure are the same, and the difference is only the number of the devices, so the following description will be given by taking the test structure for testing one device group to be tested as an example.

In a specific embodiment of the present application, as shown in fig. 2, the device to be tested has one, the first test electrode 30 has one, the second test electrode 40 has one, the first control electrodes 50 are electrically connected to the first control terminals in a one-to-one correspondence manner, that is, one first control electrode 50 is electrically connected to one first control terminal, one first switch 10 includes only one first control terminal, so that the number of the first control electrodes 50 is the same as the number of the first switches 10, one first control terminal is electrically connected to only one first control electrode 50, the second control electrodes 60 are electrically connected to the second control terminals in a one-to-one correspondence manner, that is, one second control electrode 60 is electrically connected to one second control terminal, one second switch 20 includes only one second control terminal, therefore, the number of the second control electrodes 60 is the same as that of the second switches 20, and one of the second control terminals is electrically connected to only one of the second control electrodes 60.

In order to control the working state of the first control electrode flexibly, efficiently and in a simple manner, and further improve the efficiency of the read/write endurance test, in an embodiment of the present application, as shown in fig. 2, the test structure further includes a switch matrix 70 and a voltage applying device 80, wherein the switch matrix 70 includes a plurality of input interfaces, a plurality of output interfaces, at least one first power interface, and at least one second power interface, the plurality of output interfaces includes a first group of output interfaces, the first group of output interfaces includes a plurality of output interfaces, the output interfaces of the first group of output interfaces are electrically connected to the first control electrodes 50 in a one-to-one correspondence manner, the number of output interfaces of the first group of output interfaces is greater than or equal to the number of first control electrodes 50, and the first power interfaces are electrically connected to the first test electrodes 30 in a one-to-one correspondence manner, namely, one of the device groups to be tested includes one of the first test electrodes 30, a plurality of the first test electrodes 30 electrically connected to the plurality of first power interfaces in a one-to-one correspondence belong to different device groups to be tested, and the second power interfaces are electrically connected to the second test electrodes 40 in a one-to-one correspondence, that is, one of the device groups to be tested includes one of the second test electrodes 40, and a plurality of the second test electrodes 40 electrically connected to the plurality of second power interfaces in a one-to-one correspondence belong to different device groups to be tested; the voltage applying device 80 includes a plurality of voltage output terminals electrically connected to the input interfaces in a one-to-one correspondence. Specifically, the voltage output terminals of the voltage applying device are electrically connected to the input interfaces in a one-to-one correspondence, and the switch matrix 70 transmits the voltage of the voltage output terminals to the output interfaces of the first group of output interfaces through the corresponding input interfaces, and then applies the voltage to the first control electrode 50 through the output interfaces of the first group of output interfaces, so as to control the on-off state of the first switch 10 through the first control electrode 50, and further control the reading operation on the resistive switching device.

In order to flexibly and efficiently control the operating state of the second control electrode in a simple manner and further improve the efficiency of the read/write endurance test, in an embodiment of the present application, as shown in fig. 2, the plurality of output interfaces further includes a second group of output interfaces, the second group of output structures includes a plurality of output interfaces, the output interfaces of the second group of output interfaces are electrically connected to the second control electrode 60 in a one-to-one correspondence, and the number of the output interfaces of the second group of output interfaces is greater than or equal to the number of the second control electrodes 60. Specifically, the voltage output terminals of the voltage applying device are electrically connected to the input interfaces in a one-to-one correspondence manner, the switch matrix 70 transmits the voltage of the voltage output terminals to the output interfaces of the second group of output interfaces through the corresponding input interfaces, and then applies the voltage to the second control electrode 60 through the output interfaces of the second group of output interfaces, so that the second control electrode 60 controls the switching state of the second switch 20, and thus controls the writing operation on the resistive switching device.

It should be noted that the switch matrix may further implement conduction between the input interface and the corresponding first power interface according to the control instruction, and implement electrical connection between the voltage applying device and the first testing electrode, and the switch matrix may further implement conduction between the input interface and the corresponding second power interface according to the control instruction, and implement electrical connection between the voltage applying device and the second testing electrode, so as to apply a voltage between the first testing electrode and the second testing electrode.

In order to control the switch states of the corresponding first switch and second switch flexibly and efficiently and in a simple manner, and further improve the efficiency of the read/write endurance test, in an embodiment of the present application, as shown in fig. 3 and 4, the test structure further includes an encoder 90, where the encoder 90 includes a plurality of input terminals and a plurality of output terminals, the input terminals and the output terminals are in one-to-one correspondence, that is, one of the input terminals is electrically connected to only one of the output terminals, each of the input terminals is electrically connected to the first control electrode 50 or the second control electrode 60, each of the output terminals is electrically connected to the first control terminal or the second control terminal, and the output terminal corresponding to the input terminal electrically connected to the first control electrode 50 is electrically connected to the first control terminal, that is, if the input terminal is electrically connected to the first control electrode, the corresponding output terminal thereof is electrically connected to the first control terminal, and the output terminal corresponding to the input terminal electrically connected to the second control electrode 60 is electrically connected to the second control terminal, i.e., if the input terminal is electrically connected to the second control electrode, the corresponding output terminal thereof is electrically connected to the second control terminal. Specifically, the encoder 90 transmits the voltage of the input end to the corresponding output end, and applies the voltage to the first switch 10 through the output end, so as to control the on-off state of the first switch 10, and then control the reading operation of the resistive switching device, or the encoder 90 transmits the voltage of the input end to the corresponding output end, and applies the voltage to the second switch 20 through the output end, and thus control the on-off state of the second switch 20, and then control the reading operation of the resistive switching device. The input end of the encoder in fig. 3 is electrically connected to the first control electrode 50, and the corresponding output end is electrically connected to the first control end; the input end of the encoder in fig. 4 is electrically connected to the second control electrode 60, and the corresponding output end is electrically connected to the second control end.

Note that, the following two connection methods are included, in which each of the input terminals is electrically connected to the first control electrode 50 or the second control electrode 60, each of the output terminals is electrically connected to the first control terminal or the second control terminal, and the output terminal corresponding to the input terminal electrically connected to the first control electrode 50 is electrically connected to the first control terminal: in the first mode, the input end of the encoder is electrically connected with the first control electrode, the output end of the encoder is electrically connected with the first control end, in the second mode, the input end of the encoder is electrically connected with the second control electrode, and the output end of the encoder is electrically connected with the second control end. That is, the encoder only controls the read test or the write test, and a test structure generally includes only one encoder, as shown in fig. 3 and 4.

In order to further improve the efficiency of the read/write endurance test, in a specific embodiment of the present application, the plurality of input terminals include a plurality of first input terminals and second input terminals, the plurality of output terminals include a plurality of first output terminals and second output terminals, the first input terminals are electrically connected to the first control electrodes 50 in a one-to-one correspondence, the first output terminals are electrically connected to the first control terminals in a one-to-one correspondence, that is, one first control electrode 50 is electrically connected to only one first input terminal, the second input terminals are electrically connected to the second control electrodes 60 in a one-to-one correspondence, and the second output terminals are electrically connected to the second control terminals in a one-to-one correspondence, that is, one second control electrode 60 is electrically connected to only one second input terminal. Wherein the first input terminal and the first output terminal are in one-to-one correspondence, so as to realize that the first control electrode 50 is electrically connected with the first control terminal of the first switch 10, and the second input terminal and the second output terminal are in one-to-one correspondence, so as to realize that the second control electrode 60 is electrically connected with the second control terminal of the second switch 20.

In a specific embodiment of the present application, the first switch and the second switch are independently selected from an NMOS transistor, a PMOS transistor, a transmission gate, a triode, or an IGBT. Of course, the first switch and the second switch of the present application are not limited to the NMOS transistor, the PMOS transistor, the transmission gate, the triode, or the IGBT, and those skilled in the art can select a suitable switching device according to the actual situation.

In a specific embodiment of the present application, as shown in fig. 3, the resistive switching device includes a spin orbit torque providing line and a resistive switching structure on the spin orbit torque providing line, and preferably, the resistive switching structure is an MTJ. Of course, the resistive switching structure of the present application is not limited to the MTJ and the corresponding spin-orbit torque supply line, and a person skilled in the art may select a resistive switching device having a suitable structure according to actual conditions, and any three-terminal memory device with separate read and write functions may be used.

The embodiment of the present application further provides a test method, and it should be noted that the test method in the embodiment of the present application may be used for implementing a test by using the test structure provided in the embodiment of the present application. The following describes the test methods provided by the examples of the present application.

In an embodiment of the present application, the test method includes a process of testing the write endurance count, where the process of testing the write endurance count includes: step A1, acquiring an initial resistance of an undamaged part in a device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently, and the resistance change device of the undamaged part may be damaged in the subsequent actual pulse testing process; step a2, controlling the first switch corresponding to the damaged resistive switching device to be turned off and the second switch to be turned off, that is, the damaged device is not tested any more subsequently, controlling the second switch corresponding to the undamaged part to be turned on and the first switch to be turned off, and applying a first predetermined number of predetermined pulse signals between the first test electrode and the second test electrode; a step a3 of controlling the first switch corresponding to the undamaged portion to be turned on and the second switch to be turned off, applying a voltage between the first test electrode and the second test electrode, and detecting a current resistance of the undamaged portion, which may include a resistance of a damaged resistive switching device; step a4, repeating steps a2 and A3 in sequence for 1 or more times, stopping applying the pulse signal and recording the number of times of the pulse signal currently applied when the difference between the detected resistance of the undamaged portion and the previously detected resistance is greater than a first predetermined threshold, wherein of course, the number of times of the pulse signal before step a2 is 0, that is, the initial value is 0; a step a5 of turning off the second switch corresponding to the undamaged portion, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one of the first switches corresponding to the undamaged portion to be in an on state and the other first switches to be in an off state, detecting the resistance of each of the resistive switching devices in the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device in the undamaged portion is smaller than a second predetermined threshold, and determining the number of times of writing of the damaged resistive switching device based on the number of times of the pulse signal; step a6, repeating the steps a1 to a5 until all the resistive devices in the set of devices to be tested are damaged or until the number of times of applying the pulse signal is equal to a second predetermined number of times, wherein the second predetermined number of times is greater than the first predetermined number of times.

In the process of the write endurance test, step a1 is executed to detect the initial resistance of the undamaged part in the device group to be tested, and each time step a2 is repeatedly executed, the first predetermined number of write operations are performed on the resistive switching device, and then step a3 is performed to measure the resistance of one undamaged portion at a time, until the difference between the detected resistance of the undamaged portion and the previous detected resistance is greater than a first predetermined threshold, recording the number of times of the currently applied pulse signal, executing step A5 to detect the resistance of the undamaged resistive switching device, determining the resistive switching device with the resistance smaller than a second preset threshold value as a damaged device, and determining the write endurance times as the times of recording the current write operation, and repeatedly executing the step A1 to the step A5 until the write endurance times of all the resistive random access devices are determined or all the resistive random access devices reach the qualified write endurance times. The test method is executed by adopting the test structure, and can simultaneously test the write-resistant times of a plurality of resistive devices at one time, so that the test time consumption of the write-resistant times of the resistive devices is greatly shortened.

In order to further improve the accuracy of detection and the efficiency of testing, in an embodiment of the present application, the step a1 includes: sequentially controlling one of the first switches to be in an on state and the other first switches to be in an off state, detecting the resistance of each of the resistive switching devices, and determining that the resistive switching device has been damaged when the resistance of the resistive switching device is smaller than the second predetermined threshold; and controlling the first switch corresponding to the damaged resistive switching device to be turned off, the other first switches to be turned on and the second switches to be turned off, applying voltage between the first test electrode and the second test electrode corresponding to one device group to be tested, and detecting the initial resistance of the undamaged part.

It should be noted that, once a certain resistive switching device is damaged, the resistance value of the damaged device is not calculated when the initial resistance of the undamaged portion is tested next time. Namely, the first switch corresponding to the damaged resistive switching device is kept to be turned off all the time.

In an embodiment of the present application, the test method further includes a read endurance test process, where the read endurance test process includes: step C1, acquiring an initial resistance of an undamaged part in the device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently, and the resistance change device of the undamaged part may be damaged in the subsequent actual pulse testing process; step C2, turning off the first switch and turning off the second switch corresponding to the damaged resistive switching device, turning on the first switch and turning off the second switch corresponding to the undamaged portion, and applying a predetermined pulse signal for a third predetermined number of times between the first test electrode and the second test electrode; step C3, keeping the first switches corresponding to the undamaged portions turned on and the second switches turned off, applying a voltage between the first test electrode and the second test electrode, and detecting the current resistance of the undamaged portions, which may include the resistance of the damaged resistive switching device; step C4, repeating steps C2 and C3 for 1 or more times in sequence, stopping applying the pulse signal until the difference between the detected resistance of the undamaged portion and the previously detected resistance is greater than a first predetermined threshold, and recording the number of times the pulse signal is currently applied; a step C5 of turning off the second switch corresponding to the undamaged portion, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one of the first switches corresponding to the undamaged portion to be in an on state and the other first switches to be in an off state, detecting the resistance of the resistive switching device of the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device of the undamaged portion is smaller than a second predetermined threshold, and determining the number of times of reading of the damaged resistive switching device based on the number of times of the pulse signal; and step C6, sequentially repeating the step C1 to the step C5 at least once until all the resistive devices in the device group to be tested are damaged, or until the number of times of applying the pulse signal is equal to a fourth predetermined number of times, wherein the fourth predetermined number of times is greater than the third predetermined number of times.

In the process of the read endurance test, step C1 is executed to detect the initial resistance of the undamaged part in the device group to be tested, and each time step C2 is repeatedly executed, the reading operation is performed for the resistive switching device for the third predetermined number of times, and then step C3 is performed to measure the resistance of one undamaged portion at a time until the difference between the detected resistance of the undamaged portion and the previous detected resistance is greater than the first predetermined threshold value, recording the number of times of the currently applied pulse signal, executing step C5 to detect the resistance of each resistive switching device in the undamaged portion, determining the resistive switching device with the resistance smaller than the second predetermined threshold value as a damaged device, and determining the read endurance times as the times for recording the current read operation, and repeatedly executing the step C1 to the step C5 until the read endurance times of all the resistive random access devices are determined or all the resistive random access devices reach the qualified read endurance times. The test method is executed by adopting the test structure, and can simultaneously test the read-resistant times of the resistance change devices at one time, so that the time consumption for testing the read-resistant times of the resistance change devices is greatly shortened.

It should be noted that, when the read endurance count is tested, it is very likely that a higher read voltage is applied to speed up the test process, and in this case, the step C3 cannot be omitted, but in a test environment with a normal read voltage, the step C3 may be omitted, and the corresponding resistance is directly tested in the step C2.

For example, the device group to be tested is formed by connecting 20 resistive switching devices in parallel, each resistive switching device includes an MTJ and a spin orbit torque providing line which are correspondingly and electrically connected, the resistance of one MTJ is about 4000 Ω, the resistance after failure is about 500 Ω, the 20 MTJs before testing are normal devices, the initial resistance of the device group to be tested is about 200 Ω, in the testing process, when one MTJ fails, the resistance of the undamaged part is about 148.15 Ω, the resistance jump value is about 51.85 Ω, when more MTJs fail, the resistance jump value is larger, after removing a damaged device, the number of resistive switching devices of the undamaged part is reduced by one, the corresponding initial resistance is about 210 Ω, in the testing process, when one MTJ fails, the resistance of the undamaged part is about 153.85 Ω, and the resistance jump value is about 56.15 Ω. In subsequent tests, after the failed (damaged) MTJ is removed, the resistance jump value of the part to be undamaged is detected to be larger, and the reliability is high.

In order to further improve the accuracy of the detection and the testing efficiency, in an embodiment of the present application, before the step C1, the method further includes: sequentially controlling one of the first switches to be in an on state and the other first switches to be in an off state, detecting the resistance of each of the resistive switching devices, and determining that the resistive switching device has been damaged when the resistance of the resistive switching device is smaller than the second predetermined threshold; in the case where the resistance change device has been damaged, the resistance of the damaged resistance change device is not detected in the above step C5. Before the read-resistant times are tested, the resistive devices in the group to be tested are detected, and the damaged resistive devices are screened out, so that the read-resistant times testing efficiency is improved, and the read-resistant times testing efficiency is further improved.

It should be noted that, in the actual testing process, only the read endurance testing process or the write endurance testing process is generally performed, and the read endurance testing process and the write endurance testing process are not performed on the same testing structure.

In a specific embodiment of the present application, the test structure further includes a plurality of first control electrodes and a plurality of second control electrodes, the first control electrodes are electrically connected to the first control terminal of one of the first switches, and the second control electrodes are electrically connected to the second control terminal of one of the second switches. The control method can control the switching state of the first switch through the first control electrode, so as to control the reading operation of the resistance change device electrically connected with the first switch; the control method may further control a switching state of the second switch through the second control electrode, thereby controlling a writing operation to the resistive switching device electrically connected to the second switch.

Of course, the state of the first switch and the second switch is not limited to be controlled by the first control electrode and the second control electrode in the test method, and the state of the first switch and the second switch may be controlled by other suitable manners or structures.

It should be noted that, the test structure of the present invention can be obtained without adding a mask or adding additional process steps on the basis of the existing controllable switch device and memory chip structure, and the test structure of the present invention can also be applied to other test devices requiring long-time testing of multiple samples, or applied to some process steps, which can greatly save resources and time.

In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.

Example 1

As shown in fig. 2, the test structure tests a device group to be tested, the device group to be tested includes a plurality of storage structures connected in parallel, the test structure includes a first test electrode, a second test electrode, a plurality of first switches, a plurality of second switches, a plurality of first control electrodes and a plurality of second control electrodes, the storage structure is an MTJ, the first switches are first MOS transistors, the second switches are second MOS transistors, the first control electrodes are electrically connected to the gates of the first MOS transistors in a one-to-one correspondence, the second control electrodes are electrically connected to the gates of the second MOS transistors in a one-to-one correspondence, the drains of the first MOS transistors are electrically connected to the read ends of the MTJ in a one-to-one correspondence, the drains of the second MOS transistors are electrically connected to the write ends of the MTJ in a one-to-one correspondence, the sources of the first MOS transistors and the second MOS transistors are electrically connected to the second test electrode, and the third end of the MTJ is electrically connected to the first test electrode.

Example 2

As shown in fig. 3, the testing structure tests a device group to be tested, the device group to be tested includes a plurality of parallel memory structures, the testing structure includes a first testing electrode, a second testing electrode, a plurality of first switches, a plurality of second switches, a plurality of first control electrodes and a plurality of second control electrodes, the memory structure is MTJ, the first switches are first MOS transistors, the second switches are second MOS transistors, the first control electrodes are electrically connected to the gates of the first MOS transistors in a one-to-one correspondence, the second control electrodes are electrically connected to the input ends of the encoder in a one-to-one correspondence, the output ends of the encoder are electrically connected to the gates of the second MOS transistors in a one-to-one correspondence, the input ends and the output ends of the encoder are in a one-to-one correspondence, the drains of the first MOS transistors are electrically connected to the read ends of the MTJ in a one-to one correspondence, the drains of the second MOS transistors are electrically connected to the write ends of the MTJ in a one-to one correspondence, the sources of the first MOS transistors and the second MOS transistors are electrically connected to the second testing electrodes, the third terminal of the MTJ is electrically connected to the first test electrode.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

in the test structure, when voltage is applied between the first test electrode and the second test electrode and the plurality of first switches are controlled to be switched on and the plurality of second switches are controlled to be switched off, reading operation can be performed on the plurality of resistance change devices, and when the first switches are controlled to be switched off and the second switches are controlled to be switched on, writing operation can be performed on the plurality of resistance change devices. The resistance testing method comprises the steps of controlling a first switch, a second switch, a first testing electrode and a second testing electrode in the testing structure, writing and reading a plurality of resistance changing devices in at least one device group to be tested for a plurality of times, testing the resistance values of the device group to be tested after writing and reading for a plurality of times, and subsequently determining the read-resistant times and the write-resistant times of each resistance changing device according to the testing resistance values. The test structure is controlled to simultaneously test the read-write resistant times of a plurality of resistive devices at one time, and compared with the test structure which can only test one resistive device at one time in the prior art, the test structure can greatly shorten the test time of the read-write resistant times of the resistive devices.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. The utility model provides a test structure, its characterized in that, test structure tests at least one device group that awaits measuring, and each device group that awaits measuring includes a plurality of parallelly connected resistance change device, each resistance change device includes first end, second end and third end, the first end of resistance change device is read end, the second end of resistance change device is write end, test structure includes:

a plurality of first switches, each of the first switches comprising a first end, a second end and a first control end, the first ends of the first switches being electrically connected to the read ends in a one-to-one correspondence;

the first ends of the second switches are electrically connected with the writing ends in a one-to-one correspondence manner;

the first testing electrodes are electrically connected with the third ends of the resistive devices in at least one device group to be tested respectively;

at least one second test electrode, each of the second test electrodes being electrically connected to a second end of each of the first switches and a second end of each of the second switches in at least one of the device groups under test, respectively,

the first switch, the second switch, the first test electrode and the second test electrode in the test structure are controlled, so that multiple writing and reading can be performed on a plurality of resistive devices in at least one device group to be tested, the resistance values of the device group to be tested after the multiple writing and reading are tested, and subsequently, the read-resistant times and the write-resistant times of each resistive device are determined according to the tested resistance values.

2. The test structure of claim 1, further comprising:

a plurality of first control electrodes, where the first control electrodes are electrically connected to the first control end of one of the first switches or to the first control ends of a plurality of the first switches, respectively, and the first control electrodes are used to control the switching states of the first switches, and under the condition that the first control electrodes are electrically connected to a plurality of the first switches, any two first switches electrically connected to one of the first control electrodes are electrically connected to the read ends in different sets of devices to be tested;

and under the condition that the second control electrode is electrically connected with a plurality of second switches, any two second switches electrically connected with one second control electrode are electrically connected with the writing ends in different device groups to be tested.

3. The test structure of claim 2, wherein there is one of the device under test sets, one of the first test electrodes and one of the second test electrodes, the first control electrodes being electrically connected to the first control terminals in a one-to-one correspondence, and the second control electrodes being electrically connected to the second control terminals in a one-to-one correspondence.

4. The test structure of claim 3, further comprising:

the switch matrix comprises a plurality of input interfaces, a plurality of output interfaces, at least one first power interface and at least one second power interface, the plurality of output interfaces comprise a first group of output interfaces, the first group of output interfaces comprise a plurality of output interfaces, the output interfaces of the first group of output interfaces are electrically connected with the first control electrodes in a one-to-one correspondence manner, the number of the output interfaces of the first group of output interfaces is greater than or equal to the number of the first control electrodes, the first power interfaces are electrically connected with the first test electrodes in a one-to-one correspondence manner, and the second power interfaces are electrically connected with the second test electrodes in a one-to-one correspondence manner;

and the voltage applying device comprises a plurality of voltage output terminals, and the voltage output terminals are electrically connected with the input interfaces in a one-to-one correspondence manner.

5. The test structure of claim 4, wherein the plurality of output interfaces further comprises a second group of output interfaces, the second group of output structures comprises a plurality of output interfaces, the output interfaces of the second group of output interfaces are electrically connected to the second control electrodes in a one-to-one correspondence, and the number of the output interfaces of the second group of output interfaces is greater than or equal to the number of the second control electrodes.

6. The test structure of claim 3, further comprising:

the encoder comprises a plurality of input ends and a plurality of output ends, the input ends correspond to the output ends one by one, the input ends are electrically connected with the first control electrodes or the second control electrodes, the output ends are electrically connected with the first control ends or the second control ends, the output ends corresponding to the input ends electrically connected with the first control electrodes are electrically connected with the first control ends, and the output ends corresponding to the input ends electrically connected with the second control electrodes are electrically connected with the second control ends.

7. The test structure of claim 6, wherein the plurality of input terminals comprises a plurality of first input terminals and second input terminals, and the plurality of output terminals comprises a plurality of first output terminals and second output terminals, the first input terminals being electrically connected to the first control electrodes in a one-to-one correspondence, the first output terminals being electrically connected to the first control terminals in a one-to-one correspondence, the second input terminals being electrically connected to the second control electrodes in a one-to-one correspondence, the second output terminals being electrically connected to the second control terminals in a one-to-one correspondence.

8. The test structure of any one of claims 1 to 7, wherein the first switch and the second switch are independently selected from an NMOS transistor, a PMOS transistor, a transmission gate, or a triode.

9. The test structure according to claim 1, characterized in that the resistive switching device comprises a spin orbit torque supply line and a resistive switching structure on the spin orbit torque supply line, preferably the resistive switching structure is an MTJ.

10. A test method, characterized in that it is carried out using a test structure according to any one of claims 1 to 9.

11. The test method of claim 10, wherein the test method comprises a endurance test procedure comprising:

a1, acquiring the initial resistance of an undamaged part in a device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently;

step a2, controlling the first switch corresponding to the damaged resistive switching device to be turned off and the second switch to be turned off, controlling the second switch corresponding to the undamaged portion to be turned on and the first switch to be turned off, and applying a first predetermined number of predetermined pulse signals between the first test electrode and the second test electrode;

step A3, controlling the first switch corresponding to the undamaged part to be switched on and the second switch to be switched off, applying voltage between the first test electrode and the second test electrode, and detecting the current resistance of the undamaged part;

step A4, repeating steps A2 and A3 for 1 times or more in sequence, stopping applying the pulse signal until the difference value between the detected resistance of the undamaged portion and the previously detected resistance is larger than a first preset threshold value, and recording the number of times of the currently applied pulse signal;

step a5, controlling the second switch corresponding to the undamaged portion to be turned off, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one first switch corresponding to the undamaged portion to be in an on state and the other first switches to be in an off state, detecting the resistance of each resistive switching device of the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device of the undamaged portion is smaller than a second predetermined threshold, and determining the number of times of writing endurance of the damaged resistive switching device according to the number of times of the pulse signal;

step a6, repeatedly executing the steps a1 to a5 until all the resistive devices in the device group to be tested are damaged, or until the number of times of applying the pulse signal is equal to a second predetermined number of times, wherein the second predetermined number of times is greater than the first predetermined number of times.

12. The testing method of claim 11, wherein said step a1 comprises:

sequentially controlling one first switch to be in a conducting state, and the other first switches to be in a switching-off state, detecting the resistance of each resistance change device, and determining that the resistance change device is damaged under the condition that the resistance of the resistance change device is smaller than a second preset threshold value;

and controlling the first switch corresponding to the damaged resistive switching device to be switched off, switching on the other first switches and switching off the second switches, applying voltage between the first test electrode and the second test electrode corresponding to one device group to be tested, and detecting the initial resistance of the undamaged part.

13. The test method of claim 10, wherein the test method comprises a read endurance test procedure comprising:

step C1, acquiring the initial resistance of the undamaged part in the device group to be tested, wherein each resistance change device of the undamaged part is in an undamaged state currently;

step C2, controlling the first switch corresponding to the damaged resistive switching device to be turned off and the second switch to be turned off, controlling the first switch corresponding to the undamaged portion to be turned on and the second switch to be turned off, and applying a predetermined pulse signal for a third predetermined number of times between the first test electrode and the second test electrode;

step C3, keeping the first switches corresponding to the undamaged portions turned on and the second switches turned off, applying a voltage between the first test electrode and the second test electrode, and detecting the current resistance of the undamaged portions;

step C4, repeating steps C2 and C3 for 1 or more times in sequence, stopping applying the pulse signal and recording the number of times of the pulse signal currently applied when the difference value between the detected resistance of the undamaged portion and the resistance detected last time is larger than a first predetermined threshold value;

step C5, controlling the second switch corresponding to the undamaged portion to be turned off, applying a voltage between the first test electrode and the second test electrode, sequentially controlling one first switch corresponding to the undamaged portion to be in an on state, and the other first switches to be in an off state, detecting the resistance of the resistive switching device of the undamaged portion, determining that the resistive switching device is damaged when the resistance of the resistive switching device of the undamaged portion is smaller than a second predetermined threshold value, and determining the read endurance number of the damaged resistive switching device according to the number of the pulse signals;

and step C6, sequentially and repeatedly executing the steps C1 to C5 at least once until all the resistive switching devices in the device group to be tested are damaged, or until the number of times of applying the pulse signal is equal to a fourth predetermined number of times, wherein the fourth predetermined number of times is greater than the third predetermined number of times.

14. The testing method of claim 13, wherein said step C1 comprises:

15. The method according to any one of claims 11 to 14, wherein the test structure further comprises a plurality of first control electrodes electrically connected to the first control terminal of one of the first switches and a plurality of second control electrodes electrically connected to the second control terminal of one of the second switches, and wherein in the test method, the first switches are controlled to be in an off or on state by controlling a voltage of the first control electrodes, and the second switches are controlled to be in an off or on state by controlling a voltage of the second control electrodes.