CN108133732B - Performance test method, device and equipment of flash memory chip and storage medium - Google Patents
Performance test method, device and equipment of flash memory chip and storage medium Download PDFInfo
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- CN108133732B CN108133732B CN201711384655.3A CN201711384655A CN108133732B CN 108133732 B CN108133732 B CN 108133732B CN 201711384655 A CN201711384655 A CN 201711384655A CN 108133732 B CN108133732 B CN 108133732B
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- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention discloses a performance test method, a performance test device, performance test equipment and a performance test storage medium of a flash memory chip. The method comprises the following steps: selecting a performance test sample of the flash memory chip based on a preset selection rule, and performing programming/erasing test on the flash memory chip according to the performance test sample; when the programming/erasing test is detected to be completed, performing a read interference test on the flash memory chip according to the performance test sample; and when the read interference test is detected to be completed, performing a data retention test on the flash memory chip according to the performance test sample. The technical scheme of the embodiment of the invention solves the problem that no unified flash memory performance test flow exists in the prior art, and realizes the effect of conveniently realizing the flash memory performance test.
Description
Technical Field
The embodiment of the invention relates to the technical field of memories, in particular to a performance testing method and device for a flash memory chip and a computer storage medium.
Background
Nand Flash is more and more favored by the storage industry because of its large capacity and fast rewriting speed. The internal structures of storage devices commonly used in the market, such as U disks, SSDs and the like, are all composed of Nand Flash memory particles and a controller. The firmware in the controller is closely tied to the flash granules used during the development process.
When developing a chip based on flash memory granules, the first process is usually to test some basic functions and characteristics of the flash memory granules, so as to make some targeted measures in the firmware development engineering. The research on Nand Flash requires the understanding of the influence of each parameter and the comprehensive influence of the parameters. Generally, technicians can test main characteristic parameters of Nand Flash memory particles, but currently, a unified test method and a standard flow do not exist.
Disclosure of Invention
The invention provides a performance test method and device of a flash memory chip and a computer storage medium, which are used for solving the problem that a unified flash memory performance test flow does not exist and can conveniently realize the test of the flash memory performance.
In a first aspect, an embodiment of the present invention provides a method for testing performance of a flash memory chip, where the method includes:
selecting a performance test sample of a flash memory chip based on a preset selection rule, and performing programming/erasing test on the flash memory chip according to the performance test sample;
when the programming/erasing test is detected to be completed, performing a read interference test on the flash memory chip according to the performance test sample;
and when the read interference test is detected to be completed, performing a data retention test on the flash memory chip according to the performance test sample.
Further, the selecting a performance test sample of the flash memory chip based on a preset selection rule includes:
acquiring storage blocks with the same number in each storage wing of a flash memory chip as a group of target storage block sets;
and acquiring at least two sets of target storage block sets with discontinuous numbers as performance test samples.
Further, the performing a program/erase test on the flash memory chip according to the performance test sample includes:
determining the corresponding relation between the target programming/erasing times of each group according to the preset target programming/erasing times of each group of target storage block set; the target program/erase times are different;
determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence;
the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process is different.
Further, the performing a read disturb test on the flash memory chip according to the performance test sample includes:
reading data in each memory block in the performance test sample;
when detecting that the data in each storage block in the performance test sample completes one read operation, confirming that the flash memory chip completes one read cycle;
if the number of times of the current reading cycle reaches a preset reading cycle threshold value, acquiring the number of the bit digits of the reading error, and recording;
and returning to execute the operation of reading the data in each storage block in the performance test sample until the current read cycle number reaches the preset highest read cycle number.
Further, the performing the data retention test on the flash memory chip according to the performance test sample includes:
and placing the performance test sample in an environment reaching a preset temperature, and recording the data retention time in the flash memory chip.
In a second aspect, an embodiment of the present invention further provides a device for testing performance of a flash memory chip, where the device includes:
the programming/erasing test module is used for selecting a performance test sample of the flash memory chip based on a preset selection rule and carrying out programming/erasing test on the flash memory chip according to the performance test sample;
the read interference test module is used for carrying out read interference test on the flash memory chip according to the performance test sample when detecting that the programming/erasing test is finished;
and the data retention test module is used for carrying out data retention test on the flash memory chip according to the performance test sample when the read interference test is detected to be completed.
Further, the program/erase test module is further configured to:
acquiring storage blocks with the same number in each storage wing of a flash memory chip as a group of target storage block sets;
and acquiring at least two sets of target storage block sets with discontinuous numbers as performance test samples.
Further, the program/erase test module is further configured to:
determining the corresponding relation between the target programming/erasing times of each group according to the preset target programming/erasing times of each group of target storage block set; the target program/erase times are different;
determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence;
the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process is different.
In a third aspect, an embodiment of the present invention further provides an apparatus, where the apparatus includes:
one or more processors;
a storage device for storing one or more programs,
when the one or more programs are executed by the one or more processors, the one or more processors implement the performance testing method of the flash memory chip according to any of the embodiments of the present invention.
In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the performance testing method for a flash memory chip according to any of the embodiments of the present invention.
According to the technical scheme of the embodiment of the invention, the performance test sample of the flash memory chip is selected according to the preset selection rule, the programming/erasing test is carried out on the test sample flash memory chip, when the programming/erasing test is finished, the read interference test is carried out on the test sample flash memory chip, and when the read interference test is detected to be finished, the data retention test is carried out on the test sample flash memory chip, so that the problems that no unified flash memory chip performance test flow exists in the prior art and the comprehensive performance of the chip cannot be judged are solved, the performance of the flash memory chip can be conveniently tested, and the performance of the chip can be comprehensively judged.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the technical solutions in the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flowchart illustrating a method for testing performance of a flash memory chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a performance testing apparatus for a flash memory chip according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of an apparatus according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart illustrating a method for testing performance of a flash memory chip according to an embodiment of the present invention, where the method is applicable to performance testing of the flash memory chip, the method can be executed by a performance device of the flash memory chip, and the system can be implemented in software and/or hardware.
As shown in fig. 1, the method of the embodiment may specifically include:
s110, selecting a performance test sample of the flash memory chip based on a preset selection rule, and performing programming/erasing test on the flash memory chip according to the performance test sample;
wherein, the selecting the performance test sample of the flash memory chip based on the preset selecting rule comprises: acquiring storage blocks with the same number in each storage wing of a flash memory chip as a group of target storage block sets; and acquiring at least two sets of target storage block sets with discontinuous numbers as performance test samples.
It should be noted that the chip is a packaged chip, and at least two die are included in one chip, where at least two memory wing planes are included in the die, and at least two blocks are included in the memory wing planes. In order to make the tested data result more representative, it is optional that the performance test samples of the flash memory chip are uniformly distributed during selection, so the preset selection rule in the embodiment of the present invention is as follows: firstly, acquiring each die of a flash memory chip, and then selecting a memory block with the same number from a memory wing plane in each die as a target memory block set; in order to further obtain the test sample block, at least two groups of blocks having different memory block numbers need to be obtained from the target memory block set as test samples, so that the samples can be divided into a plurality of groups.
TABLE 1
For example, the performance test samples of the flash memory chips may be selected according to table 1, where the hatched blocks in table 1 represent the performance test samples of the flash memory chips selected according to the preset rule, and it can also be seen from table 1 that at least one die in each flash memory chip, at least one plane in each die, and numbers block0 and block3 … in each plane are selected as the performance test samples of the flash memory chips. The sample selection mode of the embodiment of the invention can ensure that the selected blocks are uniformly distributed in the flash memory chip, so that the final test result is more representative.
Optionally, the performing a program/erase test on the flash memory chip according to the performance test sample includes: determining the corresponding relation between the target programming/erasing times of each group according to the preset target programming/erasing times of each group of target storage block set; the target program/erase times are different; determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence; the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process is different.
Before the program/erase test is performed, the obtained performance test samples of the flash memory chips are grouped, each group having 10 blocks. Illustratively, dividing the performance test samples of the flash memory chip into six groups; the program/erase times of the six groups of test samples are correspondingly set before the test; in order to obtain the performance of each group of flash memory chip samples under the condition of different program/erase times, different values are respectively set for the program/erase times of the six groups of samples, namely a first group of 500 times and a second group of 1000 times … sixth group of 3000 times, wherein the 500 times of the first group respectively represents that each memory block in the group is respectively programmed/erased 500 times, the 1000 times of the second group respectively represents that each memory block in the group is respectively programmed/erased 1000 times, and the program/erase times of each memory block in the sixth group is 3000 times.
TABLE 2
The specific number of program/erase times of the memory blocks in each group can be seen from table 2, and it can be seen from table 2 that the number of program/erase times of the test samples of each group of flash memories is increased by multiple, and it can be seen that the corresponding relationship of program/erase between each group is that the first group completes one program/erase, the second group completes two program/erase …, and the sixth group completes six program/erase. In order to avoid the influence on the test result of the performance test sample due to the different completion times, that is, the performance of the memory block is influenced, it is necessary to ensure that the tests of each group are completed as simultaneously as possible.
It should be noted that, by selecting the performance test sample of the flash memory chip according to the preset selection rule, the performance test sample in the selected flash memory chip needs to be subjected to the program/erase test. Optionally, an erase sequence may be determined according to the above-mentioned program/erase correspondence between each group, where an exemplary erase sequence is after once programming/erasing the first block of the first group, twice programming/erasing the first block of the second group, three times programming/erasing the first block of the third group, and so on until the most one group performs program/erase tests on the memory blocks in the performance test sample, until each memory block of the first group completes program/erase 500 times, each memory block of the second group completes program/erase 1000 times … times, each memory block of the sixth group completes program/erase 3000 times, and finally it is ensured that the program/erase tests of the sixth group are completed substantially simultaneously.
And after the first group of storage blocks are programmed/erased once, the second group of storage blocks are programmed/erased twice, the third group of storage blocks are programmed/erased three times, and the like, until the last group of storage blocks finish the corresponding programming/erasing times, taking the programming/erasing process as a programming cycle. And performing programming/erasing tests on each memory block in the performance test sample according to the programming cycle until the programming/erasing tests of all the groups are completed by preset programming/erasing times.
On this basis, during the program/erase test, the data that can be written into the memory blocks is random, and this arrangement has the advantage that all the memory blocks in the flash memory chip are in different threshold voltage ranges. In order to simulate the situation of the user in practical use to the maximum extent, the data written in different programming cycles in the same memory block are different from each other. Furthermore, the storage block includes a plurality of pages, and the data written in each page in the same storage block are different from each other.
S120, when the programming/erasing test is detected to be completed, performing a read interference test on the flash memory chip according to the performance test sample;
wherein, the performing the read disturb test on the flash memory chip according to the performance test sample comprises: reading data in each memory block in the performance test sample; when detecting that the data in each storage block in the performance test sample completes one read operation, confirming that the flash memory chip completes one read cycle; if the number of times of the current reading cycle reaches a preset reading cycle threshold value, acquiring the number of the bit digits of the reading error, and recording; and returning to execute the operation of reading the data in each storage block in the performance test sample until the current read cycle number reaches the preset highest read cycle number.
It should be noted that the read disturb is also a main parameter for evaluating the performance of the flash memory chip, and when it is detected that the program/erase test is completed, the read disturb test is performed on the test sample, specifically: the threshold for completing one read cycle is set in advance, illustratively 1000 times. And circularly reading the data in each storage block in the performance test sample, acquiring and recording a read error bit value in the cyclic reading process when the detected cycle times reach 1000 times, and indicating that the performance of the flash memory chip is better when the bit value is lower than a preset read error value. Reading is cycled until the current read cycle number reaches a preset maximum read cycle number, and reading is stopped, wherein the maximum read cycle number is 15000 times as an example.
And S130, when the read interference test is detected to be completed, performing a data retention test on the flash memory chip according to the performance test sample.
Specifically, the performing the data retention test on the flash memory chip according to the performance test sample may include: and placing the performance test sample in an environment reaching a preset temperature, and recording the data retention time in the flash memory chip.
The data retention test is mainly used for verifying the integrity of data in the flash memory chip during the use process of a user. However, due to the limit of the development cycle, it is impossible to test in the actual environment during the actual test, and the data retention time is usually tested by placing the performance test sample in a preset high-temperature environment. If the performance test specimen can be placed in an environment with a preset temperature of 125 ℃ for 15 hours, it corresponds to a period of time that the product can be used in an environment with a temperature of 60 ℃ for one year. For example, the preset temperature may be changed according to the actual requirement of the product to test the data retention time of the product. The data retention test results are closest to the actual use case according to the execution mode.
The embodiment of the invention selects the performance test sample of the flash memory chip according to the preset selection rule, performs the programming/erasing test on the test sample flash memory chip, performs the read interference test on the test sample flash memory chip when the programming/erasing test is completed, and performs the data retention test on the test sample flash memory chip when the read interference test is completed.
Example two
Fig. 2 is a schematic structural diagram of a performance testing apparatus for a flash memory chip according to a second embodiment of the present invention, the apparatus including: a program/erase test module 210, a read disturb test module 220, and a data retention test module 220.
The programming/erasing test module 210 is configured to select a performance test sample of a flash memory chip based on a preset selection rule, and perform a programming/erasing test on the flash memory chip according to the performance test sample; a read disturb test module 220, configured to perform a read disturb test on the flash memory chip according to the performance test sample when detecting that the program/erase test is completed; and the data retention test module 220 is configured to perform a data retention test on the flash memory chip according to the performance test sample when it is detected that the read disturb test is completed.
The embodiment of the invention selects the performance test sample of the flash memory chip according to the preset selection rule, performs the programming/erasing test on the test sample flash memory chip, performs the read interference test on the test sample flash memory chip when the programming/erasing test is completed, and performs the data retention test on the test sample flash memory chip when the read interference test is completed.
On the basis of the above technical solution, the program/erase test module 210 in the apparatus may also be configured to obtain the memory blocks with the same number in each memory wing of the flash memory chip as a group of target memory block sets; and acquiring at least two sets of target storage block sets with discontinuous numbers as performance test samples.
On the basis of the above technical solutions, the program/erase testing module 210 in the apparatus may further be configured to determine a corresponding relationship between each set of target program/erase times according to preset target program/erase times of each set of target storage block sets; the target program/erase times are different; determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence; the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process is different.
On the basis of the above technical solutions, the read disturb test module 220 in the apparatus is further configured to read data in each storage block in the performance test sample; when detecting that the data in each storage block in the performance test sample completes one read operation, confirming that the flash memory chip completes one read cycle; if the number of times of the current reading cycle reaches a preset reading cycle threshold value, acquiring the number of the bit digits of the reading error, and recording; and returning to execute the operation of reading the data in each storage block in the performance test sample until the current read cycle number reaches the preset highest read cycle number.
On the basis of the above technical solutions, the data retention test module 230 in the apparatus is further configured to place the performance test sample in an environment that reaches a preset temperature, and record the time for retaining data in the flash memory chip.
The device can execute the performance test method of the flash memory chip provided by any embodiment of the invention, and has the corresponding functional module and beneficial effect of executing the performance test method of the flash memory chip.
It should be noted that, the units and modules included in the apparatus are merely divided according to functional logic, but are not limited to the above division as long as the corresponding functions can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the embodiment of the invention.
EXAMPLE III
Fig. 3 is a schematic structural diagram of an apparatus according to a third embodiment of the present invention. Fig. 3 illustrates a block diagram of an exemplary device 30 suitable for use in implementing embodiments of the present invention. The device 30 shown in fig. 3 is only an example and should not bring any limitation to the function and scope of use of the embodiments of the present invention.
As shown in FIG. 3, device 30 is in the form of a general purpose computing device. The components of device 30 may include, but are not limited to: one or more processors or processing units 301, a system memory 302, and a bus 303 that couples various system components including the system memory 302 and the processing unit 301.
The system memory 302 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)304 and/or cache memory 305. The device 30 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 306 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 3, commonly referred to as a "hard drive"). Although not shown in FIG. 3, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 303 by one or more data media interfaces. Memory 302 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 308 having a set (at least one) of program modules 307 may be stored, for example, in memory 302, such program modules 307 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 307 generally perform the functions and/or methodologies of the described embodiments of the invention.
The processing unit 301 executes various functional applications and data processing by running programs stored in the system memory 302, for example, implementing a performance test method for a flash memory chip provided by an embodiment of the present invention.
Example four
The fourth embodiment of the present invention further provides a storage medium containing computer-executable instructions, which are used to perform a performance testing method of a flash memory chip when executed by a computer processor.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for embodiments of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (4)
1. A performance test method of a flash memory chip is characterized by comprising the following steps:
selecting a performance test sample of a flash memory chip based on a preset selection rule, and performing programming/erasing test on the flash memory chip according to the performance test sample;
when the programming/erasing test is detected to be completed, performing a read interference test on the flash memory chip according to the performance test sample;
when the read interference test is detected to be completed, performing a data retention test on the flash memory chip according to the performance test sample;
the selecting of the performance test sample of the flash memory chip based on the preset selecting rule comprises the following steps: acquiring storage blocks with the same number in each storage wing of a flash memory chip as a group of target storage block sets; acquiring at least two groups of target storage block sets with discontinuous serial numbers as performance test samples;
the performing a program/erase test on the flash memory chip according to the performance test pattern includes:
determining the corresponding relation between the target programming/erasing times of each group according to the preset target programming/erasing times of each group of target storage block set; the target program/erase times of the groups are different;
determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence;
the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process are different;
the performing a read disturb test on the flash memory chip according to the performance test sample includes:
reading data in each memory block in the performance test sample;
when detecting that the data in each storage block in the performance test sample completes one read operation, confirming that the flash memory chip completes one read cycle;
if the number of times of the current reading cycle reaches a preset reading cycle threshold value, acquiring the number of the bit digits of the reading error, and recording;
returning to execute the operation of reading the data in each storage block in the performance test sample until the current read cycle number reaches the preset highest read cycle number;
the performing the data retention test on the flash memory chip according to the performance test sample comprises:
and placing the performance test sample in an environment reaching a preset temperature, and recording the data retention time in the flash memory chip.
2. A performance testing apparatus for a flash memory chip, comprising:
the programming/erasing test module is used for selecting a performance test sample of the flash memory chip based on a preset selection rule and carrying out programming/erasing test on the flash memory chip according to the performance test sample;
the read interference test module is used for carrying out read interference test on the flash memory chip according to the performance test sample when detecting that the programming/erasing test is finished;
the data retention test module is used for carrying out data retention test on the flash memory chip according to the performance test sample when the read interference test is detected to be completed;
the program/erase test module is further to:
acquiring storage blocks with the same number in each storage wing of a flash memory chip as a group of target storage block sets;
acquiring at least two groups of target storage block sets with discontinuous serial numbers as performance test samples;
the data retention test module is also used for placing the performance test sample in an environment reaching a preset temperature and recording the data retention time in the flash memory chip;
the program/erase test module is further to:
determining the corresponding relation between the target programming/erasing times of each group according to the preset target programming/erasing times of each group of target storage block set; the target program/erase times of the groups are different;
determining the erasing sequence of each storage block according to the corresponding relation, and performing programming/erasing test on the flash memory chip according to the erasing sequence;
the data written in each programming/erasing process in different memory blocks are different, and the data written in the same memory block in each programming/erasing process are different;
the read disturb test module in the apparatus is further to:
reading data in each memory block in the performance test sample; when detecting that the data in each storage block in the performance test sample completes one read operation, confirming that the flash memory chip completes one read cycle;
if the number of times of the current reading cycle reaches a preset reading cycle threshold value, acquiring the number of the bit digits of the reading error, and recording; and returning to execute the operation of reading the data in each storage block in the performance test sample until the current read cycle number reaches the preset highest read cycle number.
3. An electronic device, characterized in that the device comprises:
one or more processors;
a storage device for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the method for performance testing of a flash memory chip of claim 1.
4. A storage medium containing computer-executable instructions for performing the method of testing the performance of a flash memory chip of claim 1 when executed by a computer processor.
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| CN108958655B (en) * | 2018-06-26 | 2021-08-10 | 郑州云海信息技术有限公司 | Data erasing method, device, equipment and storage medium of solid state disk |
| CN109461469A (en) * | 2018-10-30 | 2019-03-12 | 新华三技术有限公司 | A kind of test method and device |
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| CN102543216B (en) * | 2010-12-29 | 2015-07-29 | 中芯国际集成电路制造(北京)有限公司 | A kind of method of testing of flash memory |
| CN104237766B (en) * | 2013-06-24 | 2017-06-20 | 上海东软载波微电子有限公司 | Chip detecting method and device |
| CN105469834B (en) * | 2014-09-12 | 2018-08-24 | 上海华虹宏力半导体制造有限公司 | The test method of embedded flash memory |
| CN105006253B (en) * | 2015-08-11 | 2018-10-16 | 上海华虹宏力半导体制造有限公司 | A kind of flash memory chip data retention inspection method and system |
| CN107481764B (en) * | 2017-07-31 | 2020-06-12 | 深圳芯邦科技股份有限公司 | 3D Nand Flash scanning detection method and system |
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