CN111899782A - Test method, test device, electronic equipment and storage medium - Google Patents

Test method, test device, electronic equipment and storage medium Download PDF

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Publication number
CN111899782A
CN111899782A CN201910368824.7A CN201910368824A CN111899782A CN 111899782 A CN111899782 A CN 111899782A CN 201910368824 A CN201910368824 A CN 201910368824A CN 111899782 A CN111899782 A CN 111899782A
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Prior art keywords
test
value
cycle value
storage block
storage
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冯颖俏
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Shanghai Geyi Electronic Co ltd
GigaDevice Semiconductor Beijing Inc
Beijing Zhaoyi Innovation Technology Co Ltd
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Shanghai Geyi Electronic Co ltd
Beijing Zhaoyi Innovation Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0405—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals comprising complete test loop

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Abstract

The embodiment of the invention discloses a test method, a test device, electronic equipment and a storage medium, wherein the method comprises the following steps: determining test storage blocks corresponding to the test cycle values with different gradients, and enabling the test storage blocks corresponding to the test cycle values with different gradients to be uniformly distributed in a storage space of the flash memory; and carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously. By adopting the technical scheme, the purpose that the test storage blocks corresponding to different gradient test cycle values simultaneously complete test operation is achieved, the problem of unstable storage data caused by data retention is avoided, and the test effect is improved.

Description

Test method, test device, electronic equipment and storage medium
Technical Field
The embodiment of the invention relates to the technical field of flash memories, in particular to a testing method, a testing device, electronic equipment and a storage medium.
Background
The EMMC (Embedded Multi Media Card) is established by the MMC association, mainly aims at the standard specification of an Embedded memory of products such as a mobile phone or a tablet computer, and consists of an Embedded memory solution, and is provided with an MMC multimedia interface, a flash memory (such as nand flash) and an EMMC controller. More and more mobile devices employ an EMMC chip as a memory cell.
The PEC (Program Erase Cycle) test of the EMMC means that after Erase-Program cycles are performed for a set number of times on a memory block of a nand flash, data stored in the memory block is read, and the read data is compared with original Program data to determine error bit information, which is very important for analyzing the performance of the nand flash. In order to improve the testing effect, when performing the PEC test, the test sample should cover the entire memory area of nand as much as possible, and multiple sets of test cycle values with different gradients are usually set in one PEC test, where each set of test cycle values corresponds to the same number of different test memory blocks.
In the prior art, a test is usually performed from a test memory block arranged at the head, after the erase-program loop test of the test memory block arranged at the head is completed for a set number of times, a next test memory block is tested until all the test memory blocks are sequentially completed for the respective set number of times, then a read operation is performed on data stored in the test memory block, and the read data is compared with original program data to determine error bit information. It can be seen that the above test scheme has the following problems: when the last test storage block finishes testing, the data stored in the last test storage block is newer, and the data stored in the test storage block arranged in the front is older, and when the read data is compared with the original programming data on the basis of the fact, the influence of data retention on the data stored in the test storage block is adulterated, so that the read data is inaccurate, and the obtained comparison result is also inaccurate, so that the test effect is influenced.
Disclosure of Invention
Embodiments of the present invention provide a testing method, an apparatus, an electronic device, and a storage medium, which reduce a time difference between tests of all test storage blocks of a flash memory and improve a testing effect.
In a first aspect, an embodiment of the present invention provides a testing method, where the method includes:
determining test storage blocks corresponding to the test cycle values with different gradients, and enabling the test storage blocks corresponding to the test cycle values with different gradients to be uniformly distributed in a storage space of the flash memory;
and carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously.
In a second aspect, an embodiment of the present invention provides a testing apparatus, including:
the determining module is used for determining the test storage blocks corresponding to the test cycle values with different gradients so that the test storage blocks corresponding to the test cycle values with different gradients are uniformly distributed in the storage space of the flash memory;
and the test module is used for carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish the test of all the test storage blocks at the same time.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the testing method according to any one of claims 1 to 6 when executing the computer program.
In a fourth aspect, embodiments of the present invention provide a storage medium containing computer-executable instructions which, when executed by a computer processor, implement a test method as claimed in any one of claims 1 to 6.
According to the test method provided by the embodiment of the invention, after the test storage blocks corresponding to the test cycle values with different gradients are determined, the test storage blocks are tested based on the test cycle values of the test storage blocks, so that the purpose that the test storage blocks corresponding to the test cycle values with different gradients complete the test operation at the same time is achieved, the problem of unstable stored data caused by data retention is avoided, and the test effect is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the contents of the embodiments of the present invention and the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a memory cell array according to an embodiment of the invention;
fig. 2 is a schematic flow chart of a testing method according to an embodiment of the present invention;
fig. 3 is a schematic flow chart of a testing method according to a second embodiment of the present invention;
FIG. 4 is a schematic flow chart of another testing method according to a second embodiment of the present invention;
FIG. 5 is a flowchart illustrating another testing method according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of a testing apparatus according to a third embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The storage units of the flash memory are connected by word lines and bit lines to form storage pages, a plurality of storage pages form storage blocks, and finally a plurality of storage blocks form a storage unit array. Referring to the schematic structural diagram of a memory cell array shown in fig. 1, the size and number of the memory blocks are determined by the size of the flash memory space. For convenience of description of the storage blocks in the following, the storage blocks of the flash memory are numbered sequentially in this embodiment, and are denoted as storage block No. 1, storage block No. 2, and storage block No. 3 … … sequentially from top to bottom (or from bottom to top).
Example one
Fig. 2 is a schematic flow chart of a testing method according to an embodiment of the present invention. The testing method disclosed in the present embodiment may be performed by a testing apparatus, wherein the apparatus may be implemented by software and/or hardware, and is generally integrated in a chip, such as an EMMC chip. Referring specifically to fig. 2, the method includes the steps of:
step 210, determining the test storage blocks corresponding to the test cycle values with different gradients, so that the test storage blocks corresponding to the test cycle values with different gradients are uniformly distributed in the storage space of the flash memory.
Generally, when a PEC test is performed, a plurality of groups of test cycle values with different gradients are set, each group of test cycle values corresponds to the same number of different test storage blocks, the test storage blocks should cover the whole storage space of the flash memory as much as possible, and the test storage blocks corresponding to the test cycle values with different gradients should be uniformly distributed in the storage space of the flash memory, so as to realize the overall test of each storage space of the flash memory and ensure that the flash memory passing the test has better storage performance.
For example, the determining the test storage blocks corresponding to the test cycle values with different gradients to uniformly distribute the test storage blocks corresponding to the test cycle values with different gradients in the storage space of the flash memory includes:
determining the memory blocks marked as m x (N + N-1) as the test memory blocks corresponding to the test cycle value of the nth gradient;
wherein m is a preset constant and is not equal to 0, N is a positive integer, N is 0, Nmax、2nmax、3nmax……，nmaxIs the maximum value of n.
The above procedure for determining the test memory blocks corresponding to the test cycle values of different gradients is illustrated:
assume that 6 sets of test cycle values of different gradients are set in one PEC test, the test cycle value of the 1 st gradient is 1000, the test cycle value of the 2 nd gradient is 2000, the test cycle value of the 3 rd gradient is 3000, the test cycle value of the 4 th gradient is 4000, the test cycle value of the 5 th gradient is 5000, and the test cycle value of the 6 th gradient is 6000. I.e. the maximum value of n is 6, nmaxWith 6, the possible values of N are integer multiples of 6, i.e. 0, 6, 12, 18, 24 … …. Setting m to 15, and when N is 1, determining the memory block labeled 15 × N as the test memory block corresponding to the test cycle value 1000 of the 1 st gradient, that is, determining the memory blocks labeled 0, 90, 180, … …, and 15 × N as the test memory block corresponding to the test cycle value 1000 of the 1 st gradient. When N is 2, the memory block labeled 15 × N +1 is determined as the test memory block corresponding to the test cycle value 2000 of the 2 nd gradient, that is, the memory blocks labeled 15, 105, 195, … …, and 15 × N +1 are determined as the test memory blocks corresponding to the test cycle value 2000 of the 2 nd gradient. When N is 3, the memory block denoted by 15 × (N +2) is determined as the test memory block corresponding to the test cycle value 3000 of the 3 rd gradient, that is, the memory blocks denoted by 30, 120, 210, … …, and 15 × (N +2) are determined as the test memory blocks corresponding to the test cycle value 3000 of the 3 rd gradient. According to the rule, a test storage block corresponding to the test cycle value 4000 of the 4 th gradient, a test storage block corresponding to the test cycle value 5000 of the 5 th gradient and a test storage block corresponding to the test cycle value 6000 of the 6 th gradient are respectively determined. See table 1 for the labels of the test memory blocks corresponding to the test cycle values of the gradients.
Table 1: label of test storage block corresponding to test cycle value of each gradient
Testing labels of memory blocks Testing cycle value
0、90、……、15*N 1000
15、105、……、15*(N+1) 2000
30、120、……、15*(N+2) 3000
45、135、……、15*(N+3) 4000
60、150、……、15*(N+4) 5000
75、165、……、15*(N+5) 6000
According to the determination method, the test storage blocks corresponding to the test cycle values with different gradients can be uniformly distributed in the storage space of the flash memory.
And step 220, performing test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously.
Specifically, continuing with the above example, assume that 6 sets of test cycle values with different gradients are set in a PEC test, the test cycle value of the 1 st gradient is 1000, the test cycle value of the 2 nd gradient is 2000, the test cycle value of the 3 rd gradient is 3000, the test cycle value of the 4 th gradient is 4000, the test cycle value of the 5 th gradient is 5000, and the test cycle value of the 6 th gradient is 6000. The method comprises the steps of carrying out one test operation on a test storage block with a test cycle value of 1000 in a set time period, carrying out two test operations on a test storage block with a test cycle value of 2000, carrying out three test operations on a test storage block with a test cycle value of 3000, carrying out four test operations on a test storage block with a test cycle value of 4000, carrying out five test operations on a test storage block with a test cycle value of 5000, and carrying out six test operations on a test storage block with a test cycle value of 6000, so as to ensure that the test storage blocks corresponding to different test cycle values in the same time period have consistent test operation ratios, thus ensuring that the test storage blocks corresponding to different gradient test cycle values can be tested at the same time, avoiding the influence caused by data retention due to large time difference of completing the test of each test storage block, and improving the test effect. It should be noted that "simultaneously" herein refers to the same time period, and not to the same time, for example, the test memory blocks corresponding to the test cycle values of different gradients all complete the test operation between 10:00 o 'clock and 10:01 o' clock of a certain day.
According to the test method provided by the embodiment, after the test storage blocks corresponding to the test cycle values with different gradients are determined, the test storage blocks are tested based on the test cycle values of the test storage blocks, so that the purpose that the test storage blocks corresponding to the test cycle values with different gradients complete the test operation at the same time is achieved, the problem of unstable storage data caused by data retention is avoided, and the test effect is improved.
Example two
Fig. 3 is a schematic flow chart of a testing method according to a second embodiment of the present invention. On the basis of the foregoing embodiment, this embodiment provides an implementation manner of the foregoing step 220 "performing a test operation on each test storage block based on a test cycle value of each test storage block, so that all test storage blocks are tested at the same time", and specifically referring to fig. 3, the method includes the following steps:
and 310, determining the test storage blocks corresponding to the test cycle values with different gradients, so that the test storage blocks corresponding to the test cycle values with different gradients are uniformly distributed in the storage space of the flash memory.
And step 320, setting a test variable, wherein the test variable is used for recording the total times of the test operation on each test storage block.
Step 330, determining a target test storage block currently performing test operation based on the value of the test variable, and performing a test operation on the target test storage block.
Specifically, referring to the flow chart of another testing method shown in fig. 4, when the test cycle values of the different gradients are: 1000. 2000, 3000, 4000, 5000, and 6000, the determining a target test storage block currently performing a test operation based on a value of a test variable, and performing a test operation on the target test storage block, including:
and step 410, judging whether the value of the test variable is less than 6001, when the value of the test variable is less than 6001, continuing to execute step 420, otherwise, ending the process.
Step 420, determining whether the value of the test variable and the remainder of 6 are equal to 0, if the value of the test variable and the remainder of 6 are equal to 0, continuing to execute step 430, otherwise, executing step 460.
And 430, determining the test storage block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000 as the target test storage block, and continuing to execute the step 440.
Step 440, performing a test operation on the test memory block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000, and continuing to execute step 450.
And step 450, increasing the value of the test variable by 1, and returning to execute the step 410.
Step 460, determining whether the value of the test variable and the remainder of 3 are equal to 0, if the value of the test variable and the remainder of 3 are equal to 0, continuing to execute step 470, otherwise, executing step 490.
Step 470, determining the test storage block with the test cycle value of 2000, the test cycle value of 5000, and the test cycle value of 6000 as the target test storage block, and continuing to execute step 480.
Step 480, performing a test operation on the test memory block with the test cycle value of 2000, the test cycle value of 5000 and the test cycle value of 6000, and continuing to execute step 450.
Step 490, determine whether the value of the test variable and the result of 2's remainder are equal to 0, if the value of the test variable and the result of 2's remainder are equal to 0, continue to execute step 4100, otherwise execute step 4120.
Step 4100, determining the test storage block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000 as the target test storage block, and continuing to execute step 4110.
4110, performing a test operation on the test memory block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000, and continuing to execute step 450.
Step 4120, determining the test memory block with the test cycle value of 6000 as the target test memory block, and continuing to execute step 4130.
Step 4130, performing a test operation on the test memory block with the test cycle value of 6000, and continuing to execute step 450.
According to the above-mentioned step 410-4130, when the value of the test variable increases from 1 to 6, the case where the value of the test variable and the left result of 6 are equal to 0 occurs 1 time, the case where the value of the test variable and the left result of 3 are equal to 0 occurs 2 times, the case where the value of the test variable and the left result of 2 are equal to 0 occurs 3 times, and therefore, when the value of the test variable increases from 1 to 6, the test operation is performed 1 time on the test memory block with the test cycle value of 1000, the test operation is performed 2 times on the test memory block with the test cycle value of 2000, the test operation is performed 3 times on the test memory block with the test cycle value of 3000, the test operation is performed 4 times on the test memory block with the test cycle value of 4000, the test operation is performed 5 times on the test memory block with the test cycle value of 5000, and the test operation is performed 6 times on the test memory block with the test cycle value of 6000, the consistency of the test operation proportion of the test storage blocks corresponding to different test cycle values in the same time period is realized, and the test storage blocks are 1/1000. And continuing to circulate according to the method, and when the value of the test variable is equal to 6000, simultaneously completing the test operation on the test storage blocks corresponding to the test circulation values of all gradients.
The above-described test method can also be illustrated by means of a flow chart shown in fig. 5, which, with reference to fig. 5, comprises the following steps:
step 510, determining whether the value of the test variable iCnt is less than 6001, if so, executing step 520, otherwise, ending the process.
And 520, judging whether the value of the test variable iCnt and the remainder result of 6 are 0, if so, executing the step 530, and otherwise, executing the step 550.
Step 530, a test operation is performed on the test memory block with the test cycle value of 1000 and the test cycle value of 4000, and step 540 is continuously performed.
And 540, carrying out one-time test operation on the test storage block with the test cycle value of 6000, increasing the value of the test variable iCnt by 1, and returning to 510.
Step 550, determining whether the value of the test variable iCnt and the remainder of 3 are 0, if yes, performing step 560, otherwise, performing step 570.
And step 560, performing a test operation on the test memory block with the test cycle value of 2000 and the test cycle value of 5000, and returning to execute step 540.
Step 570, determine whether the value of the test variable iCnt and the remainder of 2 are 0, if yes, go to step 580, otherwise go to step 540.
And 580, performing a test operation on the test memory block with the test cycle value of 3000, the test cycle value of 4000 and the test cycle value of 5000, and returning to execute 540.
The essence of performing one test operation on the test storage block is as follows: an "erase-program" cycle is performed once on the test memory block, the erase operation being performed on the test memory block by applying an erase voltage to the control gate of the test memory block, and the program operation being performed on the test memory block by applying a program voltage to the control gate of the test memory block.
According to the testing method provided by the embodiment, the values of the testing variables and the results of the remainder of 6, 3 and 2 are respectively used as the judgment conditions, so that the testing operation of each testing storage block is realized based on the testing cycle value of each testing storage block, all the testing storage blocks are tested simultaneously, the problem of unstable storage data caused by data retention is avoided, and the testing effect is improved.
EXAMPLE III
Fig. 6 is a schematic structural diagram of a testing apparatus according to a third embodiment of the present invention. Referring to fig. 6, the apparatus includes: a determination module 610 and a test module 620;
the determining module 610 is configured to determine test storage blocks corresponding to test cycle values with different gradients, so that the test storage blocks corresponding to the test cycle values with different gradients are uniformly distributed in a storage space of the flash memory;
the test module 620 is configured to perform a test operation on each test storage block based on the test cycle value of each test storage block, so that all the test storage blocks are tested at the same time.
Further, the determining module 610 is specifically configured to:
determining the memory blocks marked as m x (N + N-1) as the test memory blocks corresponding to the test cycle value of the nth gradient;
wherein m is a preset constant and is not equal to 0, N is a positive integer, N is 0, Nmax、2nmax、3nmax……，nmaxIs the maximum value of n.
Further, the testing module 620 includes:
the device comprises a setting unit, a storage unit and a control unit, wherein the setting unit is used for setting a test variable, and the test variable is used for recording the total times of test operation on each test storage block;
and the test unit is used for determining a target test storage block currently subjected to test operation based on the value of the test variable and carrying out one-time test operation on the target test storage block.
Further, when the test cycle values of the different gradients are: 1000. 2000, 3000, 4000, 5000 and 6000, the test unit is specifically configured to:
judging whether the value of the test variable and the residue taking result of 6 are equal to 0 or not;
if the value of the test variable and the remainder result of 6 are equal to 0, determining the test storage block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000;
if the values of the test variables and the residue taking result of 6 are not equal to 0, judging whether the values of the test variables and the residue taking result of 3 are equal to 0 or not;
if the value of the test variable and the remainder result of 3 are equal to 0, determining the test storage block with the test cycle value of 2000, the test cycle value of 5000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 2000, the test cycle value of 5000 and the test cycle value of 6000;
if the values of the test variables and the residue taking result of 3 are not equal to 0, judging whether the values of the test variables and the residue taking result of 2 are equal to 0 or not;
if the remainder of the values of the test variables and the 2 is equal to 0, determining the test storage block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000;
if the value of the test variable and the remainder result of 2 are not equal to 0, determining the test storage block with the test cycle value of 6000 as the target test storage block;
and carrying out one test operation on the test storage block with the test cycle value of 6000.
Further, the test unit is further configured to increase the value of the test variable by 1 after performing a test operation on the target test storage block.
Further, the test unit is further configured to determine whether the value of the test variable is less than 6001 before determining whether the remainder result of the value of the test variable and 6 is equal to 0;
and when the value of the test variable is less than 6001, continuing to execute the operation of judging whether the remainder result of the value of the test variable and 6 is equal to 0.
The test device provided by the embodiment tests the storage blocks through the test cycle values based on the test storage blocks after determining the test storage blocks corresponding to the test cycle values with different gradients, so that the test storage blocks corresponding to the test cycle values with different gradients can complete the test operation at the same time, the problem of unstable storage data caused by data retention is avoided, and the test effect is improved.
The test device provided by the embodiment of the invention can execute the test method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in the above embodiments, reference may be made to the test methods provided in any of the embodiments of the present invention.
Example four
Fig. 7 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention. FIG. 7 illustrates a block diagram of an exemplary electronic device 12 suitable for use in implementing embodiments of the present invention. The electronic device 12 shown in fig. 7 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiment of the present invention.
As shown in FIG. 7, electronic device 12 is embodied in the form of a general purpose computing device. The components of electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 and the processing unit 16.
Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) bus, micro-channel architecture (MAC) bus, enhanced ISA bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.
Electronic device 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by electronic device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. The electronic device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 7, and commonly referred to as a "hard drive"). Although not shown in FIG. 7, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. Memory 28 may include at least one program product having a set of program modules (e.g., a test device determination module 610 and a test module 620) configured to perform the functions of embodiments of the present invention.
A program/utility 40 having a set (e.g., a test device determination module 610 and a test device 620) of program modules 42 may be stored, for example, in memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may include an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
Electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), with one or more devices that enable a user to interact with electronic device 12, and/or with any devices (e.g., network card, modem, etc.) that enable electronic device 12 to communicate with one or more other computing devices. Such communication may be through an input/output (I/O) interface 22. Also, the electronic device 12 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the Internet) via the network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 via the bus 18. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.
The processing unit 16 executes various functional applications and data processing by executing programs stored in the system memory 28, for example, to implement the test method provided by the embodiment of the present invention, the method includes:
determining test storage blocks corresponding to the test cycle values with different gradients, and enabling the test storage blocks corresponding to the test cycle values with different gradients to be uniformly distributed in a storage space of the flash memory;
and carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously.
The processing unit 16 executes various functional applications and data processing, such as implementing the test methods provided by embodiments of the present invention, by running programs stored in the system memory 28.
Of course, those skilled in the art will understand that the processor may also implement the technical solution of the testing method provided by any embodiment of the present invention.
EXAMPLE five
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a testing method provided in an embodiment of the present invention, where the method includes:
determining test storage blocks corresponding to the test cycle values with different gradients, and enabling the test storage blocks corresponding to the test cycle values with different gradients to be uniformly distributed in a storage space of the flash memory;
and carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously.
Of course, the computer program stored on the computer-readable storage medium provided by the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the test method provided by any embodiments of the present invention.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. A method of testing, comprising:
determining test storage blocks corresponding to the test cycle values with different gradients, and enabling the test storage blocks corresponding to the test cycle values with different gradients to be uniformly distributed in a storage space of the flash memory;
and carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish testing all the test storage blocks simultaneously.
2. The method of claim 1, wherein determining the test memory blocks corresponding to the test cycle values with different gradients so that the test memory blocks corresponding to the test cycle values with different gradients are uniformly distributed in a memory space of the flash memory comprises:
determining the memory blocks marked as m x (N + N-1) as the test memory blocks corresponding to the test cycle value of the nth gradient;
wherein m is a preset constant and is not equal to 0, N is a positive integer, N is 0, Nmax、2nmax、3nmax……，nmaxIs the maximum value of n.
3. The method of claim 1, wherein performing a test operation on each test memory block based on the test cycle value of each test memory block so that all test memory blocks are tested simultaneously comprises:
setting a test variable, wherein the test variable is used for recording the total times of test operation on each test storage block;
and determining a target test storage block currently subjected to test operation based on the value of the test variable, and carrying out one-time test operation on the target test storage block.
4. A method according to claim 3, characterized in that when the test cycle values of the different gradients are respectively: 1000. 2000, 3000, 4000, 5000, and 6000, the determining a target test storage block currently performing a test operation based on a value of a test variable, and performing a test operation on the target test storage block, including:
judging whether the value of the test variable and the residue taking result of 6 are equal to 0 or not;
if the value of the test variable and the remainder result of 6 are equal to 0, determining the test storage block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 1000, the test cycle value of 4000 and the test cycle value of 6000;
if the values of the test variables and the residue taking result of 6 are not equal to 0, judging whether the values of the test variables and the residue taking result of 3 are equal to 0 or not;
if the value of the test variable and the remainder result of 3 are equal to 0, determining the test storage block with the test cycle value of 2000, the test cycle value of 5000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 2000, the test cycle value of 5000 and the test cycle value of 6000;
if the values of the test variables and the residue taking result of 3 are not equal to 0, judging whether the values of the test variables and the residue taking result of 2 are equal to 0 or not;
if the remainder of the values of the test variables and the 2 is equal to 0, determining the test storage block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000 as the target test storage block;
carrying out one-time test operation on the test storage block with the test cycle value of 3000, the test cycle value of 4000, the test cycle value of 5000 and the test cycle value of 6000;
if the value of the test variable and the remainder result of 2 are not equal to 0, determining the test storage block with the test cycle value of 6000 as the target test storage block;
and carrying out one test operation on the test storage block with the test cycle value of 6000.
5. The method of claim 3 or 4, wherein after performing a test operation on the target test memory block, the method further comprises: increasing the value of the test variable by 1.
6. The method of claim 5, wherein before determining whether the remainder of the test variable value and 6 equals 0, the method further comprises:
judging whether the value of the test variable is less than 6001;
and when the value of the test variable is less than 6001, continuing to execute the operation of judging whether the remainder result of the value of the test variable and 6 is equal to 0.
7. A test apparatus, the apparatus comprising:
the determining module is used for determining the test storage blocks corresponding to the test cycle values with different gradients so that the test storage blocks corresponding to the test cycle values with different gradients are uniformly distributed in the storage space of the flash memory;
and the test module is used for carrying out test operation on each test storage block based on the test cycle value of each test storage block so as to finish the test of all the test storage blocks at the same time.
8. The apparatus of claim 7, wherein the determining module is specifically configured to:
determining the memory blocks marked as m x (N + N-1) as the test memory blocks corresponding to the test cycle value of the nth gradient;
wherein m is a preset constant and is not equal to 0, N is a positive integer, N is 0, Nmax、2nmax、3nmax……，nmaxIs the maximum value of n.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the testing method according to any of claims 1-6 when executing the computer program.
10. A storage medium containing computer-executable instructions which, when executed by a computer processor, implement the testing method of any one of claims 1-6.
CN201910368824.7A 2019-05-05 2019-05-05 Test method, test device, electronic equipment and storage medium Pending CN111899782A (en)

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JPH1164193A (en) * 1997-08-13 1999-03-05 Japan Tobacco Inc Fatigue testing machine
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CN108133732A (en) * 2017-12-20 2018-06-08 北京京存技术有限公司 Performance test methods, device, equipment and the storage medium of flash chip

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JPH1164193A (en) * 1997-08-13 1999-03-05 Japan Tobacco Inc Fatigue testing machine
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CN108133732A (en) * 2017-12-20 2018-06-08 北京京存技术有限公司 Performance test methods, device, equipment and the storage medium of flash chip

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