CN114550809A

CN114550809A - Multi-memory card testing method and device, computer equipment and storage medium

Info

Publication number: CN114550809A
Application number: CN202210068159.1A
Authority: CN
Inventors: 赖振楠; 王嗣钧
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-05-27

Abstract

The application belongs to the technical field of storage, and relates to a method and a device for testing multiple memory cards, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring a write-in command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write-in command carries the data and the number; analyzing the write-in command, obtaining the data and the number, and writing the data into the multi-memory card according to the number; and reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for XOR operation, and judging whether the multi-memory cards are normal or not according to the XOR operation result. By the adoption of the method, the plurality of storage cards are numbered, data are written into the plurality of storage cards simultaneously, manpower is not needed, testing of the storage cards can be automatically executed, cost is saved, testing efficiency can be improved, testing is reliable and easy to achieve, and the method can be universally applied to testing of the storage cards.

Description

Multi-memory card testing method and device, computer equipment and storage medium

Technical Field

The present application relates to the field of storage technologies, and in particular, to a method and an apparatus for testing multiple memory cards, a computer device, and a storage medium.

Background

With the development of information processing technology, the demand for storage devices has increased significantly. Small-sized memory devices, such as memory cards, are widely used due to their advantages of portability, high data storage capacity, and easy access. Based on the increase of the demand of the memory card, the importance of the memory card test process is relatively increased before the memory card is produced, and the efficiency and compatibility of the memory card are further ensured. Therefore, low cost and high performance memory card testing is an important issue for system manufacturers and designers.

When a memory card is tested, a tester needs to manually and gradually process the test to ensure the efficiency of the memory card. For example, each memory card is manually inserted or removed by a tester to perform the test. In the testing process, various testing devices are required to ensure the performance and compatibility of the memory card. It can be seen that the conventional memory card testing procedure is not only time-consuming but also expensive. In the prior art, the principle of testing a memory card is to write the same data into a plurality of memory cards, then read the data, and verify the coincidence degree of the read data and the written data, so as to operate the memory card.

This test operation has several features: firstly, the data volume is relatively large, for example, when the storage device to be tested is a storage card, if the capacity of the storage card is 256GB, the test data is 256 GB; if the storage device to be tested is a hard disk, if the capacity of the hard disk is 2T, the test data is 2T; and secondly, the data to be tested are written into a plurality of storage devices to be tested from a host (computer). Write-read-data compare; then write-erase block-read-data compare. Generally, such a test procedure is repeated several times to test the stability of the stored data of the memory device. It can be seen that the testing process is very lengthy and inefficient.

Disclosure of Invention

An embodiment of the application aims to provide a multi-memory card testing method, a multi-memory card testing device, computer equipment and a storage medium, so as to solve the problems that a multi-memory card testing process is very long and the efficiency is low in the prior art.

In order to solve the above technical problem, the present application provides a method for testing a multi-memory card, which adopts the following technical scheme, including the following steps:

acquiring a write command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write command comprises the data and the number;

analyzing the write-in command, obtaining the data and the number, and writing the data into the multi-memory card according to the number;

and reading the data from every two multi-memory cards with different numbers, storing the read data into a comparison circuit for XOR operation, and judging whether the two multi-memory cards with different numbers are normal or not according to the result of the XOR operation.

Further, before the step of obtaining a write command for writing data and a number of the multi-memory card into the multi-memory card, the step of carrying the data and the number further includes:

the rule of the write command is set.

Further, the step of analyzing the write command to obtain the data and the number, and writing the data into the multi-memory card according to the number specifically includes:

analyzing the write-in command to obtain the data and the serial number;

caching the obtained data into a cache region;

and writing the data in the buffer area into the multi-memory card according to the number.

Further, the step of reading the data from every two different-number multi-memory cards, placing the read data into a comparison circuit for xor operation, and judging whether the multi-memory cards are normal according to the xor operation result specifically includes:

grouping every two memory cards according to the number of the multiple memory cards;

reading the data from every two multi-memory cards with different numbers, and putting the read data into a comparison circuit for XOR operation;

if the XOR operation result is 0, the two multi-memory cards with different numbers are judged to be normal, and if the XOR operation result is 1, one of the two multi-memory cards with different numbers is judged to be abnormal;

and identifying the group of the abnormal multi-memory cards, and performing exclusive-OR operation on each multi-memory card in the group of the abnormal multi-memory cards and the detected normal multi-memory cards until the normal and abnormal conditions of all the multi-memory cards are detected.

Further, the rule for setting the write command includes:

the first byte of the set write command represents the number of the multi-memory card.

Further, after the step of reading the data from every two different numbers of the multi-memory cards, placing the read data into a comparison circuit for xor operation, and judging whether the multi-memory cards are normal according to the xor operation result, the method further comprises:

and displaying the abnormal multi-memory card number.

In order to solve the above technical problem, the present application further provides a testing apparatus for multiple memory cards, which adopts the following technical solution, including:

the device comprises an acquisition module, a storage module and a processing module, wherein the acquisition module is used for acquiring a write-in command for writing data and the serial number of the multi-memory card into the multi-memory card, and the write-in command carries the data and the serial number;

the writing module is used for analyzing the writing command, obtaining the data and the number, and writing the data into the multi-memory card according to the number;

and the judging module is used for reading the data from every two multi-memory cards with different numbers, putting the read data into the comparison circuit for XOR operation, and judging whether the multi-memory cards are normal or not according to the XOR operation result.

Further, the write module includes:

the analysis module is used for analyzing the write-in command to obtain the data and the serial number;

the cache module is used for caching the data into a cache region SRAM;

and the output module is used for writing the data into the multi-memory card according to the number by the cache region SRAM.

In order to solve the above technical problem, the present application further provides a computer device, which adopts the following technical solution, and includes a memory and a processor, where the memory stores computer-readable instructions, and the processor executes the computer-readable instructions to implement the steps of the method for testing the multi-memory card.

In order to solve the above technical problem, the present application further provides a computer-readable storage medium, which stores computer-readable instructions, and when the computer-readable instructions are executed by a processor, the steps of the method for testing a multi-memory card are implemented.

Compared with the prior art, the application mainly has the following beneficial effects: through numbering many storage cards, write in a plurality of many storage cards with data simultaneously, need not to rely on the manpower, can automize the test of execution storage card, save the cost and can promote efficiency of software testing, the test is reliable and easily realize, but the universal suitability is in the test of storage card.

Drawings

In order to more clearly illustrate the solution of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below, and it is obvious that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained by those skilled in the art without inventive effort.

FIG. 1 is an exemplary system architecture diagram in which the present application may be applied;

FIG. 2 is a flow diagram of one embodiment of a method for testing multiple memory cards of the present application;

FIG. 3 is a schematic diagram of testing of multiple memory cards in the prior art;

FIG. 4 is a timing diagram illustrating the transmission of test data for multiple memory cards according to the prior art;

FIG. 5 is a timing diagram of test data transmission for the multi-memory card of the present application;

FIG. 6 is a schematic diagram of one embodiment of the present application for writing data to multiple memory cards simultaneously;

FIG. 7 is a schematic diagram of another embodiment of the present application for writing data to multiple memory cards simultaneously;

FIG. 8 is an eight bit XOR circuit diagram of the present application;

FIG. 9 is a logic circuit diagram of the present application;

FIG. 10 is a schematic block diagram of one embodiment of a multi-memory card testing apparatus of the present application;

FIG. 11 is a block diagram illustrating one embodiment of a write module of FIG. 10;

FIG. 12 is a block diagram of one embodiment of a computer device of the present application.

In the figure, an A-NOR gate, a B-NAND gate and a C-NOR gate are arranged.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

As shown in fig. 1, the system architecture 100 may include a first terminal device 101, a second terminal device 102, a third terminal device 103, a network 104, and a server 105. The network 104 is used to provide a medium of communication links between the first terminal device 101, the second terminal device 102, the third terminal device 103 and the server 105. Network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, to name a few.

The user may use the first terminal device 101, the second terminal device 102, the third terminal device 103 to interact with the server 105 via the network 104 to receive or send messages or the like. Various communication client applications, such as a web browser application, a shopping application, a search application, an instant messaging tool, a mailbox client, social platform software, and the like, may be installed on the first terminal device 101, the second terminal device 102, and the third terminal device 103.

The first terminal device 101, the second terminal device 102, and the third terminal device 103 may be various electronic devices having a display screen and supporting web browsing, including but not limited to a smart phone, a tablet computer, an E-book reader, an MP3 player (testing persgroup Audio Layer III of Moving Picture E multi-memory card, mpeg compression standard Audio Layer 3), an MP4 player (testing persgroup Audio Layer IV of Moving Picture E multi-memory card, mpeg compression standard Audio Layer 4), a laptop computer, a desktop computer, and the like.

The server 105 may be a server that provides various services, such as a background server that provides support for pages displayed on the first terminal apparatus 101, the second terminal apparatus 102, and the third terminal apparatus 103.

It should be noted that the testing method for the multi-memory card provided in the embodiments of the present application is generally executed by the server/terminal device, and accordingly, the testing apparatus for the multi-memory card is generally disposed in the server/terminal device.

It should be understood that the number of terminal devices, networks, and servers in fig. 1 is merely illustrative. There may be any number of terminal devices, networks, and servers, as desired for implementation.

Example one

With continued reference to FIG. 2, a flow diagram of one embodiment of a method for testing a multi-memory card of the present application is shown. The testing method of the multi-memory card comprises the following steps:

step S201, a write command for writing data and a number of a multi-memory card into the multi-memory card is acquired, where the write command includes the data and the number.

Fig. 3 is a schematic diagram of testing of a prior art multi-memory card. As shown in fig. 3, in the prior art, a test system for testing multiple memory cards generally includes a terminal, a USB hub, and multiple memory cards. One end of the USB concentrator is a USB interface, and the other end of the USB concentrator can be a plurality of interfaces. The plurality of interfaces may be the same or different. The plurality of interfaces may include a SATA interface, a USB interface, a Type-C interface, and the like. And the multi-memory card is connected through interfaces such as an SATA interface, a USB interface and a Type-C interface. During the testing process, the tester is required to manually insert or remove each memory card, such as multi-memory card 1, multi-memory card 2, multi-memory card 3, and multi-memory card 4, to perform the testing. It is clear that the test is time-consuming and laborious.

Fig. 4 is a timing diagram of test data transmission of a multi-memory card in the related art. As shown in fig. 4, the same data is written from the terminal to the plurality of memory cards, and the data is composed of W1, W2, W3 and W4; time T1 data W1 is written to the card 1, time T2 data W2 is written to the card 1, time T3 data W3 is written to the card 1, and time T4 data W4 is written to the card 1. It can be seen that data storage is done serially.

In some optional implementations of this embodiment, before obtaining a write command for writing data and a number of a multi-memory card into the multi-memory card in step S201, where the write command includes the data and the number, the electronic device may further perform the following steps: the rule of the write command is set.

For example, the rule for setting the write command includes: the first byte of the set write command represents the number of the multi-memory card. Of course, the number of bytes representing the number of the multi-memory card can also be defined according to actual needs and the number of the multi-memory cards to be tested. Here, the number of numbered bytes of the multi-memory card is not limited.

In the application, the multiple memory cards are numbered, and the number information is written into the multiple memory cards, so that the tracking test is conveniently carried out.

In this embodiment, the electronic device (for example, the server/terminal device shown in fig. 1) on which the test method of the multi-memory card operates may receive the test request of the multi-memory card through a wired connection manner or a wireless connection manner. It should be noted that the wireless connection means may include, but is not limited to, a 3G/4G/5G connection, a WiFi connection, a bluetooth connection, a test connection of a wimax multi-memory card, a Zigbee connection, a uwb (ultra wideband) connection, and other wireless connection means now known or developed in the future.

Step S202, the writing command is analyzed to obtain the data and the number, and the data is written into the multi-memory card according to the number.

In some optional implementation manners of this embodiment, the analyzing the write command to obtain the data and the number, and the writing the data into the multi-memory card according to the number specifically includes:

analyzing the write-in command to obtain the data and the serial number;

caching the obtained data into a cache region;

Fig. 5 is a test data transfer timing chart of the multi-memory card of the present application. As shown in fig. 5, data W1, W2, W3, and W4 may be simultaneously written into memory card 1 within one time T1, and the control circuit (main control) may also write data W1, W2, W3, and W4 into memory card 2 or/and memory card 3 or/and memory card 4 within time T1. The numbers of the memory card 1, the memory card 2, the memory card 3, the memory card 4, and the like are obtained by analyzing the write command. Before writing data W1, W2, W3 and W4 into memory card 2 or/and memory card 3 or/and memory card 4 within time T1, data W1, W2, W3 and W4 may be buffered in a buffer area. A data output buffer is provided for temporarily storing data during writing and reserving a certain space in the memory area. I.e. the storage space of the main memory is used to temporarily store the information outputted from the disk. The purpose is to mitigate the speed mismatch conflict between the CPU and the I/O device. The interruption frequency of the CPU is reduced, and the limitation on the interruption response time of the CPU is relaxed. The parallelism between the CPU and the I/O device is improved. It can be seen that with the present embodiment, data storage is performed in parallel, which can save time.

FIG. 6 is a schematic diagram of an embodiment of the present application for writing data to multiple memory cards simultaneously. As shown in fig. 6, the terminal issues an instruction for writing data into each memory card, the CPU executes the instruction, and the data of the CPU control terminal (host side) is cached in the cache SRAM. The main control is the main control of the testing device, the main control is welded on a PCB, one end of the PCB is provided with an interface connected with the end of a host computer, and the other end of the PCB is provided with a clamping groove for inserting a plurality of storage cards so as to realize the card connection to the testing board.

Specifically, when the test is started, the CPU in the master writes the data W1, W2, W3, and W4 on the host side into the buffer area, and then writes the data W1, W2, W3, and W4 in the buffer area into each card, thereby realizing the simultaneous writing of the data into each card.

Step S203, reading the data from each two multi-memory cards with different numbers, storing the read data in a comparison circuit for xor operation, and determining whether the two multi-memory cards with different numbers are normal according to the result of the xor operation.

In some optional implementation manners of this embodiment, the reading the data from every two different-number multi-memory cards, placing the read data into the comparison circuit for performing an exclusive-or operation, and determining whether the multi-memory cards are normal according to an exclusive-or operation result specifically includes:

if the XOR operation result is 0, judging that the two multi-memory cards with different numbers are normal, and if the XOR operation result is 1, judging that one card of the two multi-memory cards with different numbers is abnormal;

The embodiment of the present application further claims to simultaneously read data in each card, so as to determine whether the data can be read and accurately read (compared with data written by a host, the data has no error). The performance of individual cards can be tested based on the data being able to be read and accurately read.

Fig. 7 is a schematic diagram of another embodiment of the present application for writing data to multiple memory cards simultaneously. As shown in fig. 7, based on this, the master control according to the embodiment of the present application further includes a comparison circuit, more specifically, an exclusive or circuit. Because the same data is written into each card, the CPU in the main control controls the reading of data from every two cards, and the read data is put into the comparison circuit for exclusive OR operation. The same data in the two cards is expressed in binary '0' and '1', the data are subjected to exclusive-or operation by an exclusive-or circuit, if the two cards are OK, the data read from the two cards are subjected to exclusive-or operation, and the result of the exclusive-or operation is '0'; if one of the two cards is NG (Not Good, Failed), the result of the xor operation is "1".

Specifically, since data is read from the memory card in a byte-by-byte manner, the data comparison, i.e., the exclusive or operation, is a byte-by-byte comparison, and the memory card reads and writes data in a byte-by-byte manner.

Further, since the data is composed of a plurality of bytes, the comparison circuit, or xor circuit, is actually a byte xor accumulation circuit, and the data is continuous, and xor operation byte by byte is actually an accumulation logic. The hardware for accumulation may be a register.

Specifically, if the result of one byte xor operation is "1", it indicates that the test result of one card is NG, and the test result of the memory card can be known.

Illustratively, in fig. 7, there are 4 cards, the data in the card 1 and the card 2 are xor-ed, the data in the card 3 and the card 4 are xor-ed, if the result of xor-ing the data in the card 1 and the card 2 is "0", and the result of xor-ing the data in the card 3 and the card 4 is "1", this indicates that at least one of the card 3 and the card 4 is NG, and xor-operates the data in the card 1 and the card 3 or xor-operates the data in the card 1 and the card 4; either the data in

cards

2 and 3 are xored or the data in cards 2 and 4 are xored. Thus, it is possible to test NG in all cards, or all cards.

The exclusive or of A and B is equivalent to the exclusive or negation of A and B, i.e.

And transforming to obtain the logic algebraic expression.

The corresponding logic circuit consists of two NOR gates and an AND gate. For 8-bit binary comparison, 8 groups of logic circuits are connected in series.

And the corresponding single cmos exclusive-or gate circuit consists of a stage of NOR gate and a stage of NOR gate. For inputs A and B, they are first obtained via a NOR gate

And obtaining the exclusive or output of A and B through an AND NOR gate.

Truth table:

A	B	NOR gate output	And nor gate output
				0	0	1	0
0	1	0	1
				1	0	0	1
1	1	0	0

The process of testing the memory card is as follows: external data is firstly input into a BULK FIFO of an SRAM for waiting processing through a multi-interface such as a USB interface, 2k or other data, namely partial input, is required once according to data of the SRAM1235, then the FIFO data is subjected to coding and decoding operation according to the read-write requirement (the SRAM needs to be transmitted to an exclusive-or circuit data, w/r) of the SRAM1235, the operation is finished and then returned to the SRAM, and the data is stored into the USB or other operations again according to the requirement. Each write data overwrites the previous SRAM FIFO data.

Data alignment illustrates:

10011100001100010101111010110111 (mother card 32-bit binary data);

9 c 315 e b 7(32 bit 16 ary);

10011100001100110101110010110111 (daughter card 32 bit binary data);

9 c 335 c b 7(16 ary);

it can be seen that the 4 th and 6 th 8bit bits are in error.

And (3) performing exclusive or comparison:

00000000000000100000001000000000 (2 ary);

00020200 (16 ary).

Fig. 8 is an 8-bit exclusive or circuit diagram of the present application. As shown in fig. 8, two devices, NMOS and PMOS, are mainly included. The source S of the PMOS1 is connected to the drain D of the PMOS2, the sources of the PMOS2 are connected to the drains D, NMOS 1D of the gates G, NMOS2 of the gates G, NMOS3 of the PMOS5, and the PMOS1, the PMOS2, the NMOS1, and the NMOS2 form a nor gate a. PMOS3, PMOS4, NMOS4 and NMOS5 form or NAND gate B. The drain D of the PMOS3 is connected to the drain D of the PMOS4, the gate of the PMOS4 is connected to the gate of the NMOS4, the source of the NMOS4 is connected to the drain of the NMOS5, and the drain of the NMOS4 is connected to the source of the PMOS5 and the drain of the NMOS3, respectively. PMOS5 and NMOS3 form nor C. The source of PMOS5 is connected to the drain of NMOS 3. And the NMOS is conducted when the G is very high level (1), and the source and the drain are conducted when the grid is very low level in the PMOS. The working principle is as follows: nor gate part for inputs a, b, the output is high only if a, b are both 1 (high). Nand gates have outputs a, b that are 0 (low) only if both a, b are 1. The not gate negates the input.

NAND gates are connected in series with corresponding logic algebraic expressions:

and the output value is inverted (not gate) and then is connected with the NAND gates of the A and the B (correspondingly connected in series).

Fig. 9 is a logic circuit diagram of the present application. As shown in FIG. 9, refer to the algebraic expression

And the A and B phases are performed, and the output value and the NOR value of the A and B are performed with NOR operation.

In some optional implementation manners of this embodiment, in step S203, reading the data from every two multi-memory cards with different numbers, storing the read data into the comparison circuit for performing an exclusive-or operation, and after determining whether the two multi-memory cards with different numbers are normal according to a result of the exclusive-or operation, the method may further include the steps of: and displaying the abnormal multi-memory card number. Through setting up the display interface, show that there is unusual many storage cards serial number, convenience of customers learns like this which many storage cards need retest or need carry out maintenance etc. and convenience of customers carries out the quality to having unusual many storage cards and follows up.

Through numbering many storage cards, write in a plurality of many storage cards with data simultaneously, need not to rely on the manpower, can automize the test of execution storage card, save the cost and can promote efficiency of software testing, the test is reliable and easily realize, but the universal suitability is in the test of storage card.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware associated with computer readable instructions, which can be stored in a computer readable storage medium, and when executed, the processes of the embodiments of the methods described above can be included. The storage medium may be a non-volatile storage medium such as a magnetic disk, an optical disk, a Read-Only Memory (ROM), or a Random Access Memory (RAM).

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Example two

With further reference to fig. 10, as an implementation of the method shown in fig. 2, the present application provides an embodiment of a multi-memory card testing apparatus, which corresponds to the method shown in fig. 2 and can be applied to various electronic devices.

As shown in fig. 10, the multi-memory card test apparatus 400 according to the present embodiment includes: an obtaining module 401, a writing module 402 and a judging module 403. Wherein:

an obtaining module 401, configured to obtain a write command for writing data and a number of a multi-memory card into the multi-memory card, where the write command includes the data and the number;

a write module 402, configured to parse the write command, obtain the data and the number, and write the data into the multi-memory card according to the number;

the determining module 403 is configured to read the data from each two different-numbered multi-memory cards, store the read data in the comparing circuit for xor operation, and determine whether the two different-numbered multi-memory cards are normal according to the result of the xor operation.

Referring to fig. 11, which is a schematic structural diagram of a specific embodiment of the write module 402, the write module 402 further includes a parsing module 4021, a caching module 4022, and an output module 4023. Wherein the content of the first and second substances,

the analyzing module 4021 is configured to analyze the write command to obtain the data and the serial number;

the cache module 4022 is configured to cache the obtained data in a cache region;

the output module 4023 is configured to write the data in the buffer into the multi-memory card according to the number.

By arranging the cache module, the contradiction of speed mismatch between the CPU and the I/O equipment is alleviated. The interruption frequency of the CPU is reduced, the limitation on the interruption response time of the CPU is relaxed, and the integrity of the written data is protected.

EXAMPLE III

In order to solve the technical problem, an embodiment of the present application further provides a computer device. Referring to fig. 12, fig. 12 is a block diagram of a basic structure of a computer device according to the present embodiment.

The computer device 6 comprises a memory 61, a processor 62, a network interface 63 communicatively connected to each other via a system bus. It is noted that only the computer device 6 having the component memory 61, the processor 62 and the network interface 63 is shown, but it is understood that not all of the shown components are required to be implemented, and that more or fewer components may be implemented instead. As will be understood by those skilled in the art, the computer device is a device capable of automatically performing numerical calculation and/or information processing according to a preset or stored instruction, and the hardware includes, but is not limited to, a microprocessor, an Application Specific Integrated Circuit (ASIC), a Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), an embedded device, and the like.

The computer device can be a desktop computer, a notebook, a palm computer, a cloud server and other computing devices. The computer equipment can carry out man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch panel or voice control equipment and the like.

The memory 61 includes at least one type of readable storage medium including a flash memory, a hard disk, a multi-memory card, a card-type memory (e.g., a test memory of an SD or D multi-memory card, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a Programmable Read Only Memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 61 may be an internal storage unit of the computer device 6, such as a hard disk or a memory of the computer device 6. In other embodiments, the memory 61 may also be an external storage device of the computer device 6, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the computer device 6. Of course, the memory 61 may also comprise both an internal storage unit of the computer device 6 and an external storage device thereof. In this embodiment, the memory 61 is generally used for storing an operating system installed in the computer device 6 and various types of application software, such as computer readable instructions of a test method of a multi-memory card. Further, the memory 61 may also be used to temporarily store various types of data that have been output or are to be output.

The processor 62 may be a Central Processing Unit (CPU), controller, microcontroller, microprocessor, or other data Processing chip in some embodiments. The processor 62 is typically used to control the overall operation of the computer device 6. In this embodiment, the processor 62 is configured to execute computer-readable instructions stored in the memory 61 or process data, such as computer-readable instructions for executing the testing method of the multi-memory card.

The network interface 63 may comprise a wireless network interface or a wired network interface, and the network interface 63 is typically used for establishing a communication connection between the computer device 6 and other electronic devices.

Through numbering many storage cards, write into a plurality of many storage cards with data simultaneously, do not need to rely on the manpower, can the automatic test of carrying out the storage card, save the cost and can promote efficiency of software testing, the test is reliable and easily realize, but the universal relevance is in the test of storage card.

Example four

The present application further provides another embodiment, which is to provide a computer-readable storage medium storing computer-readable instructions executable by at least one processor to cause the at least one processor to perform the steps of the method for testing a multi-memory card as described above.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.

It is to be understood that the above-described embodiments are merely illustrative of some, but not restrictive, of the broad invention, and that the appended drawings illustrate preferred embodiments of the invention and do not limit the scope of the invention. This application is capable of embodiments in many different forms and is provided for the purpose of enabling a thorough understanding of the disclosure of the application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that the present application may be practiced without modification or with equivalents of some of the features described in the foregoing embodiments. All equivalent structures made by using the contents of the specification and the drawings of the present application are directly or indirectly applied to other related technical fields and are within the protection scope of the present application.

Claims

1. A method for testing a multi-memory card, comprising the steps of:

acquiring a write-in command for writing data and the number of the multi-memory card into the multi-memory card, wherein the write-in command comprises the data and the number;

2. The method for testing a multi-memory card according to claim 1, wherein before the step of obtaining a write command for writing data and a number of a multi-memory card into a multi-memory card, the write command carrying the data and the number, further comprises:

the rule of the write command is set.

3. The method for testing a multi-memory card according to claim 1, wherein the step of parsing the write command to obtain the data and the number, and writing the data into the multi-memory card according to the number specifically comprises:

analyzing the write-in command to obtain the data and the serial number;

caching the obtained data into a cache region;

4. The method for testing a multi-memory card of claim 1, wherein the steps of reading the data from every two multi-memory cards with different numbers, placing the read data into a comparison circuit for xor operation, and determining whether the multi-memory cards are normal according to the xor operation result specifically include:

5. The method for testing a multi-memory card according to claim 2, wherein the rule for setting the write command includes:

6. The method for testing a multi-memory card according to any one of claims 1 to 5, wherein after the steps of reading the data from every two multi-memory cards with different numbers, putting the read data into a comparison circuit for exclusive-or operation, and judging whether the multi-memory cards are normal according to the exclusive-or operation result, the method further comprises:

and displaying the abnormal multi-memory card number.

7. A multi-memory card testing apparatus, comprising:

the device comprises an acquisition module, a storage module and a processing module, wherein the acquisition module is used for acquiring a write-in command for writing data and the serial number of the multi-memory card into the multi-memory card, and the write-in command comprises the data and the serial number;

and the judging module is used for reading the data from every two multi-memory cards with different numbers, storing the read data into the comparison circuit for XOR operation, and judging whether the two multi-memory cards with different numbers are normal or not according to the result of the XOR operation.

8. The apparatus for testing a multi-memory card according to claim 7, wherein the writing module comprises:

the cache module is used for caching the obtained data into a cache region;

and the output module is used for writing the data in the buffer area into the multi-memory card according to the serial number.

9. A computer device comprising a memory having computer readable instructions stored therein and a processor which when executed implements the steps of the method of testing a multi-memory card of any of claims 1 to 6.

10. A computer-readable storage medium having computer-readable instructions stored thereon which, when executed by a processor, implement the steps of the method for testing a multi-memory card of any one of claims 1 to 6.