CN114822675A

CN114822675A - Memory detection method and device, electronic equipment and storage medium

Info

Publication number: CN114822675A
Application number: CN202210411571.9A
Authority: CN
Inventors: 第五天昊
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-04-19
Filing date: 2022-04-19
Publication date: 2022-07-29

Abstract

The disclosure relates to a memory detection method and device, electronic equipment and a computer readable storage medium, relates to the technical field of semiconductors, and can be applied to a scene of read-write detection of a memory. The method comprises the following steps: acquiring test data and a memory to be detected, wherein the memory is in a flexible read-write switching mode; determining burst length, data writing initial address and data reading initial address corresponding to each read-write mode; writing test data into a memory based on the burst length and the data writing start address to obtain writing data; reading write data from a memory based on the burst length and the data reading start address to obtain corresponding read data; and determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine a detection result of the memory according to the data comparison result. The method and the device can accurately detect whether the memory has read-write problems according to the conversion among a plurality of read-write modes.

Description

Memory detection method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory detection method, a memory detection apparatus, an electronic device, and a computer-readable storage medium.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor Memory, and the main function principle is to represent whether a binary bit (bit) is 1 or 0 by the amount of charge stored in a capacitor.

With the continuous popularization of intelligent terminals, the application range of the DRAM is wider and wider, for example, in terminals such as mobile phones and computers used by people in daily life; moreover, with the upgrading and upgrading of products, the precision level adopted by the memory manufacturing process is smaller and smaller, the speed is faster and faster, the capacity is larger and larger, and the research and development and test processes of DRAM products become more and more important.

It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a memory detection method, a memory detection apparatus, an electronic device, and a computer-readable storage medium, so as to overcome at least to some extent the problems of the existing DRAM detection scheme, such as long test time, high cost, and inability to accurately detect a partial data read error.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the invention.

According to a first aspect of the present disclosure, there is provided a memory detection method, including: the method comprises the steps that test data and a memory to be detected are obtained, wherein the memory is in a flexible read-write switching mode, and the flexible read-write switching mode comprises multiple different read-write modes; determining burst length, data writing initial address and data reading initial address corresponding to each read-write mode; writing the test data into a memory based on the burst length and the data write start address to obtain write data; reading the written data from the memory based on the burst length and the data reading start address to obtain corresponding read data; and determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine a detection result of the memory according to the data comparison result.

In an exemplary embodiment of the present disclosure, a mode register corresponding to the memory is determined, and a current configuration parameter of the mode register is obtained; and if the current configuration parameter is not in the read-write flexible switching mode, performing configuration updating operation on the current configuration parameter so as to enable the memory to be in the read-write flexible switching mode.

In an exemplary embodiment of the present disclosure, each of the read/write modes in the read/write flexible switching mode may be switched to another, and each of the read/write modes corresponds to a different burst length.

In an exemplary embodiment of the present disclosure, the read-write mode is a first read-write mode, and the first read-write mode corresponds to a first burst length and a first write start address; writing the test data into a memory based on the burst length and the data write start address to obtain write data, comprising: generating a first writing rule corresponding to the first reading and writing mode based on the first burst length and the first writing starting address; and writing the test data into the memory according to the first writing rule to obtain first writing data.

In an exemplary embodiment of the present disclosure, the first read-write mode corresponds to a first read start address; reading the write data from the memory based on the burst length and the data read start address to obtain corresponding read data, including: generating a first reading rule corresponding to the first reading and writing mode based on the first burst length and the first reading starting address; and reading the first written data from the memory according to the first reading rule to obtain corresponding first read data.

In an exemplary embodiment of the present disclosure, the read/write mode is a second read/write mode, and the second read/write mode corresponds to a second burst length and a second write start address; writing the test data into a memory according to the data writing rule to obtain written data, including: generating a second write rule corresponding to the second read-write mode based on the second burst length and the second write start address; and writing the test data into the memory according to the second writing rule to obtain second writing data.

In an exemplary embodiment of the present disclosure, reading the write data from the memory based on the burst length and the data read start address to obtain corresponding read data includes: acquiring a generated first reading rule, and determining a first burst length corresponding to the first reading rule; and reading the second write data from the memory according to the first burst length to obtain corresponding second read data.

In an exemplary embodiment of the present disclosure, the reading and writing mode is a second reading and writing mode, reading the written data from the memory based on the burst length and the data reading start address to obtain corresponding read data, including: acquiring a second burst length corresponding to the second read-write mode; determining a plurality of second read starting addresses corresponding to the second read-write mode; the second read start address is determined based on a bit line jump address; and reading the second write data from the memory according to the second burst length and each second read start address to obtain a plurality of corresponding third read data.

In an exemplary embodiment of the present disclosure, determining a data comparison result between the write data and the read data corresponding to each of the read-write modes includes: determining a burst type corresponding to the read-write mode and a first data arrangement mode corresponding to the burst type; and carrying out consistency comparison on the written data and the read data according to the first data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, consistency comparison of the write data and the read data according to the first data arrangement to obtain the data comparison result includes: performing consistency comparison on the first written data and the first read data according to the first data arrangement mode to obtain a first comparison result; performing consistency comparison on second written data and second read data according to the first data arrangement mode to obtain a second comparison result; and performing consistency comparison on the second written data and the third read data according to the first data arrangement mode to obtain a third comparison result.

In an exemplary embodiment of the present disclosure, the above method further comprises: determining a read bit line characteristic value corresponding to a first read mode, and acquiring a second data arrangement mode corresponding to the read bit line characteristic value; reading the second written data from the memory by adopting a first reading mode based on the read bit line characteristic value to obtain fourth read data; and performing consistency comparison on the second written data and the fourth read data according to the second data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, the read-write mode includes a diagonal read-write mode, and the method further includes: obtaining a word line and bit line arrangement structure corresponding to the memory, and determining a position point to be written according to the word line and bit line arrangement structure; the position point to be written has a diagonal-like characteristic; writing the test data into the memory according to the position point to be written and the diagonal writing mode to obtain diagonal writing data; reading the diagonal write-in data from the memory to obtain corresponding diagonal read-out data; and carrying out consistency comparison on the diagonal writing data and the diagonal reading data to obtain a diagonal data comparison result.

In an exemplary embodiment of the present disclosure, determining the detection result of the memory according to the data comparison result includes: if the data comparison result indicates that the written data is consistent with the read data, the detection result indicates that the memory has no read-write problem; and if the data comparison result indicates that the written data is inconsistent with the read data, the detection result indicates that the memory has a read-write problem.

According to a second aspect of the present disclosure, there is provided a memory detection apparatus comprising: the device comprises a memory acquisition module, a test data acquisition module and a memory to be detected, wherein the memory is in a read-write flexible switching mode, and the read-write flexible switching mode comprises a plurality of different read-write modes; a rule generating module, configured to determine a burst length, a data writing start address, and a data reading start address corresponding to each read-write mode; a data writing module, configured to write the test data into a memory based on the burst length and the data writing start address to obtain write data; a data reading module, configured to read the write data from the memory based on the burst length and the data reading start address to obtain corresponding read data; and the result determining module is used for determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine the detection result of the memory according to the data comparison result.

In an exemplary embodiment of the present disclosure, the memory detection apparatus further includes a mode configuration module, configured to determine a mode register corresponding to the memory, and obtain a current configuration parameter of the mode register; and if the current configuration parameter is not in the read-write flexible switching mode, performing configuration updating operation on the current configuration parameter so as to enable the memory to be in the read-write flexible switching mode.

In an exemplary embodiment of the present disclosure, the read-write mode is a first read-write mode, and the first read-write mode corresponds to a first burst length and a first write start address; the data writing module comprises a first data writing unit and a second data writing unit, wherein the first data writing unit is used for generating a first writing rule corresponding to the first reading and writing mode based on the first burst length and the first writing starting address; and writing the test data into the memory according to the first writing rule to obtain first writing data.

In an exemplary embodiment of the present disclosure, the first read-write mode corresponds to a first read start address; the data reading module comprises a first data reading unit and a second data reading unit, wherein the first data reading unit is used for generating a first reading rule corresponding to the first reading and writing mode based on the first burst length and the first reading starting address; and reading the first written data from the memory according to the first reading rule to obtain corresponding first read data.

In an exemplary embodiment of the present disclosure, the read/write mode is a second read/write mode, and the second read/write mode corresponds to a second burst length and a second write start address; the data writing module further comprises a second data writing unit, configured to generate a second writing rule corresponding to the second read-write mode based on the second burst length and the second writing start address; and writing the test data into the memory according to the second writing rule to obtain second writing data.

In an exemplary embodiment of the present disclosure, the data reading module includes a second data reading unit, configured to obtain a generated first reading rule, and determine a first burst length corresponding to the first reading rule; and reading the second write data from the memory according to the first burst length to obtain corresponding second read data.

In an exemplary embodiment of the present disclosure, the read-write mode is a second read-write mode, and the data reading module includes a third data reading unit, configured to acquire a second burst length corresponding to the second read-write mode; determining a plurality of second read starting addresses corresponding to the second read-write mode; the second read start address is determined based on a bit line jump address; and reading the second write data from the memory according to the second burst length and each second read start address to obtain a plurality of corresponding third read data.

In an exemplary embodiment of the present disclosure, the result determining module includes a first result determining unit, configured to determine a burst type corresponding to the read-write mode and a first data arrangement manner corresponding to the burst type; and carrying out consistency comparison on the written data and the read data according to the first data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, the first result determining unit includes a comparison result determining subunit, configured to perform consistency comparison on the first write data and the first read data according to the first data arrangement manner, so as to obtain a first comparison result; performing consistency comparison on second written data and second read data according to the first data arrangement mode to obtain a second comparison result; and performing consistency comparison on the second written data and the third read data according to the first data arrangement mode to obtain a third comparison result.

In an exemplary embodiment of the present disclosure, the result determining module further includes a second result determining unit, configured to determine a read bit line characteristic value corresponding to the first read mode, and obtain a second data arrangement corresponding to the read bit line characteristic value; reading the second written data from the memory by adopting a first reading mode based on the read bit line characteristic value to obtain fourth read data; and performing consistency comparison on the second written data and the fourth read data according to the second data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, the read-write mode includes a diagonal read-write mode, and the method further includes: obtaining a word line and bit line arrangement structure corresponding to the memory, and determining a position point to be written according to the word line and bit line arrangement structure; the position point to be written has a diagonal-like characteristic; writing the test data into the memory according to the position point to be written and a diagonal writing mode to obtain diagonal writing data; reading the diagonal write-in data from the memory to obtain corresponding diagonal read-out data; and carrying out consistency comparison on the diagonal writing data and the diagonal reading data to obtain a diagonal data comparison result.

According to a third aspect of the present disclosure, there is provided an electronic device comprising: a processor; and a memory having computer readable instructions stored thereon which, when executed by the processor, implement the memory detection method according to any of the above.

According to a fourth aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a memory detection method according to any one of the above.

The technical scheme provided by the disclosure can comprise the following beneficial effects:

in the memory detection method in the exemplary embodiment of the disclosure, on one hand, in the memory detection process, by performing the read-write switching operation between different read-write modes, a situation of data read errors in the memory can be accurately detected. On the other hand, by the read-write detection mode and the combination of specific write-in data, the problem that the DIMM end is not started due to read-write errors can be effectively detected, the test efficiency is greatly improved, the test analysis speed is accelerated, and the test cost is effectively saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty. In the drawings:

FIG. 1 schematically illustrates a flow chart of a memory detection method according to an exemplary embodiment of the present disclosure;

FIG. 2 schematically illustrates an overall flow diagram for memory sensing with read-write flexible switching mode, according to an exemplary embodiment of the present disclosure;

FIG. 3 schematically illustrates an arrangement structure of word lines and bit lines of a memory according to an exemplary embodiment of the present disclosure;

FIG. 4 schematically illustrates a flow diagram for reading and writing data using a diagonal read-write mode according to an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a block diagram of data reading and writing using a diagonal read-write mode according to an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a block diagram of a memory detection apparatus according to an exemplary embodiment of the present disclosure;

FIG. 7 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure;

fig. 8 schematically illustrates a schematic diagram of a computer-readable storage medium according to an exemplary embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals denote the same or similar parts in the drawings, and thus, a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.

The block diagrams shown in the figures are functional entities only and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in the form of software, or in one or more software-hardened modules, or in different networks and/or processor devices and/or microcontroller devices.

During the production and testing of DRAMs, it is necessary to test DRAMs many times to find out the problem of data read error (tracking Fail) in DRAMs. In addition, if the DRAM has read/write problems, it may cause a problem of non-boot (boot) at a dual in-line Memory Module (DIMM) end.

Based on this, in the present exemplary embodiment, first, a memory detection method is provided, which may be implemented by a server, or a terminal device, where the terminal described in the present disclosure may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palm computer, a Personal Digital Assistant (PDA), and a fixed terminal such as a desktop computer. FIG. 1 schematically illustrates a schematic diagram of a memory detection method flow, according to some embodiments of the present disclosure. Referring to fig. 1, the memory sensing method may include the steps of:

step S110, test data and a memory to be detected are obtained, the memory is in a read-write flexible switching mode, and the read-write flexible switching mode comprises a plurality of different read-write modes.

Step S120, determining the burst length, the data writing start address and the data reading start address corresponding to each read/write mode.

In step S130, test data is written into the memory based on the burst length and the data write start address to obtain write data.

In step S140, the write data is read from the memory based on the burst length and the data read start address to obtain the corresponding read data.

Step S150, determining a data comparison result between the written data and the read data corresponding to each read/write mode, so as to determine a detection result of the memory according to the data comparison result.

According to the memory detection method in the present exemplary embodiment, on the one hand, in the memory detection process, by performing the read-write switching operation between different read-write modes, it is possible to accurately detect a situation of a data read error in the memory. On the other hand, by the read-write detection mode and the combination of specific write-in data, the problem that the DIMM end is not started due to read-write errors can be effectively detected, the test efficiency is greatly improved, the test analysis speed is accelerated, and the test cost is effectively saved.

Next, a memory detection method in the present exemplary embodiment will be further described.

In step S110, test data and a memory to be detected are obtained, and the memory is in a flexible read/write switching mode, where the flexible read/write switching mode includes multiple different read/write modes.

In some exemplary embodiments of the present disclosure, the test data may be data employed in performing a test operation on the memory. The memory to be tested may be a memory waiting for correctness checking. The read-write flexible switching mode may be a mode that can switch back and forth between a plurality of different read-write modes during memory sensing. The read-write mode may be a mode employed for reading data from the memory and writing data to the memory.

During the product development and testing process of the memory, the memory needs to be subjected to a detection process to detect a memory cell in the memory, where a data reading error occurs. Before performing a memory test, the memory to be tested, such as a DRAM product, and test data for testing the memory may be obtained. Before the memory is detected, the memory can be configured into a read-write flexible switching mode, so that the memory can be flexibly switched among a plurality of different read-write modes in the memory detection process, and data writing operation and data reading operation are carried out by adopting different read-write modes.

In an exemplary embodiment of the present disclosure, a mode register corresponding to a memory is determined, and a current configuration parameter of the mode register is obtained; and if the current configuration parameter is not in the read-write flexible switching mode, performing configuration updating operation on the current configuration parameter so as to enable the memory to be in the read-write flexible switching mode.

The mode register may be a register for storing mode parameters of the memory to be detected, and the mode register may be used to adjust the relevant mode parameters of the memory. The current configuration parameters may be related parameters of various modes corresponding to the current state of the memory. The configuration update operation may be an operation of performing a parameter update on the current configuration parameters of the mode register.

Referring to fig. 2, fig. 2 schematically illustrates an overall flow diagram for memory sensing with read-write flexible switching mode according to an exemplary embodiment of the present disclosure. In step S201, a read-write flexible switching mode is configured. Before the memory is configured in the Mode, a Mode Register corresponding to the memory, for example, a Mode Register (MR) in a DRAM product, abbreviated as (MR Set, MRs), may be determined. After the mode register is determined, the current configuration parameters of the mode register can be obtained, and whether the current configuration parameters are in a read-write flexible switching mode or not is judged. If the current configuration parameter is not in the read-write flexible switching mode, the current configuration parameter is subjected to configuration updating operation, so that the memory is in the read-write flexible switching mode, and the memory can be switched among different read-write modes in the detection process.

For example, when the memory is initially started, the initial configuration parameter of the mode register corresponding to the memory may be a default value, at this time, the initial configuration parameter of the mode register is the current configuration parameter, and the current configuration parameter of the mode register is not in the read-write flexible switching mode, so that the current configuration parameter of the mode register may be configured and updated, for example, the initial configuration parameter is updated to an "on the fly" mode defined by Joint Electron Device Engineering Council (JEDEC) standard, so that the memory is in the read-write flexible switching mode. In addition, when the current configuration parameter of the mode register is in other modes, the current configuration parameter can be updated through parameter configuration operation, so that the mode register is in the "on the fly" mode. Referring to table 1, table 1 shows the corresponding specific meanings of the mode register defined in the JEDEC standard in different operation modes.

TABLE 1 mode register description Table

As can be seen from table 1, the current mode of the memory can be adjusted by configuring the configuration parameters of the mode register, for example, when the parameter value of "a 1: a 0" is 00, the current mode of the memory is "8 (Fixed)", and the burst length corresponding to the read/write mode is a Fixed value of 8; when the parameter value of the A1: A0 is 01, the current mode of the memory is an 'on the fly' mode, and the burst length corresponding to the read-write mode is 4 or 8; when the parameter value of "a 1: a 0" is 10, the current mode of the memory is a "BC 4 (Fixed)" mode, and the burst length corresponding to the read-write mode is a Fixed value of 4; when the parameter value of "A1: A0" is 11, then the current mode of the memory is "Reserved" mode. When the memory is tested, the current configuration parameter of the mode register "A1: A0" can be configured to be 01, so that the memory is in the "on the fly" mode, and the memory can be switched between the BL8 mode and the BC4 mode during the memory test, and the burst length is 4 or 8.

In an exemplary embodiment of the present disclosure, the read-write modes in the read-write flexible switching mode may be switched to each other, and each read-write mode corresponds to a different burst length.

The Burst (Burst) refers to a manner in which adjacent memory cells in the same row continuously perform data transmission, and the number of memory cells (columns) involved in the continuous transmission is a Burst Length (BL).

When the mode register is in a read-write flexible switching mode (i.e., on the fly), it indicates that the memory can be switched among a plurality of different read-write modes; the different read/write modes correspond to different burst lengths, for example, the burst length of the BL8 mode is 8, and the burst length of the BC4 mode is 4.

In step S120, the burst length, the data writing start address, and the data reading start address corresponding to each read/write mode are determined.

In some exemplary embodiments of the present disclosure, the data write start address may be a start address employed when writing the test data into the memory. The data read start address may be a start address used when the written test data is read from the memory.

When a plurality of read-write modes corresponding to the memory are determined, burst lengths corresponding to each read-write mode can be respectively determined, a data write start address adopted when the read-write mode is adopted for data write operation, and a data read start address adopted when the read-write mode is adopted for reading written data.

In some exemplary embodiments of the present disclosure, the write data may be test data that is written in the memory in a specified read-write mode.

After the burst length and the data writing start address corresponding to the read-write mode are determined, the test data can be written into the memory according to the burst length and the data writing start address to obtain written data, so that the written data can be read out through data reading operation in the following process. In the process of detecting the memory, specific test data can be adopted for reading and writing so as to achieve a certain detection effect.

In some exemplary embodiments of the present disclosure, the read data may be written test data read from the memory in a specified read-write mode.

After the data writing operation is completed, a data reading and writing mode corresponding to the data reading operation can be further determined, and the data reading and writing mode adopted by the data writing operation and the data reading operation can be the same or different. And reading the written test data from the memory according to the determined burst length and the data reading initial address to obtain corresponding read data.

In an exemplary embodiment of the present disclosure, a first write rule corresponding to a first read-write mode is generated based on a first burst length and a first write start address; and writing the test data into the memory according to the first writing rule to obtain first writing data.

The first read-write mode may be a mode corresponding to data read and write operations with a first burst length. The first burst length may be a burst length corresponding to the first read-write mode. The first write start address may be a data write start address corresponding to the first read-write mode. The first write rule may be a rule employed when data is written into the memory in the first read-write mode. The first write data may be data written into the memory in a first read-write mode.

With continued reference to fig. 2, in step S202, data is written in a first read-write mode. The first read-write mode may be a BL8 mode, and the BL8 mode corresponds to a burst length of 8, that is, the first burst length is 8; in the present data write operation, the first write start address may be determined as the start address of the data, e.g., Y ═ 0. After the first burst length and the first Write start address are determined, a first Write rule may be generated according to the first burst length and the first Write start address, where the first Write rule includes that the first burst length 8 is used and a data Write operation is performed from the bit line start address Y ═ 0, the first Write rule may be a "Write operation burst mode Write data Write mode (BL 8)", and a corresponding code is denoted as "Write burst (01011101) (BL 8)". The test data can be written into the memory using the first write rule, generating first write data, so that the first write data can be subsequently read out from the memory.

In an exemplary embodiment of the present disclosure, a first read rule corresponding to a first read-write mode is generated based on a first burst length and a first read start address; and reading the first written data from the memory according to a first reading rule to obtain corresponding first read data.

The first read start address may be a data read start address corresponding to the first read/write mode. The first read rule may be a rule employed when the written data is read out to the memory in the first read-write mode. The first read data may be written data read from the memory in the first read-write mode.

In step S203, data is read in the first read-write mode. In the data reading operation, the first write data may be read in a first read/write mode. The first read-write mode is still adopted when the data is read, so that the first burst length is still corresponding to the first write-in data when the data is read. In addition, a first read start address corresponding to reading the first write data may be determined. A first Read rule is generated according to the first burst length and the first Read start address, and the first Read rule may be "Read operation burst mode to-be-Read data Read mode (BL8) Read start address (Y ═ 0)", and the corresponding code is denoted as "Read burst (01011101) (BL8) (Y ═ 0)". After obtaining the first reading rule, the first write data may be read from the memory according to the first reading rule, so as to obtain, in step S204, the first read data, that is, the specific reading result obtained by performing the reading operation in the "on the fly" mode in the (BL8) mode is determined. For example, in the present data reading operation, the obtained first read data may be "(01011101), (10101110), (01010111), (10101011), (11010101), (11101010), (01110101), (10111010)", and after the first read data is obtained, the first read data may be compared with the first write data in a subsequent data comparison process.

In an exemplary embodiment of the present disclosure, a second write rule corresponding to a second read-write mode is generated based on a second burst length and a second write start address; and writing the test data into the memory according to the second writing rule to obtain second writing data.

The second read/write mode may be a mode corresponding to data read and write operations with a second burst length. The second burst length may be a burst length corresponding to the second read-write mode. The second write start address may be a data write start address corresponding to the second read write mode. The second writing rule may be a rule employed when writing data into the memory using the second read-write mode. The second write data may be data written into the memory using a second read-write mode.

In step S205, data is written using the second read/write mode. After the data writing and reading operations are completed in the first read-write mode, the data writing operation can be performed based on the second read-write mode again. The second read/write mode corresponds to a second burst length, and the second read/write mode may be a BC4 mode, where the second burst length is 4; in addition, a second Write start address when a data Write operation is performed in the second read/Write mode may be determined, in this data Write operation, the second data Write start address is still "Y ═ 0", and a second Write rule may be generated according to the second burst length and the second Write start address, and the second Write rule may be, for example, a "Write operation burst mode (first four-bit fixed content Write start address (Y ═ 0)) Write mode (BC 4)", and may be, as indicated by a corresponding code, "Write burst (0111Y ═ 0) (BC 4)", that is, the written test data, the first four bits are all "0111", and the last four bits are the actual value of the test data. For example, when the original test data is "01011101", the write data obtained by this writing method will be "01111101". And performing data writing operation by adopting a second writing rule to obtain second writing data so as to read the second writing data from the memory in the following process.

In an exemplary embodiment of the present disclosure, a generated first reading rule is obtained, and a first burst length corresponding to the first reading rule is determined; and reading the second write data from the memory according to the first burst length to obtain corresponding second read data.

The second read data may be written second write data read from the memory in the first read/write mode.

In the process of detecting the memory, different read-write modes are switched continuously, test data are repeatedly written into the memory and read out from the memory, and therefore storage units with data reading errors possibly existing in the memory are detected. In step S206, the second write data is read in the first read/write mode. Illustratively, the pre-generated first Read rule is "Read operation burst mode to-be-Read data Read mode (BL 8)", and the corresponding code is "Read burst (01111101) (BL 8)", so that in step S207, the second Read data is obtained by using the first Read rule, that is, the specific Read result obtained by performing the Read operation in the "on the fly" mode in the (BL8) mode is determined. In the present embodiment, the read second readout data may be "(01011101), (10101110), (01010111), (10101011), (11010101), (11101010), (01110101), (10111010)". After the second read data is obtained, the second read data may be subjected to a consistency comparison operation with corresponding second write data.

In an exemplary embodiment of the present disclosure, a second burst length corresponding to a second read/write mode is obtained; determining a plurality of second reading starting addresses corresponding to the second reading and writing mode; a second read start address is determined based on the bit line jump address; and reading second write-in data from the memory according to the second burst length and each second reading starting address to obtain a plurality of corresponding third read-out data.

The second read start address may be a data read start address corresponding to the second read/write mode. The bit line transition address may be an address determined based on a starting address and a fixed number of transitions. The third read-out data may be data read out by performing a read operation on the second write-in data from the memory by using a second read-write mode, and when the data is read, a plurality of third read-out data may be obtained because the second read-write mode corresponds to a plurality of read-write rules.

After the second write data is read in the first read-write mode, the second write data can be continuously read from the memory in the second read-write mode to obtain corresponding read data. And reading data by adopting a second read-write mode and a second read starting address. The second read-write mode may be the BC4 mode, i.e. the second burst length is 4; in addition, a plurality of second read start addresses corresponding to the second read-write mode can be determined continuously, the second read start addresses can be determined through the bit line jump addresses, for example, the bit line jump step can be 4, and the second read start addresses can be determined through the jump of the Y address. And reading second write-in data from the memory according to the second burst length and each second read start address to obtain third read-out data.

The second read start address may be Y ═ 0, Y ═ 4, and so on, in step S208, the data is read using the second read/write mode and the second read/write start address (Y ═ 0), the data is read using the read rule "read operation fixed content read mode (BC 4)" read start address (Y ═ 0), "and in step S209, corresponding third read data is obtained, that is, the read result obtained by reading the first four bits of characters in the" on the fly "mode using the (BC4) mode is determined, for example, the third read data obtained using the read rule may be" (0111), (1011), (1101) ". In step S210, the data is read using the second read/write mode and the second read/write start address (Y ═ 4), the read data may be read using the read rule "read operation fixed content read mode (BC 4)", and in step S211, another third read data is obtained, that is, the read result obtained by reading the last four characters in the "on the fly" mode using the (BC4) mode is determined, for example, the third read data obtained using the read rule may be "(1101), (1110), (0111), (1011)".

The data is read and written in a partial writing and address jumping mode, the use habit of a user side for the memory can be simulated better, and the purposes of detecting test time and saving cost can be achieved by adopting the mode.

In step S150, a data comparison result between the write data and the read data corresponding to each read/write mode is determined, so as to determine a detection result of the memory according to the data comparison result.

In some exemplary embodiments of the present disclosure, the data comparison result may be a result of consistency comparison processing of the write data and the read data. The detection result of the memory can be the result of the detection of the read-write problem of the memory.

After data writing operation and data reading operation are respectively carried out in the memory by adopting each read-write mode, the corresponding written data and the read data in each read-write mode can be determined, consistency comparison is carried out on each written data and each read data to obtain a data comparison result, and finally the detection result of the memory is determined according to the data comparison result.

In an exemplary embodiment of the present disclosure, a burst type corresponding to a read-write mode and a first data arrangement manner corresponding to the burst type are determined; and carrying out consistency comparison on the written data and the read data according to the first data arrangement mode to obtain a data comparison result.

The burst type may be a type corresponding to continuous data transmission. The data arrangement may be an arrangement in which the transmission data corresponds to a burst type during continuous data transmission.

Before data comparison between write data and read data, the burst type corresponding to the read-write mode may be obtained, and before memory detection, the burst type and burst rule content table may be configured in advance. Referring to table 2, table 2 lists specific contents of the burst types and the burst rules defined in the JEDEC standard, specifically, the table of contents of the burst types and the burst rules defines burst types corresponding to different burst lengths, and the table of contents of the burst types and the burst rules defines different data arrangement manners corresponding to different burst types.

Table 2 burst type and burst rules table

As can be seen from table 2, the burst type and burst rule table may include the burst length, read/write mode, starting column address, burst type and remark. Before data comparison, the burst type corresponding to the read/write mode may be determined, for example, the burst type may include a Sequential access type (Sequential) and an interleaved access type (lnterlaceved), where different burst types correspond to different data arrangement manners. After determining the burst type corresponding to the read data, a first data arrangement mode corresponding to the burst type can be obtained, consistency comparison is performed on the write data and the read data according to the first data arrangement mode, and a data comparison result is obtained.

For example, in the process of the memory test, the burst type corresponding to the read/write mode is Sequential, and the first data arrangement mode corresponding to the burst type Sequential is shown in the fourth column in table 2. For different burst lengths, different data arrangement modes are provided, table 2 shows a first data arrangement mode corresponding to the burst type Sequential when the burst lengths are respectively 4 and 8, and consistency comparison can be performed on write data and read data according to the first data arrangement mode shown in table 2, so as to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, consistency comparison is performed on first write data and first read data according to a first data arrangement manner, resulting in a first comparison result; performing consistency comparison on the second written data and the second read data according to the first data arrangement mode to obtain a second comparison result; and comparing the consistency of the second written data and the third read data according to the first data arrangement mode to obtain a third comparison result.

Wherein the first comparison result may be a result of consistency comparison of the first write data and the first read data. The second comparison result may be a result of consistency comparison of the second written data with the second read data. The third comparison result may be a result of consistency comparison of the second write data with the third read data.

After the first data arrangement is determined, data consistency comparison may be performed according to the first data arrangement, for example, consistency comparison is performed on the first Write data and the first read data, and table 2 shows a data arrangement corresponding to writing and reading in the Sequential type, for example, the first Write data may be according to a burst length of 8 and be a corresponding data arrangement in the Write operation. For the first Read data, a data arrangement mode with a burst length of 8 and corresponding to the Read operation may be adopted, for example, in the Read operation, a data arrangement mode of A2A1a0 ═ 000 may be adopted for data comparison. And performing consistency comparison on the first written data and the first read data by adopting the corresponding first data arrangement mode to obtain a data comparison result.

The second write data and the second read data, and the second write data and the third read data may be compared in the same manner as the first write data and the first read data. In the data consistency comparison process, data comparison is carried out according to the data arrangement mode corresponding to the burst type, so that the data comparison process is more diversified, and the storage unit with data reading errors in the storage is comprehensively detected.

In an exemplary embodiment of the present disclosure, a read bit line characteristic value corresponding to a first read mode is determined, and a second data arrangement corresponding to the read bit line characteristic value is obtained; reading second write data from the memory based on the read bit line characteristic value and by adopting a first reading mode to obtain fourth read data; and performing consistency comparison on the second written data and the fourth read data according to the second data arrangement mode to obtain a data comparison result.

The read bit line characteristic value may be a specific value corresponding to a bit line used in the data reading process. The fourth read data may be data obtained by reading the second write data in the second data reading mode.

In order to further simulate the actual situation that a user uses the memory, in the memory detection process, different read bit line characteristic values can be used for determining the corresponding data arrangement mode so as to detect the memory cells with data read errors possibly existing in the memory. With continued reference to FIG. 2, in step S212, data is read using different read bit line characteristics. For example, in the data reading operation of this time, the first read-write mode may still be adopted, and the read bit line characteristic values are continuously converted to perform consistency comparison on the read fourth read data according to the second data arrangement mode corresponding to the different read bit line characteristic values.

For example, in the data reading process, the data may be Read according to a Read burst (01011101) (BL8) (Y ═ 7) "indicating that the data is Read according to a burst length of 8 and the characteristic value of the Read bit line is 7, and after the fourth Read data is Read according to the Read rule, the fourth Read data and the second write data may be compared for consistency according to the second data arrangement corresponding to Y ═ 7 in table 2, so as to obtain a data comparison result. In addition, the Read bit line characteristic value may be continuously adjusted, for example, if the Read bit line characteristic value is changed to 6, the Read rule at this time is "Read burst (01011101) (BL8) (Y ═ 6)", another fourth Read data is Read by using the Read rule, and the fourth Read data and the second write data are compared in data consistency according to the second data arrangement manner to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, a word line and bit line arrangement structure corresponding to a memory is obtained, and a position point to be written is determined according to the word line and bit line arrangement structure; the position points to be written have diagonal-like characteristics; writing the test data into a memory according to the position point to be written and the diagonal writing mode to obtain diagonal writing data; reading the diagonal write-in data from the memory to obtain corresponding diagonal read-out data; and carrying out consistency comparison on the diagonal writing data and the diagonal reading data to obtain a diagonal data comparison result.

The word line and bit line arrangement structure may be a specific structure in which word lines and bit lines are arranged in a memory. The position point to be written may be a position point corresponding to when the data writing operation is waiting to be performed. The diagonal-like feature may be an arrangement feature similar to a quadrilateral diagonal possessed by the position point to be written. The diagonal write data may be data resulting from writing test data to memory based on the class diagonal feature. The diagonal read data may be data obtained by reading diagonal write data from a memory. The diagonal data comparison result may be a result of consistency comparison of diagonal write data and diagonal read data.

In the memory detection process, in order to further improve the test coverage, diagonal write data can be used for writing and reading test data into the memory so as to perform data consistency comparison on the diagonal write data and the diagonal read data. In step S213, data is written and read in a diagonal read-write mode. When data is written by using a diagonal writing method, a word line and bit line arrangement structure corresponding to the memory may be determined, and referring to fig. 3, fig. 3 schematically illustrates an arrangement structure diagram of word lines and bit lines of the memory according to an exemplary embodiment of the present disclosure. The memory comprises Word Lines (WL), Bit Lines (BL) and an SA module; here, the word line address may be represented by an X address, and the bit line address may be represented by a Y address. For example, the word line in the memory may be 65536, and in the memory detection process, the jump address set by the read-write data needs to be divisionally divided by 65536 to achieve a word cycle read-write mode, so that the determined fixed jump number needs to be guaranteed to be divisionally divided by the number of the word line in the memory, and meanwhile, both sides of the SA module need to be covered to meet the test requirement.

Referring to fig. 4, fig. 4 schematically illustrates a flow chart for reading and writing data using a diagonal read-write mode according to an exemplary embodiment of the present disclosure. In step S410, a word line and bit line arrangement structure corresponding to the memory is obtained, and a position point to be written is determined according to the word line and bit line arrangement structure; the position points to be written have a diagonal-like character. Specifically, referring to fig. 5, fig. 5 schematically illustrates a structure diagram of data reading and writing using a diagonal reading and writing mode according to an exemplary embodiment of the present disclosure. The word lines and bit lines in the memory are arranged horizontally and vertically, for example, a plurality of to-be-written location points 510 are determined according to the structural features of the intersections of the word lines and the bit lines, and as can be seen from fig. 5, the plurality of to-be-written location points exhibit diagonal-like features.

In step S420, test data is written into the memory according to the location point to be written and the diagonal writing manner, so as to obtain diagonal write data. After the position point to be written is determined, the test data can be written into the memory according to the position point to be written and the diagonal writing mode, so that diagonal writing data can be obtained. In step S430, the diagonal write data is read from the memory to obtain corresponding diagonal read data. After the generation of the diagonal write operation is completed, a data read operation may be performed based on the memory to read the diagonal write data from the memory as diagonal read data. Specifically, data can be written into the memory by the following jump rule, such as "partial data operation (jump step in X direction + X) (jump step in Y direction + Y) -diagonal write/diagonal read operation". The read-write rule indicates that the step size of the jump of X can be 512 and the step size of the jump of Y can be 8.

In step S440, the diagonal write data and the diagonal read data are subjected to consistency comparison to obtain a diagonal data comparison result. After the diagonal write data and the diagonal read data are obtained, consistency comparison may be performed on the diagonal data according to a data arrangement manner configured in advance, and it may be determined whether the diagonal write data and the diagonal read data are consistent.

In the detection process of the memory, a position point to be written with the similar diagonal feature is determined, array data are written based on the position point to be written, and test operation in a larger range can be performed by adopting less data, so that the aim of increasing the test coverage rate is fulfilled.

In an exemplary embodiment of the present disclosure, if the data comparison result is that the written data is consistent with the read data, the detection result is that there is no read-write problem in the memory; and if the data comparison result is that the written data is inconsistent with the read data, the detection result indicates that the memory has read-write problems.

After the data comparison result is obtained, the detection result of the memory can be determined according to the data comparison result. For example, if the data comparison result indicates that the written data and the read data are consistent, the read data and the written data are consistent, and in this case, the detection result of the memory indicates that the memory has no read-write problem. If the data comparison result is that the written data is inconsistent with the read data, it indicates that the read data and the written data have access, which may be a problem in the data reading and writing process, and the detection result of the memory at this time indicates that the memory has a reading and writing problem. By the reading and writing mode and the specific written data, the problem of no start-up (boot) of the DIMM end can be effectively detected, and the product quality is greatly improved. For example, different unboot problems exist for different servers or terminals, such as SO-DIMM problem at the notebook computer end, U-DIMM problem at the desktop computer end, and R-DIMM problem at the server end. If the unboot phenomenon occurs in different servers or terminals, the unboot problem caused by the read-write error can be detected only through the scheme.

It should be noted that the terms "first", "second", "third", "fourth", and the like, used in this disclosure, are only used to distinguish different data read/write modes, different burst lengths, different write start addresses, different write rules, different read start addresses, different read rules, different write data, different read data, and the like, and should not impose any limitation on this disclosure.

In summary, the test data and the memory to be detected are obtained, the memory is in a flexible read/write switching mode, and the flexible read/write switching mode includes multiple different read/write modes; determining burst length, data writing initial address and data reading initial address corresponding to each read-write mode; writing test data into a memory based on the burst length and the data writing start address to obtain writing data; reading write data from a memory based on the burst length and the data reading start address to obtain corresponding read data; and determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine a detection result of the memory according to the data comparison result. On one hand, in the process of detecting the memory, the read-write switching operation is carried out between different read-write modes, so that the situation of data reading errors in the memory can be accurately detected. On the other hand, by the read-write detection mode and the combination of specific write-in data, the problem that the DIMM end is not started due to read-write errors can be effectively detected, the test cost is effectively saved, and the DIMM strip end test program is used for realizing the DIMM end test, so that the test efficiency can be greatly improved, and the test analysis speed is accelerated. In another aspect, the data read and write can be performed by address hopping, so that the purposes of reducing test time and saving cost can be achieved. On the other hand, the purpose of increasing the test coverage rate can be achieved by writing test data in the similar diagonal direction.

It is noted that although the steps of the methods of the present invention are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

Further, in the present exemplary embodiment, a memory detection apparatus is also provided. Referring to fig. 6, the memory detection apparatus 600 may include: a memory retrieval module 610, a rule generation module 620, a data write module 630, a data read module 640, and a result determination module 650.

Specifically, the memory obtaining module 610 is configured to obtain test data and a memory to be detected, where the memory is in a flexible read/write switching mode, and the flexible read/write switching mode includes multiple different read/write modes; a rule generating module 620, configured to determine a burst length, a data writing start address, and a data reading start address corresponding to each read-write mode; a data writing module 630, configured to write the test data into the memory based on the burst length and the data writing start address to obtain write data; a data reading module 640, configured to read write data from a memory based on the burst length and the data reading start address to obtain corresponding read data; the result determining module 650 is configured to determine a data comparison result between the write data and the read data corresponding to each read/write mode, so as to determine a detection result of the memory according to the data comparison result.

Further, the memory detection device 600 may represent one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the memory detection device 600 may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The memory detection device 600 may also be one or more special-purpose processing devices, such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like. The memory detection device 600 is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device to communicate over a network.

In an exemplary embodiment of the present disclosure, the read-write mode is a first read-write mode, and the first read-write mode corresponds to a first burst length and a first write start address; the data writing module comprises a first data writing unit and a second data writing unit, wherein the first data writing unit is used for generating a first writing rule corresponding to a first reading and writing mode based on a first burst length and a first writing starting address; and writing the test data into the memory according to the first writing rule to obtain first writing data.

In an exemplary embodiment of the present disclosure, the first read-write mode corresponds to a first read start address; the data reading module comprises a first data reading unit and a second data reading unit, wherein the first data reading unit is used for generating a first reading rule corresponding to a first reading-writing mode based on a first burst length and a first reading initial address; and reading the first written data from the memory according to a first reading rule to obtain corresponding first read data.

In an exemplary embodiment of the present disclosure, the read-write mode is a second read-write mode, and the second read-write mode corresponds to a second burst length and a second write start address; the data writing module further comprises a second data writing unit, which is used for generating a second writing rule corresponding to a second reading and writing mode based on the second burst length and the second writing starting address; and writing the test data into the memory according to the second writing rule to obtain second writing data.

In an exemplary embodiment of the present disclosure, the data reading module includes a second data reading unit, configured to obtain the generated first reading rule, and determine a first burst length corresponding to the first reading rule; and reading the second write data from the memory according to the first burst length to obtain corresponding second read data.

In an exemplary embodiment of the present disclosure, the read-write mode is a second read-write mode, and the data reading module includes a third data reading unit, configured to acquire a second burst length corresponding to the second read-write mode; determining a plurality of second reading starting addresses corresponding to the second reading and writing mode; a second read start address is determined based on the bit line jump address; and reading the second write-in data from the memory according to the second burst length and each second read start address to obtain a plurality of corresponding third read-out data.

In an exemplary embodiment of the present disclosure, the result determining module includes a first result determining unit, configured to determine a burst type corresponding to the read-write mode and a first data arrangement manner corresponding to the burst type; and comparing the consistency of the written data and the read data according to the first data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the present disclosure, the first result determining unit includes a comparison result determining subunit, configured to perform consistency comparison on the first write data and the first read data according to the first data arrangement manner, to obtain a first comparison result; performing consistency comparison on the second written data and the second read data according to the first data arrangement mode to obtain a second comparison result; and comparing the consistency of the second written data and the third read data according to the first data arrangement mode to obtain a third comparison result.

In an exemplary embodiment of the present disclosure, the result determining module further includes a second result determining unit, configured to determine a read bit line characteristic value corresponding to the first read mode, and obtain a second data arrangement corresponding to the read bit line characteristic value; reading second write data from the memory based on the read bit line characteristic value and by adopting a first reading mode to obtain fourth read data; and performing consistency comparison on the second written data and the fourth read data according to the second data arrangement mode to obtain a data comparison result.

In an exemplary embodiment of the disclosure, the read-write mode includes a diagonal read-write mode, the method further comprising: obtaining a word line and bit line arrangement structure corresponding to a memory, and determining a position point to be written according to the word line and bit line arrangement structure; the position points to be written have diagonal-like characteristics; writing the test data into a memory according to the position point to be written and the diagonal writing mode to obtain diagonal writing data; reading the diagonal write-in data from the memory to obtain corresponding diagonal read-out data; and carrying out consistency comparison on the diagonal writing data and the diagonal reading data to obtain a diagonal data comparison result.

In an exemplary embodiment of the present disclosure, determining a detection result of the memory according to the data comparison result includes: if the data comparison result is that the written data is consistent with the read data, the detection result indicates that the memory has no read-write problem; and if the data comparison result is that the written data is inconsistent with the read data, the detection result indicates that the memory has read-write problems.

The details of the virtual module of each memory detection device are described in detail in the corresponding memory detection method, and therefore are not described herein again.

It should be noted that although in the above detailed description several modules or units of the memory detection means are mentioned, this division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

In addition, in an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 700 according to such an embodiment of the present disclosure is described below with reference to fig. 7. The electronic device 700 shown in fig. 7 is only an example and should not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 7, electronic device 700 is embodied in the form of a general purpose computing device. The components of the electronic device 700 may include, but are not limited to: the at least one processing unit 710, the at least one memory unit 720, a bus 730 connecting different system components (including the memory unit 720 and the processing unit 710), and a display unit 740.

Wherein the storage unit stores program code that is executable by the processing unit 710 to cause the processing unit 710 to perform steps according to various exemplary embodiments of the present disclosure as described in the above section "exemplary methods" of this specification. The storage unit 720 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM)721 and/or a cache memory unit 722, and may further include a read only memory unit (ROM) 723.

The memory unit 720 may include a program/utility 724 having a set (at least one) of program modules 725, such program modules 725 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment. The program module 725 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

Bus 730 may represent one or more of any of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The electronic device 700 may also communicate with one or more external devices 770 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 700, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 700 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 750. Also, the electronic device 700 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the internet) via the network adapter 760. As shown, the network adapter 760 communicates with the other modules of the electronic device 700 via the bus 730. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. The solution according to embodiments of the present disclosure may therefore be embodied in the form of a software product, which may be stored in one memory device, which may comprise different types of non-volatile memory devices and/or any combination of volatile memory devices. Volatile memory devices, such as memory devices, may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM). The software product may also be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes instructions to cause a computing device (which may be a personal computer, a server, a terminal apparatus, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above-mentioned "exemplary methods" section of the present description, when said program product is run on the terminal device.

Referring to fig. 8, a program product 800 for implementing the above method according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited in this regard and, in the present document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.

Claims

1. A memory sensing method, comprising:

the method comprises the steps that test data and a memory to be detected are obtained, wherein the memory is in a flexible read-write switching mode, and the flexible read-write switching mode comprises multiple different read-write modes;

determining burst length, data writing initial address and data reading initial address corresponding to each read-write mode;

writing the test data into a memory based on the burst length and the data write start address to obtain write data;

reading the written data from the memory based on the burst length and the data reading start address to obtain corresponding read data;

and determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine a detection result of the memory according to the data comparison result.

2. The method of claim 1, further comprising:

determining a mode register corresponding to the memory, and acquiring the current configuration parameters of the mode register;

and if the current configuration parameter is not in the read-write flexible switching mode, performing configuration updating operation on the current configuration parameter so as to enable the memory to be in the read-write flexible switching mode.

3. The method according to claim 1 or 2, wherein each of the read/write modes in the flexible read/write switching mode can be switched with each other, and each of the read/write modes corresponds to a different burst length.

4. The method of claim 1, wherein the read/write mode is a first read/write mode, and the first read/write mode corresponds to a first burst length and a first write start address; writing the test data into a memory based on the burst length and the data write start address to obtain write data, comprising:

generating a first writing rule corresponding to the first reading and writing mode based on the first burst length and the first writing starting address;

and writing the test data into the memory according to the first writing rule to obtain first writing data.

5. The method of claim 4, wherein the first read/write mode corresponds to a first read start address; reading the write data from the memory based on the burst length and the data read start address to obtain corresponding read data, including:

generating a first reading rule corresponding to the first reading and writing mode based on the first burst length and the first reading starting address;

and reading the first written data from the memory according to the first reading rule to obtain corresponding first read data.

6. The method of claim 1, wherein the read/write mode is a second read/write mode, and the second read/write mode corresponds to a second burst length and a second write start address; writing the test data into a memory according to the data writing rule to obtain written data, including:

generating a second write rule corresponding to the second read-write mode based on the second burst length and the second write start address;

and writing the test data into the memory according to the second writing rule to obtain second writing data.

7. The method of claim 6, wherein reading the write data from the memory based on the burst length and the data read start address to obtain corresponding read data comprises:

acquiring a generated first reading rule, and determining a first burst length corresponding to the first reading rule;

and reading the second write data from the memory according to the first burst length to obtain corresponding second read data.

8. The method of claim 6, wherein the read/write mode is a second read/write mode, and reading the write data from the memory based on the burst length and the data read start address to obtain corresponding read data comprises:

acquiring a second burst length corresponding to the second read-write mode;

determining a plurality of second read starting addresses corresponding to the second read-write mode; the second read start address is determined based on a bit line jump address;

and reading the second write data from the memory according to the second burst length and each second read start address to obtain a plurality of corresponding third read data.

9. The method of claim 1, wherein determining a data comparison result between the write data and the read data corresponding to each of the read/write modes comprises:

determining a burst type corresponding to the read-write mode and a first data arrangement mode corresponding to the burst type;

and carrying out consistency comparison on the written data and the read data according to the first data arrangement mode to obtain a data comparison result.

10. The method of claim 9, wherein comparing the consistency of the write data and the read data according to the first data arrangement to obtain the data comparison result comprises:

performing consistency comparison on the first written data and the first read data according to the first data arrangement mode to obtain a first comparison result;

performing consistency comparison on second written data and second read data according to the first data arrangement mode to obtain a second comparison result;

and performing consistency comparison on the second written data and the third read data according to the first data arrangement mode to obtain a third comparison result.

11. The method of claim 6, further comprising:

determining a read bit line characteristic value corresponding to a first read mode, and acquiring a second data arrangement mode corresponding to the read bit line characteristic value;

reading the second written data from the memory by adopting a first reading mode based on the read bit line characteristic value to obtain fourth read data;

and performing consistency comparison on the second written data and the fourth read data according to the second data arrangement mode to obtain a data comparison result.

12. The method of claim 1, wherein the read-write mode comprises a diagonal read-write mode, the method further comprising:

obtaining a word line and bit line arrangement structure corresponding to the memory, and determining a position point to be written according to the word line and bit line arrangement structure; the position point to be written has a diagonal-like characteristic;

writing the test data into the memory according to the position point to be written and a diagonal writing mode to obtain diagonal writing data;

reading the diagonal write-in data from the memory to obtain corresponding diagonal read-out data;

and carrying out consistency comparison on the diagonal writing data and the diagonal reading data to obtain a diagonal data comparison result.

13. The method of claim 1, wherein determining the detection result of the memory according to the data comparison result comprises:

if the data comparison result indicates that the written data is consistent with the read data, the detection result indicates that the memory has no read-write problem;

and if the data comparison result indicates that the written data is inconsistent with the read data, the detection result indicates that the memory has a read-write problem.

14. A memory device, comprising:

the device comprises a memory acquisition module, a test data acquisition module and a memory to be detected, wherein the memory is in a read-write flexible switching mode, and the read-write flexible switching mode comprises a plurality of different read-write modes;

a rule generating module, configured to determine a burst length, a data writing start address, and a data reading start address corresponding to each read-write mode;

a data writing module, configured to write the test data into a memory based on the burst length and the data writing start address to obtain write data;

a data reading module, configured to read the write data from the memory based on the burst length and the data reading start address to obtain corresponding read data;

and the result determining module is used for determining a data comparison result of the written data and the read data corresponding to each read-write mode so as to determine the detection result of the memory according to the data comparison result.

15. An electronic device, comprising:

a processor; and

a memory having computer readable instructions stored thereon which, when executed by the processor, implement the memory detection method of any one of claims 1 to 13.

16. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the memory detection method according to any one of claims 1 to 13.