CN112133357B - eMMC test method and device - Google Patents
eMMC test method and device Download PDFInfo
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- CN112133357B CN112133357B CN202011066427.3A CN202011066427A CN112133357B CN 112133357 B CN112133357 B CN 112133357B CN 202011066427 A CN202011066427 A CN 202011066427A CN 112133357 B CN112133357 B CN 112133357B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application is applicable to the field of memory bank pieces and provides a test method and device of eMMC, wherein the test method comprises the following steps: determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; writing the bottom pattern data into each sector in the target area, and writing the background pattern data into each sector in the test area; performing power-off verification operation on the test area to obtain a verification state of the test area; and determining a test result of the eMMC based on the verification state of the test area. According to the method and the device, the test area is selected randomly to test, the probability of selecting the abnormal area as the test area is increased, the test effect can be improved, and the problem that the data error is caused by the fact that the tested eMMC is powered off in actual use due to poor effect of testing the power-off data protection performance of the eMMC through power-off verification in the prior art is solved.
Description
Technical Field
The application belongs to the field of memory bank pieces, and particularly relates to a testing method and device of an eMMC.
Background
eMMC (Embedded Multi Media Card ) is commonly used in mobile phones, tablet computers, communication devices, as a storage device. These devices often have a power failure condition, and if power is cut off during normal writing of data to eMMC, data errors, anomalies, etc. may be caused, thereby reducing stability of the devices. Therefore, the eMMC needs to be subjected to a power-off performance test to ensure that the eMMC has a strong power-off protection capability.
However, in the eMMC test in the prior art, during power failure, fixed pattern data is generally written into a certain fixed area with a fixed size in the eMMC to perform power failure test verification, so that the power failure test verification is not strict enough, and the eMMC verified by the power failure test may cause data errors when in-service power failure, that is, the test effect of the power failure test verification is poor.
Disclosure of Invention
The embodiment of the application provides a test method and device for eMMC, which can improve the test effect by randomly selecting a test area, and solve the problem that the test result is likely to be wrong due to the fact that the power failure causes data errors when the tested eMMC is in actual use due to poor effect of power failure data protection performance of the test eMMC in the prior art.
In a first aspect, an embodiment of the present application provides a method for testing eMMC, including: determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; writing the bottom pattern data into each sector in the target area, and writing the background pattern data into each sector in the test area; performing power-off verification operation on the test area to obtain a verification state of the test area; and determining a test result of the eMMC based on the verification state of the test area.
In a possible implementation manner of the first aspect, the determining, based on the verification state of the test area, the test result of the eMMC includes: and determining a test result of the eMMC based on the verification states of the test areas corresponding to all the partitions of the eMMC.
It should be understood that, generally, only one partition, that is, the target area, of the eMMC needs to be selected randomly, and the test result of the eMMC can be determined based on the verification state of the test area corresponding to the target area. In one possible implementation manner of the foregoing, the test result of the eMMC is determined based on the verification states of the test areas corresponding to all the partitions of the eMMC, that is, only if the verification states of the test areas corresponding to all the partitions of the eMMC are passed, the test result of the eMMC is passed, so that the test is relatively more strict, the efficiency of the test is reduced, the resource consumption is increased, and the test method provided by the possible implementation manner can be executed according to the requirements.
In a second aspect, an embodiment of the present application provides a testing device of eMMC, including: the test area determining module is used for determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; the style data writing module is used for writing the bottom style data into each sector in the target area and writing the background style data into each sector in the test area; the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area; and the test result determining module is used for determining the test result of the eMMC based on the verification state of the test area.
In a third aspect, an embodiment of the present application provides a terminal device, including: a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method of any one of the above first aspects when the computer program is executed.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, comprising: the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any of the above first aspects.
In a fifth aspect, embodiments of the present application provide a computer program product for, when run on a terminal device, causing the terminal device to perform the method of any one of the first aspects.
It will be appreciated that the advantages of the second to fifth aspects may be found in the relevant description of the first aspect, and are not described here again.
Compared with the prior art, the embodiment of the application has the beneficial effects that:
compared with the prior art, the testing method provided by the application has the advantages that the testing is carried out by randomly selecting the testing area, the probability of selecting the abnormal area as the testing area is increased, the testing effect can be improved, and the problem that the data error is caused by the fact that the tested eMMC is in the fact that the power failure verification testing effect is poor in the prior art is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an implementation of the test method provided in the first embodiment of the present application;
FIG. 2 is a flow chart of an implementation of the test method provided in the second embodiment of the present application;
FIG. 3 is a flow chart of an implementation of the test method provided in the third embodiment of the present application;
fig. 4 is a schematic structural diagram of an eMMC provided in a third embodiment of the present application;
FIG. 5 is a flow chart of an implementation of the test method provided in the fourth embodiment of the present application;
FIG. 6 is a flow chart of an implementation of the test method provided in the fifth embodiment of the present application;
FIG. 7 is a flowchart of an implementation of the testing method provided in the sixth embodiment of the present application;
FIG. 8 is a flow chart of an implementation of the test method provided in the seventh embodiment of the present application;
FIG. 9 is a logic flow diagram of an application scenario provided in an embodiment of the present application;
FIG. 10 is a schematic structural diagram of a testing device according to an embodiment of the present disclosure;
fig. 11 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
The term interpretation in relation to the present application is briefly explained here. "data verification" generally refers to scanning data of an object region to obtain current data distribution information of the object region; the determining the verification result of the data verification according to the current data distribution information may specifically be: comparing the current data distribution information with the reference data distribution information corresponding to the data verification, if the current data distribution information and the reference data distribution information are the same, the verification result of the data verification is passed, and if the current data distribution information and the reference data distribution information are different, the verification result of the data verification is failed; the reference data distribution information may be obtained by writing information in recorded history data. It should be understood that the "data verification" in the subsequent third embodiment has a feature definition, and is different from the above general "data verification", and specific details may be found in the subsequent description in the third embodiment. "writing certain data to each sector in a certain area" means writing the certain data to the certain area until the certain area is filled with the certain data; generally, the eMMC starts to receive data by transmitting a write data command to the eMMC.
In the embodiment of the present application, the execution body of the flow is a terminal device. The terminal device includes, but is not limited to: the device such as a server, a computer, a smart phone and a tablet computer can execute the test method provided by the application; the terminal device is preferably a device carrying a uboot system (boot loader of an embedded system), and the test method provided in this embodiment is preferably executed by an ODROID XU4 development board platform of the uboot system. Fig. 1 shows a flowchart of an implementation of the test method provided in the first embodiment of the present application, which is described in detail below:
in S101, a test area within a target area of eMMC is determined based on a random algorithm.
In this embodiment, the target area is any partition of eMMC. For example, according to the eMMC standard, the partitions of eMMC may include 2 Boot partitions (Boot Area Partitions, boot), 1 playback protection memory block (Replay Protected Memory Block, RPMB), 4 general partitions (General Purpose Partitions, GPP), and 1 User Data Area (UDA), 8 total partitions, in which case the target Area may be any one of the above-described partitions. In one possible implementation manner, the determining, based on the random algorithm, the test area in the target area of the eMMC may specifically be: dividing the target area into a plurality of candidate areas based on the size of the target area, and randomly selecting one of the candidate areas as the test area based on a random algorithm; optionally, the larger the storage space of the target area is, the more the number of divided candidate areas is; alternatively, when dividing a plurality of candidate areas, the storage space size of each candidate area may be the same. It should be understood that the above-mentioned random algorithm may be any algorithm that can be implemented to randomly select a region from a plurality of regions as the test region, which is not limited herein.
In S102, the base pattern data is written into each sector in the target area, and then the background pattern data is written into each sector in the test area.
In this embodiment, the base pattern data and the background pattern data are preset pattern data; the writing of the bottom pattern data into each sector in the target area and the writing of the background pattern data into each sector in the test area may specifically be: writing the bottom pattern data into the target area to enable the target area to be filled with the bottom pattern data; for example, the base pattern data may be 0x77, and the base pattern data is filled into each sector, so that the target area is filled with the base pattern data; typically, the size of the sector is 512 bytes.
At this time, the test area in the target area is filled with the bottom pattern data, and then the background pattern data is written into the test area, i.e. the background pattern data covers all the bottom pattern data in the test area, so that the test area is filled with the background pattern data, and detailed description about the bottom pattern data can be referred to, and will not be repeated here. It should be emphasized that the base pattern data may be different from the background pattern data, for example, the base pattern data may be 0x77 and the background pattern data may be 0x88.
It should be appreciated that the underlying style data and background style data herein are used to distinguish the target region from the test region in terms of data distribution to facilitate subsequent power-down verification operations on the test region.
In S103, a power-off verification operation is performed on the test area, resulting in a verification state of the test area.
In one possible implementation manner, the power-off verification operation may specifically be: writing test pattern data into each sector in the test area, powering off the eMMC in the process of writing the test pattern data into each sector in the test area, and powering on the eMMC again after a preset time length; after the power-off operation and the power-on operation are executed, data verification is carried out on the test area, and specifically, current data distribution information in the test area is determined; determining reference data distribution information of the data verification according to the power-off time; comparing the current data distribution information with the reference data distribution information, if the current data distribution information and the reference data distribution information are the same, the verification result of the data verification is passing, namely the verification state of the test area is passing, and if the current data distribution information and the reference data distribution information are different, the verification result of the data verification is not passing, namely the verification state of the test area is not passing.
It should be understood that the test pattern data is different from the base pattern data and the background pattern data, for example, the base pattern data may be 0x77, the background pattern data may be 0x88, and the test pattern data may be 0x66.
In S104, a test result of the eMMC is determined based on the verification state of the test area.
In this embodiment, the determining the test result of the eMMC based on the verification state of the test area may specifically be: if the verification state of the test area is passed, carrying out data verification on a non-test area in the target area, wherein the non-test area is other areas except the test area in the target area; if the verification state of the non-test area is passed, the test result of the eMMC is passed; if the verification state of the non-test area is failed, the test result of the eMMC is failed; if the verification state of the test area is failed, the test result of the eMMC is failed. And verifying the data of the non-test area, specifically, verifying whether the non-test area is full of the bottom pattern data, if the data in the non-test area are all the bottom pattern data, the verification state of the non-test area is passed, otherwise, the verification state of the non-test area is failed.
It should be understood that, in one possible implementation manner, S101 to S103 are executed multiple times before S104 to obtain verification states of multiple test areas, and if the verification state of any test area is failed, determining that the test result of the eMMC is failed; if the verification states of all the test areas are passed, the test result of the eMMC is passed.
In this embodiment, a test area in a target area of an eMMC is randomly determined, and a power-off verification operation is performed on the test area to determine a test result of the eMMC; compared with the prior art, the uncertainty of the test area can be increased, so that more possible areas can be subjected to power-off verification operation, the test result of the eMMC can be determined, the probability of selecting an abnormal area as the test area can be increased on the premise of not increasing the resource consumption of the test (not increasing the size of the test area), the test effect is improved, and the problem that the test area is fixed and the data error is possibly caused by power-off in the actual use of the tested eMMC when the power-off data protection performance of the eMMC is tested through power-off verification in the prior art is solved.
Fig. 2 shows a flowchart of an implementation of the test method provided in the second embodiment of the present application. Referring to fig. 2, with respect to the embodiment illustrated in fig. 1, the test method S103 provided in this embodiment includes S201 to S206, which are specifically described as follows:
In this embodiment, the test area includes a plurality of dynamic areas and a plurality of static areas.
Further, the performing the power-off verification operation on the test area to obtain a verification state of the test area includes:
in S201, N test pattern data are randomly generated and sequentially written into each sector within the target dynamic region.
In this embodiment, N is an integer greater than 1, preferably 3 or 4 or 5, which is preset; the target dynamic region is any dynamic region in the test region.
In this embodiment, the step of randomly generating N test pattern data and the step of sequentially writing the N test pattern data into each sector in the target dynamic area may be performed asynchronously, specifically, the terminal device randomly generates N test pattern data, which are respectively first test pattern data to nth test pattern data, sequentially writes the N test pattern data into each sector in the target dynamic area, specifically, writes the first test pattern data into each sector in the target dynamic area, writes the second test pattern data into each sector … in the target dynamic area, and so on, and finally writes the nth test pattern data into each sector in the target dynamic area.
In one possible manner, the step of randomly generating N test pattern data and the step of sequentially writing the N test pattern data into each sector in the target dynamic area may be performed synchronously, specifically, the terminal device randomly generates first test pattern data, writes the first test pattern data into each sector in the target dynamic area, randomly generates second test pattern data …, and so on, and finally randomly generates nth test pattern data and writes the nth test pattern data into each sector in the target dynamic area.
In S202, in the process of writing the nth test pattern data into each sector in the target dynamic area, the eMMC is powered off, and after a preset period of time, the eMMC is powered on again.
In this embodiment, in the process of writing the nth test pattern data into each sector in the target dynamic area, the eMMC is powered off, that is, when the nth test pattern data is written into a part of the sectors in the target dynamic area, the eMMC is powered off, and at this time, a part of the sectors in the target dynamic area should have the nth test pattern data written therein, and another part of the sectors should have the nth-1 test pattern data written therein. And after the preset time, the eMMC is powered on again so as to perform data verification on the target dynamic area later, and the power-off data protection performance of the eMMC is tested.
In a possible implementation manner, the determining the power-off time for powering off the eMMC may specifically be that, when the nth test pattern data is written into the target dynamic area, a plurality of write data commands are sent to the eMMC, so as to complete writing of the nth test pattern data into each sector in the target dynamic area. After sending the mth writing data command, the eMMC writes the nth test pattern data to a portion of the sectors of the target dynamic area based on the mth writing data command; randomly selecting a target time as the power-off time during the period that the eMMC writes the Nth test pattern data to a part of the sectors of the target dynamic area based on the Mth write data command, wherein M is preferably 4, 5 or 6; the foregoing randomly selects a target time as the power-off time during writing the N-th test pattern data to the partial sector of the target dynamic area based on the M-th write data command, specifically, may preset a delay time, where the delay time is greater than a time period from receiving a write data command to starting writing the N-th test pattern data to the partial sector of the target dynamic area, and is less than a time period when the eMMC is used to receive and complete a write data command, that is, after the delay time elapses from a time period when the M-th write data command is sent, the eMMC is writing the N-th test pattern data to the partial sector of the target dynamic area based on the M-th write data command, and at this time, the eMMC is powered off, that is, the power-off time; the delay time is generally preset according to information such as specification parameters of the eMMC; the specification parameters include a time period for receiving a write data command of the eMMC, a time period for receiving write data in response to the write data command, and a time period for writing the write data to an area corresponding to the write data command; the specification parameters can be measured by a testing instrument; the test instrument can measure the usage of the eMMC at various stages of the runtime.
It should be appreciated that the power-off time for powering off the eMMC may be randomly set, and the power-off time may be a time during which the eMMC responds to the mth write data command.
In S203, data verification is performed on the target dynamic area.
In this embodiment, the data verification on the target dynamic area may specifically be: scanning the data of the target dynamic region to obtain the current data distribution information of the target dynamic region; determining reference data distribution information according to the power-off time of the power-off of the eMMC in S202, where the reference data distribution information is used to characterize the data distribution of the target dynamic area at the power-off time, that is, if the eMMC has the power-off data protection capability, the data distribution of the target dynamic area should conform to the reference data distribution information at the time; comparing the current data distribution information with the reference data distribution information, if the current data distribution information and the reference data distribution information are the same, the data verification result of the target dynamic area is passed, and if the current data distribution information and the reference data distribution information are different, the data verification result of the target dynamic area is failed.
In S204, if the data verification result of the target dynamic area is failed, the verification status of the test area is identified as failed.
In this embodiment, if the data verification result of the target dynamic area is failed, that is, if a data error occurs in the target dynamic area after the eMMC is powered off, the verification state of the test area is identified as failed, so that it is determined that the test result of the eMMC is failed (that is, the power-off data protection performance of the eMMC does not reach the standard of the test method provided in this embodiment).
In S205, if the data verification results of all the dynamic areas in the test area are passed, performing data verification on all the static areas in the test area.
In this embodiment, if the data verification result of all the dynamic areas in the test area is passed, that is, after the eMMC is powered off, the target dynamic area has no data error, data verification is performed on all the static areas in the test area, so as to further determine the verification state of the test area.
It should be understood that the implementation means for determining the data verification results of all the dynamic areas in the test area may specifically refer to the above-mentioned S201 to S203, and will not be described herein again.
In S206, if the data in all the static areas are the background style data, the verification status of the test area is identified as passing.
In this embodiment, in the step S201, only the target dynamic area is subjected to the data coverage operation, and no data coverage operation is performed on the static area, so that the data in the static area is still the background pattern data filled in the test area in the step S102, and if all the data in the static area are the background pattern data, that is, all the data in the static area are unchanged before and after the power-off operation on the eMMC, that is, all the static areas have a certain power-off protection capability on the stored data, the verification state of the test area is marked as passing.
In this embodiment, by dividing the test area into a plurality of dynamic areas and a plurality of static areas and performing power-off when writing data into the dynamic areas, it is possible to perform a multi-directional power-off data protection test on the test area, that is, to detect the power-off data protection capability of the eMMC when writing new data, and to detect the power-off data protection capability of the eMMC to protect the written data.
Fig. 3 shows a flowchart of an implementation of the test method provided in the third embodiment of the present application. Referring to fig. 3, with respect to the embodiment shown in fig. 2, the test method S203 provided in this embodiment includes S301 to S303, which are specifically described as follows:
Further, the performing data verification on the target dynamic area includes:
in S301, a theoretical writing position corresponding to the power-off time of the eMMC is obtained.
In this embodiment, the power-off time refers to the time of power-off of the eMMC in S202. The obtaining the theoretical writing position corresponding to the power-off time of the eMMC may specifically be: in the process of writing the nth test pattern data into each sector in the target dynamic area, when the nth test pattern data is being written into the target sector in the target dynamic area, the eMMC is powered off, and then the position of the target sector is the theoretical writing position corresponding to the power-off time.
In one possible implementation, writing data to the target dynamic area is performed by sending a write data command to the eMMC, where each write data command corresponds to a fixed writable data size, typically 512KB, and the write data command may be, for example, a command25 (CMD 25) corresponding to the eMMC; the obtaining the theoretical writing position corresponding to the power-off time of the eMMC may specifically be: determining a write-in data command corresponding to the power-off time, and determining a termination write-in position corresponding to the write-in data command, wherein the termination write-in position is the theoretical write-in position.
In S302, an actual writing position is determined according to the data of the target dynamic area.
In this embodiment, the determining the actual writing position according to the data of the target dynamic area may specifically be: scanning the data of the target dynamic region to obtain the current data distribution information of the target dynamic region; and determining the actual writing position according to the current data distribution information, wherein the current data distribution information is used for representing that a part of the target dynamic region stores the N test pattern data and another part of the target dynamic region stores the N-1 test pattern data, namely the junction of the N test pattern data and the N-1 test pattern data is the actual writing position.
In S303, if the difference between the theoretical writing position and the actual writing position is greater than the preset allowable error value, the data verification result of the target dynamic area is identified as failed.
In this embodiment, the allowable error value is a preset value, and is preferably a sum of the write data amount corresponding to the single write data command and three times the data amount of the cache in the eMMC, generally, the write data amount corresponding to the single write data command is 512KB, the data amount of the cache is 32KB, and the allowable error value is 512kb+3x32kb=608 KB.
It should be understood that if the difference between the theoretical writing location and the actual writing location is less than or equal to the preset allowable error value, the data verification result of the target dynamic area is identified as passing.
In order to better explain the test method provided in this embodiment, referring to fig. 4, fig. 4 shows a schematic structural diagram of an eMMC provided in the third embodiment of the present application, and referring to fig. 4, the eMMC includes 2 BOOT areas, 1 RPMB area, 4 GPP areas, and 1 UDA area, where the test area in the UDA area has a plurality of dynamic areas and a plurality of static areas, for example, a 0-dynamic area in the drawing is taken as a target dynamic area, each solid horizontal line in the target dynamic area in the drawing represents a writable data amount corresponding to a write data command, all solid vertical lines represent sectors in S201 in which N test pattern data are sequentially written in the target dynamic area, all data writing processes in the target dynamic area are performed from top to bottom, where the rightmost vertical line represents a process of writing N test pattern data in the target dynamic area, and the middle stops because the eMMC is powered off in S202, where the illustrated allowable error value is a bottom line is the theoretical write position, and the actual write position is the write position of the vertical line.
In this embodiment, by setting the allowable error value specifically, compared with the test method in the prior art, the additional requirement of the test method provided by this embodiment is added, so that the test effect of the test method is better, and the power-off data protection performance of the eMMC by the test method provided by this embodiment is better verified.
Fig. 5 shows a flowchart of an implementation of the test method provided in the fourth embodiment of the present application. Referring to fig. 5, with respect to the embodiment shown in fig. 1, the test method provided in this embodiment further includes S501 to S502, which are specifically described as follows:
further, determining a test result of the eMMC based on the verification state of the test area includes:
in S501, a test result of the target area is determined based on the verification state of the test area.
In this embodiment, if the verification status of the test area is passed, it is indicated that the test for the target area is passed, that is, the test result of the target area is passed; if the verification state of the test area is failed, the data error exists in the target area, that is, the test result of the target area is failed.
In one possible implementation manner, the determining the test result of the target area based on the verification state of the test area may specifically be: if the verification state of the test area is passing, data verification is carried out on the non-test area in the target area, and if the verification state of the non-test area is passing, the test result of the target area is passing; if the verification state of the test area is failed, the test result of the target area is failed. The implementation means of the data verification in the non-test area may specifically refer to the description related to S104, which is not repeated here.
In S502, a test result of the eMMC is determined based on the test results of all partitions in the eMMC.
In this embodiment, in order to further verify the power-off protection performance of the eMMC with the passed test result, it is insufficient to only use one target area as a test object, and it is necessary to test all the partitions in the eMMC as test objects, specifically, determine the test results corresponding to all the partitions in the eMMC, and determine the test result of the eMMC based on the test results of all the partitions in the eMMC.
In one possible implementation manner, before determining the test result of the eMMC based on the test results of all the partitions in the eMMC, the method includes: the specific implementation may refer to S101 to S103 and S501 described above, which are not described herein again. The determining the test result of the eMMC based on the test results of all the partitions in the eMMC may specifically be: if the test results of all the partitions in the eMMC are passed, the test results of the eMMC are passed; if the test result of any partition in the eMMC is failed, the test result of the eMMC is failed.
In this embodiment, the test result of the eMMC is determined by determining the test results of all the partitions of the eMMC, and according to the test results of all the partitions of the eMMC, the power-off protection performance of the eMMC that the test result is passed is further verified.
Fig. 6 shows a flowchart of an implementation of the test method provided in the fifth embodiment of the present application. Referring to fig. 6, with respect to the embodiment described in fig. 1, the test method provided in this embodiment further includes S601, which is specifically described as follows:
further, before the determining the test area in the target area of the eMMC based on the random algorithm, the method further includes:
in S601, power-on initialization processing is performed on the eMMC, and the working state of the eMMC is adjusted to a transmission state.
In this embodiment, generally, for an eMMC to be tested, it is guaranteed that the operation state of the eMMC is adjusted to a transfer (transfer) state when the test is performed, so that data is written into a target area in the eMMC later.
In this embodiment, the power-on initialization process is performed on the eMMC, so as to adjust the working state of the eMMC to the transmission state, so that the subsequent test of the eMMC with the shutdown electric data protection performance is performed.
Fig. 7 shows a flowchart of an implementation of the test method provided in the sixth embodiment of the present application. Referring to fig. 7, with respect to the embodiment shown in fig. 1, the test method provided in this embodiment further includes S701, and the test method S104 provided in this embodiment includes S702, which is specifically described as follows:
in S701, the number of verification cycles is acquired to generate a verification state of the test area determined per verification cycle.
In this embodiment, the verification cycle number is used to determine a cycle number for executing the determination of the test area within the target area of the eMMC based on a random algorithm; the number of verification cycles may be preset.
In this embodiment, in order to ensure the test effect on the power-off data protection performance of the eMMC, multiple tests are required, and thus the verification cycle number needs to be preset. The specific implementation of the verification state of the test area determined by each verification period may refer to the descriptions related to S101 to S103, which are not described herein.
In one possible implementation manner, the test area determined by each verification period may come from different partitions in the eMMC, so as to increase the total range of the test areas of all verification periods, and improve the test effect on the eMMC.
Further, the determining the test result of the eMMC based on the verification state of the test area includes:
in S702, a test result of the eMMC is determined based on the verification states of the plurality of test areas randomly determined for each verification period.
In this embodiment, the determining, based on the verification states of the plurality of test areas determined randomly in each verification period, the test result of the eMMC may specifically be: if the verification state of the test area corresponding to any verification period is failed, the test result of the eMMC is failed; if the verification states of the test areas corresponding to all the verification periods are passed, the test result of the eMMC is passed.
In this embodiment, the test result of the eMMC is determined according to the verification states of the plurality of test areas randomly determined in each verification period, so that the accuracy of the test result is improved, and the test effect on the eMMC is better.
Fig. 8 shows a flowchart of an implementation of the test method provided in the seventh embodiment of the present application. Referring to fig. 8, with respect to the embodiment illustrated in fig. 7, the test method S702 provided in this embodiment includes S801 to S803, which are specifically described as follows:
further, the determining the test result of the eMMC based on the verification states of the plurality of test areas randomly determined in each verification period includes:
In S801, if the verification status of the test area corresponding to any verification period is failed, it is determined that the test result of the eMMC is failed.
In this embodiment, in order to improve the accuracy of the test result of the eMMC determined later, the test result is determined as failed in any verification period where the verification status of the test area corresponding to the verification period is failed.
In S802, if the verification states of the test areas corresponding to all the verification periods are passed, data verification is performed on the target area.
In this embodiment, if the verification states of the test areas corresponding to all the verification periods are passed, it is indicated that the data in the target area has no data error due to power failure; in order to further improve the accuracy of the test result of the eMMC determined later, data verification is performed on the target area at this time. The specific implementation of the data verification on the target area may refer to the above-mentioned part of the term explanation related to the present application, and will not be described herein.
In S803, a test result of the eMMC is determined based on the data verification result of the target area.
In this embodiment, the determining the test result of the eMMC based on the data verification result of the target area may specifically be: if the data verification result of the target area is passing, the test result of the eMMC is passing; if the data verification result of the target area is failed, the test result of the eMMC is failed; that is, only the data verification result of the target area is passed, the test result of the eMMC is passed.
In this embodiment, by increasing the data verification on the target area, the accuracy of the test result is further improved, so that the test effect on the eMMC is better, and the power-off data protection capability of the eMMC that passes the data verification is further verified.
Fig. 9 is a schematic logic flow diagram of an application scenario provided in an embodiment of the present application, and referring to fig. 9, fig. 9 details specific logic steps when a test method provided in an embodiment of the present application is executed in the application scenario, and referring to fig. 9, when the test method provided in an embodiment of the present application is started to be executed, the details are as follows:
step 1: carrying out power-on initialization processing on the eMMC so as to adjust the working state of the eMMC to a transmission state, so that the eMMC is subjected to data transmission subsequently;
step 2: determining a target area of the eMMC based on a random algorithm, and determining a test area of the target area;
step 3: writing the bottom pattern data into each sector in the target area, and writing the background pattern data into each sector in the test area;
step 4: performing power-off test on the test area, and if the current test times j are smaller than the preset verification cycle number, continuing to execute the step 5; if the current test times j reach the preset verification cycle number, executing the step 12;
Step 5: the initial value of i is 1; randomly generating ith test pattern data, writing the ith test pattern data into a target dynamic area, and repeatedly executing the step 5 by adding the value of i if i is less than N; if i=n, executing the next step;
step 6: transmitting a plurality of write data commands to the eMMC to write the nth test pattern data to the target dynamic area; executing the next step when the Mth write data command is transmitted;
step 7: after the sending time of the Mth writing data command passes through a preset delay time, the eMMC is powered off;
step 8,: after a preset time period passes, the eMMC is electrified again;
step 9: performing data verification on the target dynamic region; if the data verification is passed, executing the next step; if the data verification is not passed, identifying that the eMMC fails the test;
step 10: detecting whether the target dynamic region is the last dynamic region in the test region, if not, identifying the next dynamic region of the target dynamic region as a new target dynamic region, and returning to the step 5, namely ensuring that all dynamic regions in the test region need to pass through the steps 5-9; if the target dynamic region is the last dynamic region in the test region, executing the next step;
Step 11: data verification is carried out on all static areas in the test area; if the data verification is passed, the value of the test times j is increased by one, and the step 4 is returned; if the data verification is not passed, identifying that the eMMC fails the test;
step 12: performing data verification on the target area, and if the data verification is passed, identifying that the eMMC passes the test; and if the data verification is not passed, identifying that the eMMC fails the test.
The relevant description refers to the relevant description in all the embodiments described above, and is not limited herein.
Corresponding to the method described in the above embodiments, fig. 10 shows a schematic structural diagram of a test device provided in an embodiment of the present application, and for convenience of explanation, only the portions related to the above embodiments of the present application are shown.
Referring to fig. 10, the test apparatus includes: the test area determining module is used for determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; the style data writing module is used for writing the bottom style data into each sector in the target area and writing the background style data into each sector in the test area; the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area; and the test result determining module is used for determining the test result of the eMMC based on the verification state of the test area.
Optionally, the power-off verification module includes: the data writing module is used for randomly generating N pieces of test pattern data and writing the N pieces of test pattern data into each sector in the target dynamic area in sequence; the N is an integer greater than 1; the target dynamic region is any dynamic region in the test region; the power-off and power-on module is used for powering off the eMMC in the process of writing the Nth test pattern data into each sector in the target dynamic area, and re-powering on the eMMC after a preset time length; the data verification module is used for carrying out data verification on the target dynamic region; if the data verification result of the target dynamic area is not passed, marking that the verification state of the test area is not passed; if the data verification results of all the dynamic areas in the test area are passed, performing data verification on all the static areas in the test area; and if the data in all the static areas are the background pattern data, identifying that the verification state of the test area is passed.
Optionally, the data verification module includes: the reference data module is used for acquiring a theoretical writing position corresponding to the power-off time of the eMMC; the scanning data module is used for determining the actual writing position according to the data of the target dynamic area; and the data analysis module is used for identifying the data verification result of the target dynamic area as failed if the difference value between the theoretical writing position and the actual writing position is larger than a preset allowable error value.
Optionally, the test result determining module includes: the target area test result determining module is used for determining a test result of the target area based on the verification state of the test area; and the module is used for determining the test result of the eMMC based on the test results of all the partitions in the eMMC. Optionally, the test device further includes: and the initialization module is used for carrying out power-on initialization processing on the eMMC and adjusting the working state of the eMMC to a transmission state.
Optionally, the test device further includes: the verification cycle number acquisition module is used for acquiring the verification cycle number to generate a verification state of the test area determined by each verification cycle; the verification cycle number is used for determining the cycle number of executing the test area in the target area of the eMMC based on a random algorithm; the test result determining module is further used for determining test results of the eMMC based on verification states of the plurality of test areas determined randomly in each verification period.
Optionally, the test result determining module is further configured to determine that the test result of the eMMC is failed if the verification status of the test area corresponding to any verification period is failed; if the verification states of the test areas corresponding to all the verification periods are passed, the data verification module is instructed to perform data verification on the target area; and determining a test result of the eMMC based on the data verification result of the target area.
It should be noted that, because the content of information interaction and execution process between the devices is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
Fig. 11 shows a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 11, the terminal device 11 of this embodiment includes: at least one processor 110 (only one processor is shown in fig. 11), a memory 111 and a computer program 112 stored in the memory 111 and executable on the at least one processor 110, the processor 110 implementing the steps in any of the various method embodiments described above when executing the computer program 112.
The terminal device 11 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, etc. The terminal device may include, but is not limited to, a processor 110, a memory 111. It will be appreciated by those skilled in the art that fig. 11 is merely an example of the terminal device 11 and is not meant to be limiting as to the terminal device 11, and may include more or fewer components than shown, or may combine certain components, or may include different components, such as input-output devices, network access devices, etc.
The processor 110 may be a central processing unit (Central Processing Unit, CPU), the processor 110 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 111 may in some embodiments be an internal storage unit of the terminal device 11, such as a hard disk or a memory of the terminal device 11. The memory 111 may in other embodiments also be an external storage device of the terminal device 11, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal device 11. Further, the memory 111 may also include both an internal storage unit and an external storage device of the terminal device 11. The memory 111 is used to store an operating system, application programs, boot loader (BootLoader), data, and other programs, etc., such as program codes of the computer program. The memory 111 may also be used to temporarily store data that has been output or is to be output.
Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements steps that may implement the various method embodiments described above.
Embodiments of the present application provide a computer program product which, when run on a mobile terminal, causes the mobile terminal to perform steps that may be performed in the various method embodiments described above.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application implements all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/terminal apparatus, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (8)
1. A method for testing eMMC, comprising:
determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC;
writing the bottom pattern data into each sector in the target area, and writing the background pattern data into each sector in the test area;
Performing power-off verification operation on the test area to obtain a verification state of the test area;
acquiring verification cycle numbers to generate verification states of the test areas determined by each verification cycle; the verification cycle number is used for determining the cycle number of executing the test area in the target area of the eMMC based on a random algorithm;
if the verification state of the test area corresponding to any verification period is failed, determining that the test result of the eMMC is failed;
if the verification states of the test areas corresponding to all the verification periods are passed, carrying out data verification on the target area;
and determining a test result of the eMMC based on the data verification result of the target area.
2. The test method of claim 1, wherein the test area comprises a plurality of dynamic areas and a plurality of static areas; and executing power-off verification operation on the test area to obtain a verification state of the test area, wherein the power-off verification operation comprises the following steps:
randomly generating N pieces of test pattern data and sequentially writing the N pieces of test pattern data into each sector in the target dynamic area; the N is an integer greater than 1; the target dynamic region is any dynamic region in the test region;
In the process of writing the Nth test pattern data into each sector in the target dynamic area, powering off the eMMC, and powering on the eMMC again after a preset time period;
performing data verification on the target dynamic region;
if the data verification result of the target dynamic area is not passed, marking that the verification state of the test area is not passed;
if the data verification results of all the dynamic areas in the test area are passed, performing data verification on all the static areas in the test area;
and if the data in all the static areas are the background pattern data, identifying that the verification state of the test area is passed.
3. The method of testing as claimed in claim 2, wherein said data verification of said target dynamic region comprises:
acquiring a theoretical writing position corresponding to the power-off time of the eMMC;
determining an actual writing position according to the data of the target dynamic area;
and if the difference value between the theoretical writing position and the actual writing position is larger than a preset allowable error value, identifying the data verification result of the target dynamic area as failed.
4. The test method of any one of claims 1-3, wherein the determining the test result of the eMMC based on the verification status of the test area comprises:
determining a test result of the target area based on the verification state of the test area;
and determining the test result of the eMMC based on the test results of all the partitions in the eMMC.
5. The test method of claim 1, wherein prior to the determining the test region within the eMMC target region based on the random algorithm, further comprising:
and carrying out power-on initialization processing on the eMMC and adjusting the working state of the eMMC to a transmission state.
6. A test device, comprising:
the test area determining module is used for determining a test area in the target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC;
the style data writing module is used for writing the bottom style data into each sector in the target area and writing the background style data into each sector in the test area;
the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area;
The verification cycle number acquisition module is used for acquiring the verification cycle number to generate a verification state of the test area determined by each verification cycle; the verification cycle number is used for determining the cycle number of executing the test area in the target area of the eMMC based on a random algorithm;
the test result determining module is used for determining that the test result of the eMMC is failed if the verification state of the test area corresponding to any verification period is failed; if the verification states of the test areas corresponding to all the verification periods are passed, carrying out data verification on the target area; and determining a test result of the eMMC based on the data verification result of the target area.
7. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 5 when executing the computer program.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 5.
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