CN112133357A - eMMC testing method and device - Google Patents
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- CN112133357A CN112133357A CN202011066427.3A CN202011066427A CN112133357A CN 112133357 A CN112133357 A CN 112133357A CN 202011066427 A CN202011066427 A CN 202011066427A CN 112133357 A CN112133357 A CN 112133357A
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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Abstract
The application is suitable for the field of memory pieces, and provides an eMMC testing method and device, wherein the testing method comprises the following steps: determining a test area in a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; writing bottom pattern data into each sector in the target area, and writing background pattern data into each sector in the test area; performing power-off verification operation on the test area to obtain a verification state of the test area; determining a test result of the eMMC based on a verification status of the test area. This application tests through selecting the test area at random, increases and selects the probability as the test area to the abnormal region, can improve the test effect, solves among the prior art through the not good effect that leads to probably having the eMMC that causes the data error of outage when the in-service use of outage verification test eMMC's outage data protection performance.
Description
Technical Field
The application belongs to the field of memory parts, and particularly relates to an eMMC testing method and device.
Background
eMMC (Embedded multimedia Card) is commonly used in mobile phones, tablet computers, communication devices as a storage device. These devices often have a power failure, and if power is cut off during normal writing of data to the eMMC, data errors, anomalies, and the like may be caused, thereby reducing the stability of the device. Therefore, the eMMC needs to be subjected to power-off performance testing to ensure that the eMMC has strong power-off protection capability.
However, in the eMMC test in the prior art, when the power is off, generally, fixed pattern data is written into a fixed area with a fixed size in the eMMC to perform power-off test verification, such power-off test verification is not strict enough, which may cause data errors caused by power-off of the eMMC passing the power-off test verification during actual use, that is, the test effect of the power-off test verification is not good enough.
Disclosure of Invention
The embodiment of the application provides a testing method and device of eMMC, tests through selecting the test area at random, can improve the test effect, solves the problem that the poor effect of testing the power-off data protection performance of the eMMC through power-off verification in the prior art leads to the fact that the tested eMMC is powered off and causes data errors when in actual use.
In a first aspect, an embodiment of the present application provides a method for testing an eMMC, including: determining a test area in a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; writing bottom pattern data into each sector in the target area, and writing background pattern data into each sector in the test area; performing power-off verification operation on the test area to obtain a verification state of the test area; determining a test result of the eMMC based on a verification status of the test area.
In one possible implementation manner of the first aspect, the determining a test result of the eMMC based on the verification status of the test area includes: and determining the test result of the eMMC based on the verification states of the test areas corresponding to all the partitions of the eMMC.
It should be understood that, generally, only one partition, i.e., a target area, of the eMMC needs to be randomly selected, and a test result of the eMMC can be determined based on a verification state of a test area corresponding to the target area. In the above possible implementation manner, the test result of the eMMC is determined based on the verification states of the test areas corresponding to all the partitions of the eMMC, that is, the test result of the eMMC passes only when the verification states of the test areas corresponding to all the partitions of the eMMC pass, so that the test is relatively stricter, the efficiency of the test is reduced, the resource consumption is increased, and the test method provided by the possible implementation manner can be executed as required.
In a second aspect, an embodiment of the present application provides a testing apparatus for an eMMC, including: a test area determination module for determining a test area within a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; the pattern data writing module is used for writing the bottom pattern data into each sector in the target area and then writing the background pattern data into each sector in the test area; the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area; a test result determination module to determine a test result of the eMMC based on a verification status of the test area.
In a third aspect, an embodiment of the present application provides a terminal device, including: a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the method of any of the above first aspects when executing the computer program.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including: the computer readable storage medium stores a computer program which, when executed by a processor, implements the method of any of the first aspects described above.
In a fifth aspect, the present application provides a computer program product, which when run on a terminal device, causes the terminal device to execute the method of any one of the above first aspects.
It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.
Compared with the prior art, the embodiment of the application has the advantages that:
compared with the prior art, the test method provided by the application has the advantages that the test is carried out by randomly selecting the test area, the probability of selecting the abnormal area as the test area is increased, the test effect can be improved, and the problem that the eMMC possibly subjected to test is powered off to cause data errors when the eMMC is actually used due to poor power-off verification test effect in the prior art is solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a flow chart of an implementation of a testing method provided in a first embodiment of the present application;
FIG. 2 is a flow chart of an implementation of a testing method provided in a second embodiment of the present application;
FIG. 3 is a flow chart of an implementation of a testing method provided in the third embodiment of the present application;
fig. 4 is a schematic structural diagram of an eMMC provided in a third embodiment of the present application;
FIG. 5 is a flowchart of an implementation of a testing method provided in the fourth embodiment of the present application;
FIG. 6 is a flow chart of an implementation of a testing method provided in a fifth embodiment of the present application;
FIG. 7 is a flowchart of an implementation of a testing method provided in the sixth embodiment of the present application;
FIG. 8 is a flowchart of an implementation of a testing method provided in the seventh embodiment of the present application;
FIG. 9 is a schematic logic flow diagram of an application scenario provided by an embodiment of the present application;
FIG. 10 is a schematic structural diagram of a testing apparatus according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to" determining "or" in response to detecting ". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.
The explanation of the terms related to the present application will be briefly described herein. "data validation" generally refers to scanning data of an object region to obtain current data distribution information of the object region; determining a verification result of the data verification according to the current data distribution information, which may specifically be: comparing the current data distribution information with reference data distribution information corresponding to the data verification, wherein if the current data distribution information is the same as the reference data distribution information, the verification result of the data verification is passed, and if the current data distribution information is different from the reference data distribution information, the verification result of the data verification is failed; the reference data distribution information may be obtained by recording history data write information. It should be understood that the feature definition of "data verification" in the third embodiment is different from the general "data verification" described above, and the specific details can be referred to the description in the third embodiment. "writing certain data to each sector in a certain area" means writing the certain data to the certain area until the certain area is filled with the certain data; generally, the eMMC starts receiving data by sending a write data command to the eMMC.
In the embodiment of the present application, the main execution body of the flow is a terminal device. The terminal devices include but are not limited to: the device comprises a server, a computer, a smart phone, a tablet computer and the like, wherein the server, the computer, the smart phone, the tablet computer and the like can execute the test method provided by the application; the terminal device is preferably a device equipped with an uboot system (boot loader of an embedded system), and the test method provided by this embodiment is preferably executed by an ODROID XU4 development board platform of the uboot system. Fig. 1 shows a flowchart of an implementation of the testing method provided in the first embodiment of the present application, which is detailed as follows:
in S101, a test area within the target area of the eMMC is determined based on a random algorithm.
In this embodiment, the target area is any partition of the eMMC. For example, according to the eMMC standard, a partition of the eMMC may include 8 Partitions including 2 Boot Area Partitions (boots), 1 Replay Protected Memory Block (RPMB), 4 General Purpose Partitions (GPP), and 1 User Data Area (UDA), in which case the target Area may be any one of the above-described Partitions. In a possible implementation manner, the determining a test region in the target region of the eMMC based on the random algorithm may specifically be: dividing the target area into a plurality of candidate areas based on the size of the target area, and randomly selecting one of the candidate areas as the test area based on a random algorithm; optionally, the larger the storage space of the target area is, the larger the number of the divided candidate areas is; alternatively, when dividing a plurality of candidate regions, the size of the storage space of each candidate region may be the same. It should be understood that the random algorithm may be any algorithm that can randomly select one of the plurality of regions as the test region, and is not limited herein.
In S102, the underlying pattern data is written into each sector in the target area, and then the background pattern data is written into each sector in the test area.
In this embodiment, the base style data and the background style data are preset style data; the writing of the bottom pattern data into each sector in the target area and the writing of the background pattern data into each sector in the test area may specifically be: writing the bottom-layer style data into the target area to make the target area filled with the bottom-layer style data; for example, if the base pattern data may be 0x77, the base pattern data is filled into each sector, so that the target area is filled with the base pattern data; typically, the size of the sector is 512 bytes.
At this time, the test area in the target area is filled with the underlying pattern data, and then the background pattern data is written into the test area, that is, the background pattern data covers all the underlying pattern data in the test area, so that the test area is filled with the background pattern data. It is emphasized that the base style data is different from the background style data, for example, the base style data may be 0x77, and the background style data may be 0x 88.
It should be understood that the underlying pattern data and the background pattern data are used to distinguish the target area and the test area in the data distribution, so as to facilitate the subsequent power-off verification operation of the test area.
In S103, a power-off verification operation is performed on the test area to obtain a verification state of the test area.
In a possible implementation manner, the power-off verification operation may specifically be: writing test pattern data into each sector in the test area, powering off the eMMC in the process of writing the test pattern data into each sector in the test area, and powering on the eMMC again after preset time; after the power-off operation and the power-on operation are executed, performing data verification on the test area, and specifically determining current data distribution information in the test area; determining reference data distribution information of the data verification according to the power-off time; comparing the current data distribution information with the reference data distribution information, if the current data distribution information is the same as the reference data distribution information, the verification result of the data verification is passed, namely the verification state of the test area is passed, and if the current data distribution information is different from the reference data distribution information, the verification result of the data verification is not passed, namely the verification state of the test area is not passed.
It should be understood that the test pattern data is different from the base pattern data and the background pattern data, for example, the base pattern data may be 0x77, the background pattern data may be 0x88, and the test pattern data may be 0x 66.
In S104, a test result of the eMMC is determined based on the verification status of the test area.
In this embodiment, the determining the test result of the eMMC based on the verification status of the test area may specifically be: if the verification state of the test area is passed, performing data verification on a non-test area in the target area, wherein the non-test area is other areas except the test area in the target area; if the verification state of the non-test area is pass, the test result of the eMMC is pass; if the verification state of the non-test area is failed, the test result of the eMMC is failed; if the verification status of the test area is failed, the test result of the eMMC is failed. The data verification of the non-test area is performed, specifically, whether the non-test area is full of the underlying pattern data is verified, if the data in the non-test area is the underlying pattern data, the verification state of the non-test area is passed, otherwise, the verification state of the non-test area is failed.
It should be understood that, in a possible implementation manner, before S104, S101 to S103 are executed multiple times to obtain verification statuses of multiple test areas, and if the verification status of any test area is failed, the test result of the eMMC is determined to be failed; if the verification status of all the test areas is passed, the test result of the eMMC is passed.
In this embodiment, a test area in a target area of the eMMC is randomly determined, and a power-off verification operation is performed on the test area to determine a test result of the eMMC; compared with the prior art, the uncertainty of the test area can be increased, so that more possible areas can receive power-off verification operation, the test result of the eMMC is determined, the probability of selecting an abnormal area as the test area can be increased on the premise of not increasing the resource consumption of the test (not increasing the size of the test area), the test effect is improved, and the problem that when the power-off data protection performance of the eMMC is tested through power-off verification in the prior art, the test area is fixed, so that the tested eMMC is possibly powered off to cause data errors in actual use is solved.
Fig. 2 shows a flowchart of an implementation of the testing method provided in the second embodiment of the present application. Referring to fig. 2, with respect to the embodiment shown in fig. 1, the test method S103 provided in this embodiment includes S201 to S206, which are detailed as follows:
in this embodiment, the test area includes a plurality of dynamic areas and a plurality of static areas.
Further, the performing a power-off verification operation on the test area to obtain a verification state of the test area includes:
in S201, N test pattern data are randomly generated and written into each sector in the target dynamic area in sequence.
In this embodiment, N is an integer greater than 1, preferably 3 or 4 or 5, and N is preset; the target dynamic region is any dynamic region in the test region.
In this embodiment, the step of randomly generating N test pattern data and the step of writing the N test pattern data into each sector in the target dynamic area sequentially may be performed asynchronously, specifically, the terminal device randomly generates N test pattern data, which are respectively the first test pattern data to the nth test pattern data, and then writes the N test pattern data into each sector in the target dynamic area sequentially, specifically, first writes the first test pattern data into each sector in the target dynamic area, then writes the second test pattern data into each sector in the target dynamic area …, and so on, and finally writes the nth test pattern data into each sector in the target dynamic area.
In a possible manner, the step of randomly generating N test pattern data and the step of sequentially writing the N test pattern data into each sector in the target dynamic area may be performed synchronously, specifically, the terminal device randomly generates first test pattern data, writes the first test pattern data into each sector in the target dynamic area, randomly generates second test pattern data …, and so on, and finally randomly generates nth test pattern data and writes the nth test pattern data into each sector in the target dynamic area.
In S202, the eMMC is powered off during the process of writing the nth test pattern data into each sector in the target dynamic region, and the eMMC is powered on again after a preset time duration.
In this embodiment, the eMMC is powered off during the writing of the nth test pattern data into each sector in the target dynamic region, that is, the eMMC is powered off when the nth test pattern data is written into a part of sectors of the target dynamic region, at this time, a part of sectors of the target dynamic region should have the nth test pattern data written therein, and another part of sectors should have the nth-1 test pattern data written therein. The eMMC is powered on again after the preset time length so as to carry out data verification on the target dynamic area subsequently, and the power-off data protection performance of the eMMC is tested.
In a possible implementation manner, determining the power-off time for powering off the eMMC may specifically be, when the nth test pattern data is written in the target dynamic area, sending a plurality of write data commands to the eMMC to complete writing the nth test pattern data in each sector in the target dynamic area. After sending the mth write data command, the eMMC writes the nth test pattern data to a partial sector of the target dynamic region based on the mth write data command; randomly selecting a target time as the power-off time during the period of writing the Nth test pattern data into the partial sector of the target dynamic area by the eMMC based on the Mth write data command, wherein M is preferably 4, 5 or 6; the aforementioned randomly selecting a target time as the power-off time during the period when the eMMC writes the nth test pattern data to the partial sector of the target dynamic region based on the mth write data command, specifically, a delay time may be preset, where the delay time is greater than a time used by the eMMC from receiving a write data command to starting writing the nth test pattern data to the partial sector of the target dynamic region and is less than a time used by the eMMC for receiving and completing a write data command, that is, after the delay time elapses from the sending time of the mth write data command, the eMMC is writing the nth test pattern data to the partial sector of the target dynamic region based on the mth write data command, and at this time, the eMMC is powered off, and the time at this time is the power-off time; the delay time is generally preset according to information such as the eMMC specification parameters; the specification parameters include a time spent by the eMMC for receiving a write data command, a time spent for responding to the write data command, a time spent for receiving write data, and a time spent for writing the write data into an area corresponding to the write data command; the specification parameters can be measured by a test instrument; the test instrument can measure the time of use of the eMMC at various stages of operation.
It should be appreciated that the power-down time for powering down the eMMC may be randomly set, and the power-down time may be a certain time during which the eMMC responds to the mth write data command.
In S203, data verification is performed on the target dynamic region.
In this embodiment, the data verification on the target dynamic region may specifically be: scanning the data of the target dynamic area to obtain the current data distribution information of the target dynamic area; determining reference data distribution information according to the power-off time of powering off the eMMC in S202, where the reference data distribution information is used to represent the due data distribution of the target dynamic region at the power-off time, that is, if the eMMC has power-off data protection capability, the data distribution of the target dynamic region at this time should conform to the reference data distribution information; and comparing the current data distribution information with the reference data distribution information, wherein if the current data distribution information is the same as the reference data distribution information, the data verification result of the target dynamic area is passed, and if the current data distribution information is different from the reference data distribution information, the data verification result of the target dynamic area is failed.
In S204, if the data verification result of the target dynamic region is failed, the verification status of the test region is identified as failed.
In this embodiment, if the data verification result of the target dynamic area is failed, that is, if the data error occurs in the target dynamic area after the eMMC is powered off, the verification status of the test area is identified as failed, so as to subsequently determine that the test result of the eMMC is failed (that is, the power-off data protection performance of the eMMC does not meet the standard of the test method provided in this embodiment).
In S205, if the data verification results of all the dynamic areas in the test area are passed, data verification is performed on all the static areas in the test area.
In this embodiment, if the data verification results of all the dynamic areas in the test area are passed, that is, no data error occurs in the target dynamic area after the eMMC is powered off, the data verification is performed on all the static areas in the test area, so as to further determine the verification status of the test area.
It should be understood that, the implementation means for determining the data verification results of all dynamic regions in the test region may specifically refer to the above S201 to S203, and will not be described herein again.
In S206, if the data in all the static areas are the background style data, the verification status of the test area is identified as pass.
In this embodiment, in the above step S201, only the data coverage operation is performed on the target dynamic area, and the data coverage operation is not performed on the static area, so that the data in the static area is still the background pattern data filled in the test area in step S102, and at this time, if the data in all the static areas are the background pattern data, that is, the data in all the static areas are not changed before and after the power-off of the eMMC, that is, all the static areas have a certain power-off protection capability for the stored data, the verification state of the test area is identified as pass.
In this embodiment, the test area is divided into a plurality of dynamic areas and a plurality of static areas, and power is turned off when data is written into the dynamic areas, so that a multi-directional power-off data protection test can be performed on the test area, that is, the power-off data protection capability of the eMMC when new data is written into the eMMC is detected, and the power-off data protection capability of the eMMC for protecting the written data is detected.
Fig. 3 shows a flowchart of an implementation of the testing method provided in the third embodiment of the present application. Referring to fig. 3, in comparison with the embodiment shown in fig. 2, the test method S203 provided in this embodiment includes S301 to S303, which are detailed as follows:
further, the data verification of the target dynamic region includes:
in S301, a theoretical write position corresponding to the power-off time of the eMMC is acquired.
In this embodiment, the power-off time refers to the time when the eMMC is powered off in S202. The obtaining of the theoretical write position corresponding to the power-off time of the eMMC may specifically be: in the process of writing the nth test pattern data into each sector in the target dynamic area, the eMMC is powered off when the nth test pattern data is being written into the target sector in the target dynamic area, and the position of the target sector is the theoretical writing position corresponding to the power-off time.
In one possible implementation, writing data to the target dynamic region may be performed by sending write data commands to the eMMC, where each write data command corresponds to a fixed writable data size, typically 512KB, and may be, for example, command number 25 (command25, CMD25) corresponding to the eMMC; the obtaining of the theoretical write position corresponding to the power-off time of the eMMC may specifically be: and determining a write-in data command corresponding to the power-off moment, and determining a write-termination position corresponding to the write-in data command, wherein the write-termination position is the theoretical write-in position.
In S302, an actual writing position is determined according to the data of the target dynamic region.
In this embodiment, the determining the actual writing position according to the data of the target dynamic area may specifically be: scanning the data of the target dynamic area to obtain the current data distribution information of the target dynamic area; and determining the actual writing position according to the current data distribution information, specifically, the current data distribution information is used for representing that a part of the target dynamic region stores the nth test pattern data, and another part of the target dynamic region stores the N-1 test pattern data, that is, the boundary between the nth test pattern data and the N-1 test pattern data is the actual writing position.
In S303, if the difference between the theoretical writing position and the actual writing position is greater than a preset allowable error value, the data verification result of the target dynamic region is identified as failed.
In this embodiment, the allowable error value is a preset value, and the allowable error value is preferably a sum of the write data size corresponding to a single write data command and three times the cached data size in the eMMC, generally, the write data size corresponding to a single write data command is 512KB, the cached data size is 32KB, and the allowable error value is 512KB +3 × 32KB — 608 KB.
It should be understood that if the difference between the theoretical writing position and the actual writing position is less than or equal to a preset allowable error value, the data verification result of the target dynamic region is identified as passing.
To better explain the testing method provided by this embodiment, refer to fig. 4, fig. 4 shows a schematic structural diagram of an eMMC provided by a third embodiment of the present application, refer to fig. 4, the eMMC includes 2 BOOT regions, 1 RPMB region, 4 GPP regions, and 1 UDA region, the testing region in the UDA region has a plurality of dynamic regions and a plurality of static regions, exemplarily, 0-dynamic region in the figure is taken as a target dynamic region, each solid horizontal line in the target dynamic region in the diagram represents a writable data amount corresponding to a write data command, all solid vertical lines represent respective sectors in S201 that sequentially write N test pattern data into the target dynamic region, data writing processes of all the target dynamic regions are performed from top to bottom, wherein the rightmost solid vertical line represents a process that the nth test pattern data is written into the target dynamic region, the reason why the middle stop is because the eMMC is powered off in S202, the bottom line of the allowable error value shown in the figure at this time is the theoretical write position, and the position where the end point of the vertical solid line is located is the actual write position.
In this embodiment, by particularly setting the allowable error value, compared with the test method in the prior art, the additional requirement of the test method provided by this embodiment is added, so that the test effect of the test method is better, and the power-off data protection performance of the eMMC of the test method provided by this embodiment is better verified.
Fig. 5 shows a flowchart of an implementation of the testing method provided in the fourth embodiment of the present application. Referring to fig. 5, with respect to the embodiment shown in fig. 1, the test method provided in this embodiment further includes S501 to S502, which are detailed as follows:
further, determining a test result of the eMMC based on the verification status of the test area includes:
in S501, a test result of the target area is determined based on the verification status of the test area.
In this embodiment, if the verification status of the test area is "pass", it indicates that the test for the target area is "pass", that is, the test result of the target area is "pass"; if the verification status of the test area is failed, it indicates that the target area has data errors, i.e. the test result of the target area is failed.
In a possible implementation manner, the determining the test result of the target area based on the verification status of the test area may specifically be: if the verification state of the test area is passed, performing data verification on a non-test area in the target area, and if the verification state of the non-test area is passed, determining that the test result of the target area is passed; and if the verification state of the test area is failed, the test result of the target area is failed. The implementation means for performing data verification on the non-test area specifically refers to the related description of S104, and is not described herein again.
In S502, a test result of the eMMC is determined based on the test results of all partitions within the eMMC.
In this embodiment, in order to further verify the power-off protection performance of the eMMC whose test result is passed, it is not enough to only use one target area as the test object, and all partitions in the eMMC need to be tested as the test object, specifically, the test results corresponding to all partitions in the eMMC are determined, and the test result of the eMMC is determined based on the test results of all partitions in the eMMC.
In one possible implementation manner, before determining the test result of the eMMC based on the test results of all partitions in the eMMC, the method includes: the test results corresponding to each partition in the eMMC are respectively determined, and specific implementation may refer to S101 to S103 and S501, which are not described herein again. The determining the test result of the eMMC based on the test results of all partitions in the eMMC may specifically be: if the test results of all the partitions in the eMMC pass, the test result of the eMMC passes; if the test result of any partition in the eMMC is failed, the test result of the eMMC is failed.
In this embodiment, the power-off protection performance of the eMMC that passes the test result is further verified by determining the test result of all partitions of the eMMC and determining the test result of the eMMC according to the test result of all partitions of the eMMC.
Fig. 6 shows a flowchart of an implementation of the testing method provided in the fifth embodiment of the present application. Referring to fig. 6, in comparison with the embodiment shown in fig. 1, the test method provided in this embodiment further includes S601, which is detailed as follows:
further, before determining the test area in the target area of the eMMC based on the random algorithm, the method further includes:
in S601, the eMMC is powered on and initialized, and the operating state of the eMMC is adjusted to a transmission state.
In this embodiment, generally, for an eMMC to be tested, it is guaranteed that the operational state of the eMMC is adjusted to a transfer (transfer) state when the test is performed, so as to subsequently write data into a target area within the eMMC.
In this embodiment, the power-on initialization processing is performed on the eMMC to adjust the working state of the eMMC to a transmission state, so as to perform a subsequent test on the eMMC regarding the protection performance of the power-off data.
Fig. 7 shows a flowchart of an implementation of the testing method provided in the sixth embodiment of the present application. Referring to fig. 7, with respect to the embodiment shown in fig. 1, the test method provided in this embodiment further includes S701, and the test method S104 provided in this embodiment includes S702, which is described in detail as follows:
in S701, the number of verification cycles is acquired to generate a verification state of the test region determined per verification cycle.
In this embodiment, the verification cycle number is used to determine the cycle number of executing the random algorithm-based determination of the test region within the target region of the eMMC; the number of verification cycles may be preset.
In this embodiment, in order to ensure the test effect on the power-off data protection performance of the eMMC, a plurality of tests need to be performed, and therefore the number of verification cycles needs to be set in advance. The specific implementation of generating the verification status of the test area determined in each verification period may refer to the description of S101 to S103, which is not described herein again.
In one possible implementation manner, the test area determined in each verification period may be from a different partition within the eMMC, so as to increase the total range of the test areas of all verification periods, and improve the test effect on the eMMC.
Further, the determining a test result of the eMMC based on the verification status of the test area includes:
in S702, a test result of the eMMC is determined based on the verification status of the plurality of test areas randomly determined for each verification period.
In this embodiment, the determining the test result of the eMMC based on the verification status of the plurality of test areas randomly determined in each verification period may specifically be: if the verification state of the test area corresponding to any verification period is failed, the test result of the eMMC is failed; and if the verification states of the test areas corresponding to all the verification periods are passed, the test result of the eMMC is passed.
In this embodiment, the test result of the eMMC is determined by the verification states of the plurality of test areas randomly determined in each verification period, so that the accuracy of the test result is improved, and the test effect on the eMMC is better.
Fig. 8 shows a flowchart of an implementation of the testing method provided in the seventh embodiment of the present application. Referring to fig. 8, with respect to the embodiment shown in fig. 7, the testing method S702 provided in this embodiment includes S801 to S803, which are detailed as follows:
further, the determining the test result of the eMMC based on the randomly determined verification status of the plurality of test areas for each verification period includes:
in S801, if the verification status of the test area corresponding to any verification cycle is failed, it is determined that the test result of the eMMC is failed.
In this embodiment, in order to improve the accuracy of subsequently determining the test result of the eMMC, the test result is determined to be failed when the verification state of the test area corresponding to any verification cycle is failed.
In S802, if the verification status of the test area corresponding to all verification periods is passed, performing data verification on the target area.
In this embodiment, if the verification states of the test areas corresponding to all the verification periods are passed, it indicates that the data in the target area has no data error due to power failure; in order to further improve the accuracy of the subsequently determined test result of the eMMC, data verification is performed on the target area at this time. The above-mentioned specific implementation of data verification for the target area can refer to the above-mentioned part related to the term explanation of the present application, and is not described herein again.
In S803, a test result of the eMMC is determined based on the data verification result of the target area.
In this embodiment, the determining the test result of the eMMC based on the data verification result of the target area may specifically be: if the data verification result of the target area is passed, the test result of the eMMC is passed; if the data verification result of the target area is failed, the test result of the eMMC is failed; that is, only if the data verification result of the target area is passed, the test result of the eMMC is passed.
In this embodiment, the accuracy of the test result is further improved by adding data verification to the target area, so that the test effect on the eMMC is better, and the power-off data protection capability of the eMMC verified by the data is further verified.
Fig. 9 shows a logic flow diagram of an application scenario provided in an embodiment of the present application, referring to fig. 9, fig. 9 details specific logic steps when a testing method provided in an embodiment of the present application is executed in the application scenario, and referring to fig. 9, when the testing method provided in an embodiment of the present application starts to be executed, details are as follows:
step 1: carrying out power-on initialization processing on the eMMC so as to adjust the working state of the eMMC to a transmission state, and carrying out data transmission on the eMMC subsequently;
step 2: determining a target area of the eMMC based on a random algorithm, and determining a test area of the target area;
and step 3: writing the bottom pattern data into each sector in the target area, and writing the background pattern data into each sector in the test area;
and 4, step 4: performing power-off test on the test area, and if the current test frequency j is less than the preset verification cycle number, continuing to execute the step 5; if the current test frequency j reaches the preset verification cycle number, executing the step 12;
and 5: the initial value of i is 1; randomly generating ith test pattern data and writing the ith test pattern data in a target dynamic area, and if i is less than N, adding the value of i and repeatedly executing the step 5; if i is equal to N, executing the next step;
step 6: sending a plurality of write data commands to the eMMC so as to write the Nth test pattern data into the target dynamic area; executing the next step when the Mth write data command is sent;
and 7: after the sending time of the Mth write data command is subjected to preset delay time, the eMMC is powered off;
step 8, the following steps: after the preset time length, electrifying the eMMC again;
and step 9: performing data verification on the target dynamic area; if the data passes the verification, executing the next step; if the data verification fails, identifying that the eMMC does not pass the test;
step 10: detecting whether the target dynamic area is the last dynamic area in the test area, if not, identifying the next dynamic area of the target dynamic area as a new target dynamic area, and returning to the step 5, namely ensuring that all dynamic areas in the test area are subjected to the steps 5-9; if the target dynamic area is the last dynamic area in the test area, executing the next step;
step 11: performing data verification on all static areas in the test area; if the data passes the verification, adding one to the value of the test time j, and returning to the step 4; if the data verification fails, identifying that the eMMC fails the test;
step 12: performing data verification on the target area, and if the data verification is passed, identifying that the eMMC passes the test; and if the data verification fails, identifying that the eMMC fails the test.
The relevant description can refer to the relevant description in all the embodiments described above, and is not limited herein.
Fig. 10 shows a schematic structural diagram of a testing apparatus provided in an embodiment of the present application, corresponding to the method described in the above embodiment, and only shows portions related to the above embodiment of the present application for convenience of description.
Referring to fig. 10, the test apparatus includes: a test area determination module for determining a test area within a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC; the pattern data writing module is used for writing the bottom pattern data into each sector in the target area and then writing the background pattern data into each sector in the test area; the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area; a test result determination module to determine a test result of the eMMC based on a verification status of the test area.
Optionally, the power outage verification module includes: the data writing module is used for randomly generating N test pattern data and sequentially writing the N test pattern data into each sector in the target dynamic area; n is an integer greater than 1; the target dynamic area is any dynamic area in the test area; the power-off module is used for powering off the eMMC in the process of writing the Nth test pattern data into each sector in the target dynamic area and powering on the eMMC again after preset time length; the data verification module is used for performing data verification on the target dynamic area; if the data verification result of the target dynamic area is failed, identifying the verification state of the test area as failed; if the data verification results of all the dynamic areas in the test area are passed, performing data verification on all the static areas in the test area; and if the data in all the static areas are the background style data, identifying that the verification state of the test area is a pass.
Optionally, the data verification module includes: the reference data module is used for acquiring a theoretical writing position corresponding to the power-off time of the eMMC; the scanning data module is used for determining an actual writing position according to the data of the target dynamic area; and the data analysis module is used for identifying the data verification result of the target dynamic region as failed if the difference value between the theoretical writing position and the actual writing position is greater than a preset allowable error value.
Optionally, the test result determining module includes: the target area test result determining module is used for determining the test result of the target area based on the verification state of the test area; the module is used for determining the test result of the eMMC according to the test results of all the partitions in the eMMC. Optionally, the testing apparatus further includes: and the initialization module is used for carrying out power-on initialization processing on the eMMC and adjusting the working state of the eMMC to a transmission state.
Optionally, the testing apparatus further includes: the verification cycle number acquisition module is used for acquiring verification cycle numbers so as to generate a verification state of the test area determined by each verification cycle; the verification cycle number is used for determining the cycle number of executing a test area in a target area of the eMMC determined based on a random algorithm; the test result determination module is further configured to determine a test result of the eMMC based on the randomly determined verification states of the plurality of test areas for each verification period.
Optionally, the test result determining module is further configured to determine that the test result of the eMMC fails if the verification state of the test area corresponding to any verification period fails; if the verification states of the test areas corresponding to all the verification periods are passed, indicating the data verification module to perform data verification on the target area; determining a test result of the eMMC based on the data verification result of the target area.
It should be noted that, for the information interaction, the execution process, and other contents between the above-mentioned apparatuses, the specific functions and the technical effects of the embodiments of the method of the present application are based on the same concept, and specific reference may be made to the section of the embodiments of the method, which is not described herein again.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Fig. 11 shows a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 11, the terminal device 11 of this embodiment includes: at least one processor 110 (only one processor is shown in fig. 11), a memory 111, and a computer program 112 stored in the memory 111 and executable on the at least one processor 110, the steps of any of the various method embodiments described above being implemented when the computer program 112 is executed by the processor 110.
The terminal device 11 may be a desktop computer, a notebook, a palm computer, a cloud server, or other computing devices. The terminal device may include, but is not limited to, a processor 110, a memory 111. Those skilled in the art will appreciate that fig. 11 is only an example of the terminal device 11, and does not constitute a limitation to the terminal device 11, and may include more or less components than those shown, or combine some components, or different components, for example, and may further include an input/output device, a network access device, and the like.
The Processor 110 may be a Central Processing Unit (CPU), and the Processor 110 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The storage 111 may in some embodiments be an internal storage unit of the terminal device 11, such as a hard disk or a memory of the terminal device 11. In other embodiments, the memory 111 may also be an external storage device of the terminal device 11, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 11. Further, the memory 111 may also include both an internal storage unit and an external storage device of the terminal device 11. The memory 111 is used for storing an operating system, an application program, a BootLoader (BootLoader), data, and other programs, such as program codes of the computer programs. The memory 111 may also be used to temporarily store data that has been output or is to be output.
The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.
The embodiments of the present application provide a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the above method embodiments when executed.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing apparatus/terminal apparatus, a recording medium, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), an electrical carrier signal, a telecommunications signal, and a software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A method for testing eMMC, comprising:
determining a test area in a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC;
writing bottom pattern data into each sector in the target area, and writing background pattern data into each sector in the test area;
performing power-off verification operation on the test area to obtain a verification state of the test area;
determining a test result of the eMMC based on a verification status of the test area.
2. The test method of claim 1, wherein the test area comprises a plurality of dynamic areas and a plurality of static areas; the executing the power-off verification operation on the test area to obtain the verification state of the test area comprises:
randomly generating N test pattern data and writing the N test pattern data into each sector in a target dynamic area in sequence; n is an integer greater than 1; the target dynamic area is any dynamic area in the test area;
powering off the eMMC in the process of writing the Nth test pattern data into each sector in the target dynamic area, and powering on the eMMC again after a preset time length;
performing data verification on the target dynamic area;
if the data verification result of the target dynamic area is failed, identifying the verification state of the test area as failed;
if the data verification results of all the dynamic areas in the test area are passed, performing data verification on all the static areas in the test area;
and if the data in all the static areas are the background style data, identifying that the verification state of the test area is a pass.
3. The testing method of claim 2, wherein the performing data validation on the target dynamic region comprises:
acquiring a theoretical writing position corresponding to the power-off time of the eMMC;
determining an actual writing position according to the data of the target dynamic area;
and if the difference value between the theoretical writing position and the actual writing position is greater than a preset allowable error value, identifying the data verification result of the target dynamic region as failed.
4. The testing method of any of claims 1-3, wherein the determining a test result for the eMMC based on the validation status of the test area comprises:
determining a test result of the target area based on a verification state of the test area;
determining a test result of the eMMC based on the test results of all partitions within the eMMC.
5. The testing method of claim 1, wherein prior to determining the test area within the target area of the eMMC based on the stochastic algorithm, further comprising:
and carrying out power-on initialization processing on the eMMC and adjusting the working state of the eMMC to a transmission state.
6. The testing method of claim 1, further comprising:
acquiring verification cycle number to generate a verification state of the test area determined by each verification cycle; the verification cycle number is used for determining the cycle number of executing a test area in a target area of the eMMC determined based on a random algorithm;
the determining a test result of the eMMC based on the verification status of the test area includes:
and determining the test result of the eMMC according to the randomly determined verification states of the plurality of test areas in each verification period.
7. The test method of claim 6, wherein the determining the test result for the eMMC based on the randomly determined verification status for the plurality of test regions for each verification period comprises:
if the verification state of the test area corresponding to any verification period is failed, determining that the test result of the eMMC is failed;
if the verification states of the test areas corresponding to all the verification periods are passed, performing data verification on the target area;
determining a test result of the eMMC based on the data verification result of the target area.
8. A test apparatus, comprising:
a test area determination module for determining a test area within a target area of the eMMC based on a random algorithm; the target area is any partition of the eMMC;
the pattern data writing module is used for writing the bottom pattern data into each sector in the target area and then writing the background pattern data into each sector in the test area;
the power-off verification module is used for executing power-off verification operation on the test area to obtain a verification state of the test area;
a test result determination module to determine a test result of the eMMC based on a verification status of the test area.
9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114518981A (en) * | 2022-01-10 | 2022-05-20 | 深圳佰维存储科技股份有限公司 | eMMC test method, device, readable storage medium and electronic equipment |
| CN116383091A (en) * | 2023-05-29 | 2023-07-04 | 珠海妙存科技有限公司 | Starting method and starting device of eMMC verification platform and storage medium |
| CN116913351A (en) * | 2023-09-13 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Method, device, medium and equipment for testing data loss of storage equipment |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109815071A (en) * | 2019-01-04 | 2019-05-28 | 珠海妙存科技有限公司 | A kind of storage medium power failure test method based on linux system |
| CN110739025A (en) * | 2019-09-30 | 2020-01-31 | 广州妙存科技有限公司 | storage equipment power failure test method, device and system |
| CN111081309A (en) * | 2019-12-16 | 2020-04-28 | 湖南磐石科技有限公司 | Solid state disk test system |
| CN111105839A (en) * | 2018-10-26 | 2020-05-05 | 长鑫存储技术有限公司 | Chip testing method and device, electronic equipment and computer readable medium |
| CN111124881A (en) * | 2019-11-13 | 2020-05-08 | 深圳佰维存储科技股份有限公司 | eMMC firmware test method and device |
| WO2020164921A1 (en) * | 2019-02-14 | 2020-08-20 | Robert Bosch Gmbh | Method and apparatus for processing data stored in a storage device |
-
2020
- 2020-09-30 CN CN202011066427.3A patent/CN112133357B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111105839A (en) * | 2018-10-26 | 2020-05-05 | 长鑫存储技术有限公司 | Chip testing method and device, electronic equipment and computer readable medium |
| CN109815071A (en) * | 2019-01-04 | 2019-05-28 | 珠海妙存科技有限公司 | A kind of storage medium power failure test method based on linux system |
| WO2020164921A1 (en) * | 2019-02-14 | 2020-08-20 | Robert Bosch Gmbh | Method and apparatus for processing data stored in a storage device |
| CN110739025A (en) * | 2019-09-30 | 2020-01-31 | 广州妙存科技有限公司 | storage equipment power failure test method, device and system |
| CN111124881A (en) * | 2019-11-13 | 2020-05-08 | 深圳佰维存储科技股份有限公司 | eMMC firmware test method and device |
| CN111081309A (en) * | 2019-12-16 | 2020-04-28 | 湖南磐石科技有限公司 | Solid state disk test system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114518981A (en) * | 2022-01-10 | 2022-05-20 | 深圳佰维存储科技股份有限公司 | eMMC test method, device, readable storage medium and electronic equipment |
| CN116383091A (en) * | 2023-05-29 | 2023-07-04 | 珠海妙存科技有限公司 | Starting method and starting device of eMMC verification platform and storage medium |
| CN116383091B (en) * | 2023-05-29 | 2023-08-29 | 珠海妙存科技有限公司 | Starting method and starting device of eMMC verification platform and storage medium |
| CN116913351A (en) * | 2023-09-13 | 2023-10-20 | 合肥康芯威存储技术有限公司 | Method, device, medium and equipment for testing data loss of storage equipment |
| CN116913351B (en) * | 2023-09-13 | 2023-12-26 | 合肥康芯威存储技术有限公司 | Method, device, medium and equipment for testing data loss of storage equipment |
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| Publication number | Publication date |
|---|---|
| CN112133357B (en) | 2023-06-09 |
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