KR101365430B1 - Apparatus for state detecting of flash memory in solid state drive tester - Google Patents
Apparatus for state detecting of flash memory in solid state drive tester Download PDFInfo
- Publication number
- KR101365430B1 KR101365430B1 KR1020120088329A KR20120088329A KR101365430B1 KR 101365430 B1 KR101365430 B1 KR 101365430B1 KR 1020120088329 A KR1020120088329 A KR 1020120088329A KR 20120088329 A KR20120088329 A KR 20120088329A KR 101365430 B1 KR101365430 B1 KR 101365430B1
- Authority
- KR
- South Korea
- Prior art keywords
- test
- storage
- pattern data
- flash memory
- failure
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
Abstract
A flash memory state detection apparatus is disclosed in a solid state drive tester capable of detecting an individual flash memory malfunctioning in an SSD composed of a plurality of flash memories.
In the disclosed solid state drive tester, a flash memory state detection apparatus includes: a host terminal for receiving a test condition for testing a storage from a user; Test control means for generating a test pattern or randomly generating a test pattern according to the test condition, and testing the storage with the test pattern, wherein the test control means includes a LBA (Logical) of a host at the time of testing the storage. A test execution unit for restricting the use of an algorithm for changing a block address (PB) to a physical block address (PBA) written to a flash memory in the SSD and matching the LBA of the host and the SSD to detect a flash memory in which the error occurs in the SSD is provided. .
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory state detection device in a solid state drive (SSD) tester, and more particularly, to detect an individual flash memory malfunctioning in an SSD composed of a plurality of flash memories. A flash memory state detector in a solid state drive tester.
To date, the most commonly known and used mass storage media storage device is a hard disk (HDD). However, in recent years, as the price of NAND flash semiconductor devices that can store a large capacity among the semiconductor devices having a memory function and the data stored therein is not erased even when power is not supplied, SSDs using the semiconductor devices having a memory function have been reduced. Massive digital media storage devices such as these are emerging.
These SSDs have three to five times faster write and read speeds than conventional hard disks, and hundreds of times read / write speeds for random addresses required by database management systems. It has excellent performance. In addition, since SSD operates in a silent manner, it can solve the problem of noise, which is a disadvantage of the existing hard disk, and operates at a low power level that is incomparable with that of a hard disk. It is known to be the most suitable.
In addition, it has the advantages of being more durable than conventional hard disks against external shocks, and in terms of design for external appearance, it can be manufactured in a smaller and more diverse form compared to a hard disk of a standard shape. It is possible to make the appearance of the electronic product in which the device is used smaller, which has many advantages in terms of its application.
Due to these advantages, SSD devices are rapidly spreading not only to existing desktop computers and laptop computers, but also to storage media for search, home shopping, video service servers, storage media for various research and development, and special equipment fields. Forecasts are expected to expand.
The SSD test apparatus proposed in the related art for testing a well-known SSD is disclosed in FIG. 1.
The conventional SSD test apparatus shown in FIG. 1 includes a
The
The
The
More preferably, the
The well-known
In addition, the
The conventional solid state drive (SSD) test apparatus configured as described above has a plurality of test devices for testing storage in a single chip on a single board through an FPGA, and a user for testing an SSD wants to test a solid state drive tester. After accessing the storage, the test condition is input through the
The test condition of the user input through the
The
The
In more detail, the
The pattern data generated in this way is transferred to the
Afterwards, the command data output for the test by the embedded
Next, the result data for a test of the
The
The failure signal generated when the SSD test is determined to be failed is stored in the internal failure memory, and is later transmitted to the embedded
Therefore, the user can check the test result of the easily tested storage through the
However, the prior art as described above, even when a problem occurs only in a specific flash memory of the SSD, the storage tester determines that the failure, the entire SSD can not be used.
For example, although the SSD recovery can be performed by replacing only a specific flash memory having a problem among a plurality of flash memories constituting the SSD, it is impossible to detect the state of the flash memory individually, so that the entire SSD is determined to be a failure, The entire SSD will be unusable.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art,
SUMMARY OF THE INVENTION An object of the present invention is to provide a flash memory state detection apparatus in a solid state drive tester capable of detecting an individual flash memory malfunctioning in an SSD composed of a plurality of flash memories.
Another problem to be solved by the present invention is to analyze the LBA in which the failure occurs to record the failure information in the failed memory to detect a specific flash memory, and read it from the host terminal to replace the specific flash memory to recover the SSD To provide a flash memory state detection device in one solid state drive tester.
A first embodiment of a flash memory state detection apparatus in a solid state drive tester according to the present invention for solving the above problems,
A host terminal for receiving a test condition for testing the storage from a user;
Test control means for generating a test pattern or randomly generating a test pattern according to the test condition, and testing the storage with the test pattern,
Wherein the test control means comprises:
And a test execution unit that detects a flash memory in which an error occurs in the SSD by matching a logical block address (LBA) between the host and the SSD when the storage is tested.
The test execution unit,
A pattern data generator for generating pattern data by selecting any one of pattern data generated by the test condition or randomly generated pattern data according to a pattern data selection signal output from an embedded processor controlling the test of the storage;
A buffer memory for temporarily storing read data read from the storage;
According to a control command outputted from the embedded processor, a control command for limiting the use of an algorithm for changing a logical block address (LBA) of a host to a physical block address (PBA) written to flash memory in an SSD during storage testing is output. Command generator;
A failure processor configured to compare the pattern data generated by the pattern data generator with read data temporarily stored in the buffer memory to determine whether a failure occurs, and generate failure information upon failure;
And a failure memory for storing failure information generated by the failure processing unit.
The failure information may include an address of a flash memory in which the failure occurs.
The second embodiment of the flash memory state detection apparatus in the solid state drive tester according to the present invention for solving the above problems,
A host terminal for receiving a test condition for testing the storage from a user;
Test control means for generating a test pattern or randomly generating a test pattern according to the test condition, and testing the storage with the test pattern,
Wherein the test control means comprises:
And a test execution unit configured to detect a flash memory having an error by converting a logical block address (LBA) of a host into a physical block address (PBA) of the flash memory when an error of the flash memory in the SSD occurs during the storage test. .
The address translation algorithm is characterized by using write amplification, garbage collection, wear-leveling.
The test execution unit,
A pattern data generator for generating pattern data by selecting any one of pattern data generated by the test condition or randomly generated pattern data according to a pattern data selection signal output from an embedded processor controlling the test of the storage;
A buffer memory for temporarily storing read data read from the storage;
An LBA analyzer configured to generate the LBA of the host as the same PBA as the address of the flash memory generated by the SSD, based on an address translation algorithm used by the SSD according to a failure processing instruction generated by the embedded processor;
By comparing the pattern data generated by the pattern data generator with the read data temporarily stored in the buffer memory to determine whether the failure (fail), and in case of failure, the failure information is generated by including the PBA generated by the LBA analysis unit in the failure information A failure processing unit;
A failure memory for storing failure information generated by the failure processing unit;
And a command generator for transmitting a test command generated by the embedded processor to a storage interface unit.
The address translation algorithm is characterized by using write amplification, garbage collection, and wear-leveling.
According to the present invention, there is an advantage of detecting a malfunctioning individual flash memory in an SSD composed of a plurality of flash memories.
In addition, according to the present invention, it is possible to detect a specific flash memory that has failed by analyzing a failed LBA, so by replacing only a specific failed flash memory and recovering the SSD, the entire SSD can be used when a specific flash memory fails as before. There is an effect that can solve the problem that cannot be solved.
1 is a schematic configuration diagram of a solid state drive test apparatus to which the conventional and the present invention is applied;
2 is a configuration diagram of a first embodiment of a test execution unit in the present invention;
3 is a configuration diagram of a second embodiment of a test execution unit in the present invention;
4 is a configuration diagram of an embodiment of a multi-interfacer applied to the present invention.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
In general, in SSDs, the LBA (Logical Block Address) of the SSD processed by the host and the actual LBA written to the flash memory in the SSD are called PBAs (Physical Block Address), and algorithms such as write amplification, garbage collection, and wear-leveling are used in the SSD. Because LBA and PBA are not the same, the host does not know which address in which flash memory is actually written or read.
In order to know the PBA processed in the SSD, it is necessary to control the SATA controller of the SSD, find out the algorithm of the firmware (F / W) that converts the LBA to PBA, and generate the PBA on the host to find the failed flash memory.
The present invention proposes the following two methods to detect the flash memory in which the SSD fails in the host.
First, by creating a test mode in the SSD's firmware, the LBA of the host and the flash memory is matched by avoiding algorithms such as write amplification, garbage collection, and wear-leveling when testing the SSD. This allows the storage test to determine the pass / fail of the SSD and write its address to the failed memory to find the failed flash memory of the SSD and to recover the SSD by replacing only the flash memory.
Secondly, the storage tester emulates the write amplification, garbage collection, and wear-leveling algorithms performed by the SSD controller firmware on the storage, and knows the PBA and flashes the host's LBA when a failure occurs. The SSD can be recovered by converting to PBA in memory, storing it in the failed memory, checking the failed flash memory in the host, and replacing only the corresponding flash memory.
Hereinafter, the two methods described above will be described in detail by dividing the first and second embodiments.
≪ Embodiment 1 >
In the solid state drive tester corresponding to the first embodiment of the present invention, the flash memory state detection apparatus is identical to the conventional solid state drive test apparatus shown in FIG. Control means 130,
Here, the characteristics of the present invention is to change the control algorithm in the embedded
The
The
The
More preferably, the
The well-known
In addition, as illustrated in FIG. 2, the
In addition, the
As shown in FIG. 4, the
The first embodiment of the flash memory state detection device in the solid state drive tester according to the present invention configured as described above is a method for testing an SSD in a state in which a plurality of test devices for testing storage are chipped onto a single board through an FPGA. After the user connects to the storage to test the solid state drive tester, and inputs a test condition through the host terminal (110). The test condition may include an interface selection signal and a test pattern selection signal for interfacing with the storage to be tested. The test pattern selection signal is a selection signal for selecting preset pattern data or selecting a plurality of randomly generated random pattern data.
The test condition of the user input through the
The
The
In more detail, as illustrated in FIG. 2, the
By such a control command, the
The
For example, although not shown in the drawing, the
The pattern data generator may include a pattern data generator for generating 8-bit pattern data, a pattern data generator for generating 16-bit pattern data, a pattern data generator for generating 24-bit pattern data, and a pattern data generator for generating 32-bit pattern data. It may include.
The multiplexer selects one of the pattern data stored in the pattern data memory or the pattern data randomly generated by the plurality of pattern data generators according to the pattern data selection signal generated from the embedded
In this case, as shown in FIG. 4, the
For example, an interface selection signal is applied from the embedded
Subsequently, the command data output for the test by the embedded
In addition, the write data output from the
When the command data and the write data for the test are input to each interface unit as described above, the
Here, since the SATA interface, the SAS interface, and the PCIe interface adopt the standard interface for the interface as it is, detailed description of each interface will be omitted.
Next, after reading the result data for the test of the
When the data reading the storage test is transmitted to the embedded
The
The failure information generated in this way is stored in the
Therefore, the user can check the test result of the storage easily tested through the
As a result of this check, if a specific flash memory has failed, the SSD can be recovered by replacing only the failed specific flash memory with the SSD. Thus, when a specific flash memory has failed in the related art, the entire SSD cannot be used. The problem is solved.
≪ Embodiment 2 >
In the solid state drive tester corresponding to the second embodiment of the present invention, the flash memory state detection device is the same as the conventional solid state drive test device shown in FIG. 1, and includes a
Here, the feature of the present invention is to change the control algorithm in the embedded
The
The
The
More preferably, the
The well-known
In addition, as illustrated in FIG. 3, the
In addition, the
As shown in FIG. 4, the
The second embodiment of the flash memory state detection device in the solid state drive tester according to the present invention configured as described above is to test an SSD in a state in which a plurality of test devices for testing storage are chipped onto a single board through an FPGA. After the user connects to the storage to test the solid state drive tester, and inputs a test condition through the host terminal (110). The test condition may include an interface selection signal and a test pattern selection signal for interfacing with the storage to be tested. The test pattern selection signal is a selection signal for selecting preset pattern data or selecting a plurality of randomly generated random pattern data.
The test condition of the user input through the
The
The
In more detail, as illustrated in FIG. 3, the
In addition, the
For example, although not shown in the drawing, the
The pattern data generator may include a pattern data generator for generating 8-bit pattern data, a pattern data generator for generating 16-bit pattern data, a pattern data generator for generating 24-bit pattern data, and a pattern data generator for generating 32-bit pattern data. It may include.
The multiplexer selects one of the pattern data stored in the pattern data memory or the pattern data randomly generated by the plurality of pattern data generators according to the pattern data selection signal generated from the embedded
In this case, as shown in FIG. 4, the
For example, an interface selection signal is applied from the embedded
Subsequently, the command data output for the test from the embedded
In addition, the write data output from the
When the command data and the write data for the test are input to each interface unit as described above, the
Here, since the SATA interface, the SAS interface, and the PCIe interface adopt the standard interface for the interface as it is, detailed description of each interface will be omitted.
Next, after reading the result data for the test of the
When the data reading the storage test is transmitted to the embedded
The
If it is determined that the read data has failed, the PBA of the flash memory included in the received read data is transferred to the
The
If it is determined that the read data is a failure, the
The failure information generated in this way is stored in the
Therefore, the user can check the test result of the storage easily tested through the
As a result of this check, if a specific flash memory has failed, the SSD can be recovered by replacing only the failed specific flash memory with the SSD. Thus, when a specific flash memory has failed in the related art, the entire SSD cannot be used. The problem is solved.
It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims and their equivalents. Of course, such modifications are within the scope of the claims.
110 ... Host terminal
120 ... network
130 ... Test control means
132 ... Storage interface
133 ... Embedded processor
160 ... Test execution
161, 171... Pattern data generator
162, 172. Buffer memory
163, 173... Failure handler
164, 174... Fail memory
165, 176... Command generator
175 ... LBA Analysis Department
Claims (7)
Wherein the test control means comprises:
A test execution unit configured to detect a flash memory having an error in the SSD by matching a Logical Block Address (LBA) of a host and a solid state drive (SSD) during a test of the storage;
The test execution unit,
A pattern data generator for generating pattern data by selecting any one of pattern data generated by the test condition or randomly generated pattern data according to a pattern data selection signal output from an embedded processor controlling the test of the storage; A buffer memory for temporarily storing read data read from the storage; In response to a control command output from the embedded processor, a control command for limiting the use of an address translation algorithm that changes a logical block address (LBA) of a host to a physical block address (PBA) written to a flash memory in an SSD during storage testing. An output command generator; A failure processor configured to compare the pattern data generated by the pattern data generator with read data temporarily stored in the buffer memory to determine whether a failure occurs, and generate failure information upon failure; And a failure memory for storing failure information generated by the failure processing unit.
Wherein the test control means comprises:
When the storage of the flash memory in the SSD (Solid State Drive) when the error occurs, the test execution unit for converting the LBA (Logical Block Address) of the host to the PBA (Physical Block Address) of the flash memory to detect the failed flash memory and,
The test execution unit,
A pattern data generator for generating pattern data by selecting any one of pattern data generated by the test condition or randomly generated pattern data according to a pattern data selection signal output from an embedded processor controlling the test of the storage; A buffer memory for temporarily storing read data read from the storage; An LBA analyzer configured to generate the LBA of the host as the same PBA as the address of the flash memory generated by the SSD, based on an address translation algorithm used by the SSD according to a failure processing instruction generated by the embedded processor; By comparing the pattern data generated by the pattern data generator with the read data temporarily stored in the buffer memory to determine whether the failure (fail), and in case of failure, the failure information is generated by including the PBA generated by the LBA analysis unit in the failure information A failure processing unit; A failure memory for storing failure information generated by the failure processing unit; And a command generator for transmitting a test command generated by the embedded processor to a storage interface unit.
A flash memory state detection device in a solid state drive tester characterized by using algorithms of write amplification, garbage collection, and wear-leveling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120088329A KR101365430B1 (en) | 2012-08-13 | 2012-08-13 | Apparatus for state detecting of flash memory in solid state drive tester |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120088329A KR101365430B1 (en) | 2012-08-13 | 2012-08-13 | Apparatus for state detecting of flash memory in solid state drive tester |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR101365430B1 true KR101365430B1 (en) | 2014-02-20 |
Family
ID=50271564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020120088329A KR101365430B1 (en) | 2012-08-13 | 2012-08-13 | Apparatus for state detecting of flash memory in solid state drive tester |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101365430B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610740A (en) * | 2019-09-29 | 2019-12-24 | 深圳大普微电子科技有限公司 | Test unit, method and system, controller and storage device |
| KR20230065067A (en) * | 2021-11-04 | 2023-05-11 | 주식회사 엑시콘 | Apparatus for Testing Solid State Drive based on PCIe Interface |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060021429A (en) * | 2004-09-03 | 2006-03-08 | 주식회사 유니테스트 | Signal distribution apparatus for semiconductor device tester |
| KR20100114697A (en) * | 2009-04-16 | 2010-10-26 | (주) 제노맥스 | Storage tester and solid state drive device |
-
2012
- 2012-08-13 KR KR1020120088329A patent/KR101365430B1/en active IP Right Grant
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060021429A (en) * | 2004-09-03 | 2006-03-08 | 주식회사 유니테스트 | Signal distribution apparatus for semiconductor device tester |
| KR20100114697A (en) * | 2009-04-16 | 2010-10-26 | (주) 제노맥스 | Storage tester and solid state drive device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110610740A (en) * | 2019-09-29 | 2019-12-24 | 深圳大普微电子科技有限公司 | Test unit, method and system, controller and storage device |
| KR20230065067A (en) * | 2021-11-04 | 2023-05-11 | 주식회사 엑시콘 | Apparatus for Testing Solid State Drive based on PCIe Interface |
| KR102600569B1 (en) | 2021-11-04 | 2023-11-09 | 주식회사 엑시콘 | Apparatus for Testing Solid State Drive based on PCIe Interface |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9171643B2 (en) | Solid state drive tester | |
| KR101240634B1 (en) | Apparatus for fail detecting in solid state drive tester | |
| US9015545B2 (en) | Solid state drive tester | |
| KR101561854B1 (en) | Non-mounted storage test device based on fpga | |
| US9411700B2 (en) | Storage tester capable of individual control for a plurality of storage | |
| US7743292B2 (en) | Apparatus and method for memory card testing | |
| US9378846B2 (en) | Non-mounted storage test device based on FPGA | |
| KR101547317B1 (en) | System for detecting fail block using logic block address and data buffer address in storage test device | |
| US9448742B2 (en) | Communication between a host and a secondary storage device | |
| US9245613B2 (en) | Storage interface apparatus for solid state drive tester | |
| US9858366B2 (en) | Simulator and simulating method for flash memory background | |
| US20140164845A1 (en) | Host computer and method for testing sas expanders | |
| KR101365430B1 (en) | Apparatus for state detecting of flash memory in solid state drive tester | |
| CN112133357B (en) | eMMC test method and device | |
| US9153345B2 (en) | Error generating apparatus for solid state drive tester | |
| CN110058954A (en) | Storage system for error checking | |
| US20230141749A1 (en) | Failure prediction method and device for a storage device | |
| US11115056B2 (en) | Location selection based on erasure code techniques | |
| US20180285228A1 (en) | Memory test system and an operating method thereof | |
| KR20150070528A (en) | Data storage device and operating method thereof | |
| CN109582523B (en) | Method and system for effectively analyzing performance of NVMe (network video recorder) module at front end of SSD (solid State drive) | |
| CN117393032B (en) | Storage device and data processing method thereof | |
| JP2020113132A (en) | Control device, disk array device, and patrol diagnostic method | |
| TWI447712B (en) | System and method for testing hard disks under extensible firmware interface | |
| CN115774848A (en) | Failure prediction method and device for storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20161212 Year of fee payment: 4 |
|
| FPAY | Annual fee payment |
Payment date: 20181204 Year of fee payment: 6 |
|
| FPAY | Annual fee payment |
Payment date: 20191112 Year of fee payment: 7 |