CN113409881B - Flash memory erasure interrupt recovery test method and device, electronic equipment and storage medium - Google Patents
Flash memory erasure interrupt recovery test method and device, electronic equipment and storage medium Download PDFInfo
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- CN113409881B CN113409881B CN202110719195.5A CN202110719195A CN113409881B CN 113409881 B CN113409881 B CN 113409881B CN 202110719195 A CN202110719195 A CN 202110719195A CN 113409881 B CN113409881 B CN 113409881B
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56012—Timing aspects, clock generation, synchronisation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The invention discloses a flash memory erasure interrupt recovery test method, a device, electronic equipment and a storage medium, wherein the method comprises the following steps: writing first data information into a non-operation area in the flash memory; writing second data information into an operation area in the flash memory; sequentially and circularly executing the circular operation of erasure, empty checking, programming and verification by the sector of the selected operation area, interrupting the erasure operation and recovering the erasure operation according to the set interval time in the erasure process, and detecting and recording whether the first data information of the non-operation area is changed or not at intervals; and ending the cycle when the selected sector cycle execution operation reaches the set cycle times. The method enables the flash memory chip to circularly perform multiple tests, and the interrupt and recovery operations cover the whole erasing process, so that the test data is representative, the performance of the flash memory chip can be accurately and effectively reflected, and meanwhile, the influence of the accumulated occurrence of the erase interrupt and recovery operations on the data in the non-operation area can be effectively and clearly reflected.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method and apparatus for testing interruption and recovery of flash memory, an electronic device, and a storage medium.
Background
Nor Flash generally has two functions: program code and stored data are stored. Nor Flash mainly includes three data operations: data reading, data programming and data erasing. XIP (on-chip execution) operation of the CPU on Flash is achieved by sending a read command to Flash to read the code stored in Flash. The process of storing data to Flash by the CPU is as follows: firstly, an erasing instruction is sent to empty a certain block of Flash, then a programming instruction is sent to write user data into a certain page of the block, and finally a reading instruction is sent to read and verify the data. Typically, erase and program operations require some time during which Flash is generally unable to respond to other commands than interrupt commands and status register read commands. Nor Flash can only perform one operation at a time, i.e. when one operation is in progress, flash does not respond to other operations, such as erasing and programming, and does not respond to a read instruction.
When the CPU reads the command from the Flash, if the Flash is doing erasing or programming operation, the CPU needs to send an interrupt command to interrupt the programming or erasing operation of the Flash, and the state can be stored in the Flash; after the instruction is fetched, the CPU needs to send an erasing or programming recovery instruction to the Flash, and the Flash can recover the state and continue to complete the erasing or programming operation.
Because the erase operation is the most complex algorithm inside Flash, the inside contains a complex state machine, and also contains switching of up to plus or minus 10V voltage, the erase operation affects not only the operating area but also the non-operating area. When the chip is designed, the interruption of Flash erasure and the recovery flow are required to be tested, if the interruption of Flash erasure and the recovery flow are not processed completely, jump of data in the Flash can be caused, the data or the data in the code area can be turned over if the data is light, and the Flash device can be damaged permanently if the data is heavy. The existing Flash erase interrupt and recovery flow test method has the following defects:
1. the random interruption of the erasing operation is common, the interruption time point cannot ensure to cover all time slices of the erasing algorithm, and the incomplete risk of verification exists, namely the influence of the erasing interruption and the recovery operation on the chip cannot be comprehensively and effectively reflected;
2. the influence of erasure interruption and recovery operation on the data of the non-operation area is not detected;
3. in practice, the erase interrupt recovery operation may affect the establishment and maintenance of the internal voltage of Flash, but the lower frequency generally adopted by the conventional method is used for testing, so that the problem of the Flash memory chip is difficult to be detected at low frequency, that is, the influence of the erase interrupt and recovery operation on the chip cannot be reflected sufficiently.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, an electronic device, and a storage medium for testing interruption recovery of flash memory, so as to fully, effectively and fully reflect the influence of interruption recovery operation on a chip.
In a first aspect, an embodiment of the present application provides a method for performing an interrupt resume test on a NOR FLASH, where the method includes the following steps:
s1, writing first data information into a non-operation area in a flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;
s2, writing second data information into an operation area in the flash memory;
s3, sequentially and circularly executing the circular operation of erasure, empty checking, programming and verification by the sector of the selected operation area, interrupting the erasure operation and recovering the erasure operation according to the set interval time in the erasure process, and detecting and recording whether the first data information of the non-operation area is changed or not at intervals in the circular execution of the circular operation by the sector;
s4, when the selected sector cycle execution operation reaches the set cycle times, ending the cycle.
The method for testing interruption recovery of flash memory erasure further comprises the following steps executed before the step S1:
s0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.
The method for testing interruption recovery of flash memory erasure further comprises the following steps:
s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the chip read-write speed of the flash memory chip are normal.
The first data information comprises data 0 and data 1.
In the method for testing interruption and resumption of flash memory erase, the set interval of "interrupting the erase operation and resuming the erase operation according to the set interval time" in the step S3 includes an interruption interval time for starting the interruption erase operation and a resume interval time for starting the resume erase operation after the interruption erase operation is delayed.
In the method for testing interruption recovery of flash memory erase, in step S3, an interval threshold may be set, and when a sector performs a cyclic operation for the interval threshold number of times, whether the first data information of the non-operation area changes is detected and recorded.
The method for testing interruption recovery of flash memory erase, wherein the sectors in step S3 are one or more sectors randomly selected from the operation area.
In a second aspect, an embodiment of the present application further provides a FLASH memory erase interrupt resume test device, configured to perform an interrupt resume test on a NOR FLASH, including:
the writing module is used for writing first data information and second data information into a non-operation area and an operation area in the flash memory respectively;
the selection module is used for selecting the sector in the operation area;
the circulation operation module is used for circularly executing the erasing-blank checking-programming-checking operation on the sector selected by the selection module;
the interrupt recovery module can intermittently send out an interrupt and erase operation instruction and a recovery and erase operation instruction;
the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;
the interrupt recovery module can intermittently send out an interrupt erasure operation instruction and a recovery erasure operation instruction when the circulation module performs erasure operation; the detection module may intermittently detect and record whether the first data information of the non-operation area is changed during the cyclic operation of the selected sector by the cyclic operation module.
In a third aspect, embodiments of the present application also provide an electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method as provided in the first aspect above.
In a fourth aspect, embodiments of the present application also provide a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method as provided in the first aspect above.
As can be seen from the foregoing, according to the method, the device, the electronic device and the storage medium for testing interruption and recovery of flash memory erase provided by the embodiments of the present application, the method repeatedly performs interruption and recovery operations in an erase stage of a selected sector by performing a cyclic operation on the selected sector, so that a flash memory chip is circularly tested for multiple times, and the interruption and recovery operations cover the whole erase process, so that test data is representative, and the performance of the flash memory chip can be accurately and effectively reflected, and meanwhile, the first data information change condition of a non-operation area is detected at intervals, so that the influence of the accumulation of the interruption and recovery operations on the data of the non-operation area can be effectively and clearly reflected; in addition, the bus clock frequency is set to be the limit frequency of the flash memory, so that the flash memory is in a state in which problems are most likely to occur, and the chip performance can be more fully tested.
Drawings
Fig. 1 is a flowchart of a flash memory erase interrupt recovery test method according to an embodiment of the present application.
Fig. 2 is a logic diagram of an embodiment 1 of a flash memory erase interrupt recovery test method according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a flash memory erase interrupt recovery test device according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
1-2, FIG. 1-2 is a method for performing an interrupt recovery test on NOR FLASH according to some embodiments of the present application, the method comprising the steps of:
s1, writing first data information into a non-operation area in a flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;
the non-operation area refers to the storage unit areas where the direct erase interrupt recovery operation is not required, and the first data information is written into the storage units of these areas for the purpose of subsequently verifying the influence of the erase interrupt recovery operation on the non-operation area.
In particular, setting the limiting frequency makes it easier to detect problems exposed during the testing of flash memory chips.
S2, writing second data information into an operation area in the flash memory;
the operation area refers to a memory cell area which can be selected for performing an erase interrupt recovery operation, in order to reduce test time in actual operation, a part of the area is generally selected in the operation area for performing test operation so as to save test time and reduce the overall erase write frequency in the test process of the flash memory chip, the area selected for the test operation generally takes a block or a sector as a test unit, no matter which part of the operation area is subjected to test operation, second data information is also integrally written in the operation area, and the test unit of the operation area is subjected to the next step from the erase step after the second data information is written;
s3, sequentially and circularly executing the circular operation of erasure, empty checking, programming and verification by the sector of the selected operation area, interrupting the erasure operation and recovering the erasure operation according to the set interval time in the erasure process, and detecting and recording whether the first data information of the non-operation area is changed or not at intervals in the circular execution of the circular operation by the sector;
specifically, in the embodiment of the present application, a sector (sector) is used as a test unit of an operation area, and after the sector is selected, in each cycle operation, the following operations are sequentially performed on the sector: and erasing the data of all the storage units in the sector to enable the data of all the storage units to be 1, performing empty checking processing on the data of the storage units, detecting the erasing condition of the storage units, performing data programming on the storage units in the sector, and finally reading and checking the data of the storage units.
Specifically, the programming data of the storage units in the selected sector are the second data information, so that the data information of the storage units in the sector at the beginning and the end of each cycle operation is ensured to be the same, and the stability of the data of the flash memory chip after the flash memory chip is subjected to the erase interrupt recovery operation can be better reflected as the data reference.
Specifically, over-erase detection and repair are required when the erase operation is finished, so that the over-erase condition of the memory cells after the memory cells are erased is ensured not to exist.
More specifically, in each erase operation in the loop operation, the erase operation is interrupted and resumed according to the interval time, so that the whole erase operation process can be covered, that is, it is ensured that the erase interruption can cover all time slices of the erase algorithm, so that the erase interruption and resumption mode can effectively reflect the chip performance.
More specifically, after a certain number of cyclic operations are executed, whether the first data information of the non-operation area changes is detected and recorded, so that the influence of the cumulative occurrence number of the erase interrupt and the recovery operation on the data of the non-operation area can be effectively and clearly reflected.
More specifically, it is possible to record the change condition of the first data information while detecting and recording whether the change is generated in the first data information of the non-operation area, so as to more clearly reflect the influence of the cumulative occurrence times of the erase interrupt and the resume operation on the data of the non-operation area.
S4, when the selected sector cycle execution operation reaches the set cycle times, ending the cycle.
Specifically, the test method of the embodiment of the application is more representative by setting a sufficient cycle number for the cycle operation, and the performance of the flash memory chip can be tested more accurately.
In some preferred embodiments, the number of cycles of the cycling operation is 50-150K, in this example, preferably 100K.
According to the flash memory erasure interruption recovery test method, the selected sector of the operation area is repeatedly subjected to erasure, empty checking, programming and verification in a cyclic operation mode, and interruption and recovery operations are carried out for a plurality of times in the erasure process, so that the flash memory chip is circularly subjected to a plurality of tests, the interruption and recovery operations cover the whole erasure process, test data are representative, the performance of the flash memory chip can be accurately and effectively reflected, meanwhile, the first data information change condition of the non-operation area is detected at intervals, and the influence of the accumulation occurrence of the erasure interruption and the recovery operations on the data of the non-operation area can be effectively and clearly reflected; in addition, the bus clock frequency is set to be the limit frequency of the flash memory, so that the flash memory is in a state in which problems are most likely to occur, and the chip performance can be more fully tested.
In some preferred embodiments, the method further comprises the step of performing before step S1:
s0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.
Specifically, the step S0 ensures that the basic functions of the chip before the chip test are normal, namely the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal, and prepares for the influence on the device by checking the recovery of frequent erasure interruption after the test.
In the existing test method, the erase interrupt and recovery functions are generally only verified, the influence of frequent erase interrupt recovery on the Flash device is not tested after the test, and the circuit structure of Flash determines that any operation related to high-voltage switching can possibly influence the reliability of the device, so that the Flash memory chip can be damaged or damaged after the test operation.
Thus, in some preferred embodiments, the method further comprises the step of performing after step S4:
s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the chip read-write speed of the flash memory chip are normal.
Specifically, since step S0 is executed, it is known that the basic function of the flash memory chip under test is in a normal state before the test, and the change condition of the performance of the flash memory chip after the test, that is, whether the corresponding basic function is changed and the change amplitude can be known through step S5.
More specifically, whether the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal or not is analyzed, so that the problems of whether the flash memory chip has electric leakage or not and whether the read-write speed is attenuated or not can be known.
In some preferred embodiments, the first data information includes data 0 and data 1.
Specifically, since the first data information includes data 0 and data 1, when step S3 detects whether the first data information changes, it can test both erase disturbance and over-erase (affected area data 0 becomes 1) and program disturbance (affected area data 1 becomes 0), so that the influence of the erase interrupt recovery operation on the non-operation area by the operation area of the flash memory chip can be more clearly tested.
More specifically, in the embodiment of the present application, the first data information is 5A data, checkerboard data, or the like, and these data include data 0 and data 1.
More specifically, the second data information is A5 data, which is distinguishable from the first data information.
In some preferred embodiments, the set interval of "interrupting the erase operation, resuming the erase operation at set interval time" in step S3 includes an interruption interval time for starting the interruption erase operation and a resume interval time for starting the resume erase operation with a delay after the interruption erase operation.
Specifically, after starting to erase the memory cell, after an interrupt interval time, an erase interrupt instruction is sent to the flash memory chip to interrupt the erase operation, then after an erase interrupt instruction is sent to delay a recovery interval time, an erase recovery instruction is sent to the flash memory chip to enable the erase operation to continue, then after the interrupt interval time, an erase interrupt instruction is sent to the flash memory chip to interrupt the erase operation, and so on, the erase interrupt and recovery operations are continuously carried out until the erase operation in the round of circulation operation is completed; the interruption interval time and the recovery interval time are set to continuously carry out the erasing interruption and recovery operation, so that the whole erasing process is covered by the erasing interruption and recovery operation, thereby more effectively and comprehensively reflecting the influence of the interruption and recovery operation on the data of the flash memory chip in different stages of the erasing operation and reflecting the data holding capacity of the flash memory chip.
In some preferred embodiments, an interval threshold may be set in step S3, and it is detected and recorded whether the first data information of the non-operation area is changed every time the sector performs the cyclic operation for the interval threshold number of times.
Specifically, by setting the interval threshold to detect the change of the first data information, the influence of different stages in the cyclic operation and cyclic process on the non-operation area can be orderly and clearly reflected.
In some preferred embodiments, the interval threshold is typically 1/500-1/50 of the number of cyclic operations, in this example 1/100, and if the number of cyclic operations is 100K, the interval threshold is 1000.
In some preferred embodiments, the sectors in step S3 are one or more sectors randomly selected from the operating region.
Specifically, the sector selection adopts a random selection mode to ensure that the test unit has randomness, and the randomly selected sector can more effectively reflect the performance of the flash memory chip.
According to the flash memory erasure interruption recovery test method, the selected sector is subjected to circulation operation, interruption and recovery operation are repeatedly carried out in an erasure stage in the circulation operation, so that the flash memory chip is subjected to repeated tests, the interruption and recovery operation covers the whole erasure process, test data are representative, the performance of the flash memory chip can be accurately and effectively reflected, meanwhile, the change condition of first data information of a non-operation area is intermittently detected, and the influence of the accumulation occurrence of the erasure interruption and the recovery operation on the data of the non-operation area can be effectively and clearly reflected.
Example 1
Referring to fig. 2, before testing, an Automatic Test Equipment (ATE) is used to test the standby current, the deep sleep current and the read-write speed of the chip, so as to ensure the normal basic function of the chip before testing, and prepare for checking the influence of frequent erasure interrupt recovery on the device after testing.
Writing 5A data into a non-operation area in the whole flash memory chip; the bus clock frequency is set to be the limit frequency of Flash (the test board card adopts equal-length wires to ensure the maximum frequency of frequency runaway).
Writing A5 data into an operation area of the flash memory chip, randomly selecting a sector (sector) in the operation area, and performing 'erase-empty-program-check' cyclic operation on the sector for 100K times; in the erasing process, an erasing interrupt command is sent every tSUS (e.g. 40 us) to interrupt the erasing operation, and then the erasing operation is recovered by delaying tRS (e.g. 30 us), so that the process is repeated until the inquiry state register checks that the erasing operation of the current round is completed, and the process can ensure that the erasing interrupt can cover all time slices of the erasing algorithm.
In the test process, checking the data of the non-operation area every 1000 times of cyclic operations, and checking whether the non-operation area is influenced by over-erasure or erasure disturbance of the operation area; since the non-operational area of the present test procedure is written with 5A data, including data 0 and data 1, the inspection process can test for both erase disturbances and over-erase (affected area data 0 to 1) and program disturbances (affected area data 1 to 0).
After the test is finished, an Automatic Test Equipment (ATE) is used again to check the standby current, the deep sleep current and the reading and writing speed of the chip, and whether the chip has electric leakage and the reading and writing speed is attenuated.
In a second aspect, referring to fig. 3, fig. 3 is a schematic diagram of a FLASH memory erase interrupt resume test apparatus according to some embodiments of the present application, for performing interrupt resume test on a NOR FLASH, including:
the writing module is used for writing first data information and second data information into a non-operation area and an operation area in the flash memory respectively;
the selection module is used for selecting the sector in the operation area;
the circulation operation module is used for circularly executing the erasing-blank checking-programming-checking operation on the sector selected by the selection module;
the interrupt recovery module can intermittently send out an interrupt and erase operation instruction and a recovery and erase operation instruction;
the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;
the interrupt recovery module can intermittently send out an interrupt and erase operation instruction and a recovery and erase operation instruction when the circulation module performs erase operation; the detection module may intermittently detect and record whether the first data information of the non-operation area is changed during the cyclic operation of the selected sector by the cyclic operation module.
According to the flash memory erasure interrupt recovery test device, the first data information and the second data information are respectively written into the non-operation area and the operation area of the flash memory chip to be tested through the writing module, then the sector in the operation area is selected through the selection module, and the sector is used for circularly executing erasure-empty checking-programming-checking operation through the circulation operation module, wherein in the erasure process, the interrupt recovery module intermittently sends an interrupt erasure operation instruction and a recovery erasure operation instruction to the circulation module, so that the whole erasure operation process is intermittently interrupted and recovered, the selected area of the flash memory chip is circularly tested for a plurality of times, the interrupt operation and the recovery operation cover the whole erasure process, the test data are representative, the performance of the flash memory chip can be accurately and effectively reflected, meanwhile, the influence of erasure interrupt and recovery operation accumulation on the data of the non-operation area can be effectively and clearly reflected through the fact that the detection module intermittently detects the change condition of the first data information of the non-operation area in the circulation operation process.
In some preferred embodiments, the flash memory device further comprises a performance test module, wherein the performance test module is used for detecting performance of the flash memory chip before and after testing.
Specifically, the performance test module may detect standby current, deep sleep current, and read/write speed of the flash memory chip.
More specifically, the performance test module detects the performance of the chip before starting the test, ensures that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal, and prepares for checking the influence of frequent erasure interrupt recovery on the device after the test.
More specifically, the performance test module detects the performance of the chip after the test is finished, and can learn the change condition of the performance of the flash memory chip after the test, namely whether the corresponding basic function is changed and the change amplitude is changed, so as to learn whether the flash memory chip has electric leakage in the test and whether the read-write speed is attenuated.
In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: processor 301 and memory 302, the processor 301 and memory 302 being interconnected and in communication with each other by a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, which when run by a computing device, the processor 301 executes to perform the method in any of the alternative implementations of the embodiments described above.
In a fourth aspect, embodiments of the present application provide a storage medium, which when executed by a processor, performs a method in any of the alternative implementations of the above embodiments. The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (10)
1. A FLASH erase interrupt resume test method for performing an interrupt resume test on a NOR FLASH, the method comprising the steps of:
s1, writing first data information into a non-operation area in a flash memory, and setting the bus clock frequency as the limit frequency of the flash memory;
s2, writing second data information into an operation area in the flash memory;
s3, sequentially and circularly executing the circular operation of erasure, empty checking, programming and verification by the sector of the selected operation area, interrupting the erasure operation and recovering the erasure operation according to the set interval time in the erasure process, and detecting and recording whether the first data information of the non-operation area is changed or not at intervals in the circular execution of the circular operation by the sector;
s4, when the cycle execution operation of the selected sector reaches the set cycle times, ending the cycle;
the steps of interrupting the erasing operation and recovering the erasing operation according to the set interval time in the erasing process comprise the following steps:
after the erasing operation is started to the memory unit, an erasing interrupt instruction is sent to the flash memory chip to interrupt the erasing operation after the interrupt interval time, and then after the erasing interrupt instruction is sent to delay the recovery interval time, an erasing recovery instruction is sent to the flash memory chip to enable the erasing operation to continue, so that the erasing operation is continuously carried out, and the erasing operation is recovered until the erasing operation in the circulation operation of the round is completed.
2. The method for testing interruption of flash memory erase according to claim 1, further comprising the step of, before step S1:
s0, testing the performance of the flash memory chip, and ensuring that the standby current, the deep sleep current and the read-write speed of the flash memory chip are normal.
3. The method for resuming the flash erase interrupt according to claim 2, further comprising the step of, after step S4:
s5, checking the performance of the flash memory chip, and analyzing whether the standby current, the deep sleep current and the chip read-write speed of the flash memory chip are normal.
4. The method of claim 1, wherein the first data information includes data 0 and data 1.
5. The method according to claim 1, wherein the set interval of "interrupt erase operation and resume erase operation according to set interval time" in the step S3 includes an interrupt interval time for starting the interrupt erase operation and a resume interval time for starting the resume erase operation after the interrupt erase operation is delayed.
6. The method according to claim 1, wherein in step S3, an interval threshold is set, and when the sector performs a cyclic operation for the interval threshold number of times, it is detected and recorded whether the first data information of the non-operation area is changed.
7. The method of claim 1, wherein the sectors in step S3 are one or more sectors randomly selected from the operating area.
8. A FLASH erase interrupt resume test device for performing an interrupt resume test on a NOR FLASH, comprising:
the writing module is used for writing first data information and second data information into a non-operation area and an operation area in the flash memory respectively and setting the bus clock frequency as the limit frequency of the flash memory;
the selection module is used for selecting the sector in the operation area;
the circulation operation module is used for circularly executing the erasing-blank checking-programming-checking operation on the sector selected by the selection module and ending the circulation when the circulation execution operation of the selected sector reaches the set circulation times;
the interrupt recovery module can intermittently send out an interrupt and erase operation instruction and a recovery and erase operation instruction;
the detection module is used for detecting and recording whether the first data information of the non-operation area changes or not;
the interrupt recovery module can intermittently send out an interrupt erasure operation instruction and a recovery erasure operation instruction when the circulation module performs erasure operation; the detection module can intermittently detect and record whether the first data information of the non-operation area changes or not in the process of performing the cyclic operation on the selected sector by the cyclic operation module;
the process of intermittently sending out an interrupt erase operation instruction and a resume erase operation instruction when the loop module performs erase operation comprises the following steps:
after the erasing operation is started to the memory unit, an erasing interrupt instruction is sent to the flash memory chip to interrupt the erasing operation after the interrupt interval time, and then after the erasing interrupt instruction is sent to delay the recovery interval time, an erasing recovery instruction is sent to the flash memory chip to enable the erasing operation to continue, so that the erasing operation is continuously carried out, and the erasing operation is recovered until the erasing operation in the circulation operation of the round is completed.
9. An electronic device comprising a processor and a memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of any of claims 1-7.
10. A storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method according to any of claims 1-7.
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| CN115309464B (en) * | 2022-09-30 | 2022-12-16 | 芯天下技术股份有限公司 | Method, device, equipment and medium for verifying suspend function of flash memory chip |
| CN115312107B (en) * | 2022-09-30 | 2022-12-13 | 芯天下技术股份有限公司 | Method, device, equipment and medium for updating erasing operation voltage of flash memory chip |
| CN117331421B (en) * | 2023-12-01 | 2024-03-19 | 深圳市航顺芯片技术研发有限公司 | Micro control chip, resetting method thereof and storage medium |
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