CN115309464B - Method, device, equipment and medium for verifying suspend function of flash memory chip - Google Patents
Method, device, equipment and medium for verifying suspend function of flash memory chip Download PDFInfo
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- CN115309464B CN115309464B CN202211229131.8A CN202211229131A CN115309464B CN 115309464 B CN115309464 B CN 115309464B CN 202211229131 A CN202211229131 A CN 202211229131A CN 115309464 B CN115309464 B CN 115309464B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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Abstract
The application relates to the technical field of nonvolatile memories, and particularly discloses a method, a device, equipment and a medium for verifying a suspend function of a flash memory chip; the verification method comprises the following steps: when a flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command based on clock change and according to a preset time interval until the target state machine runs, wherein the target state machine is a state machine with a suspension function to be verified; the verification method realizes complete verification of the running process of the whole target state machine by executing the suspension and recovery instructions for multiple times in the running process of the target state machine based on clock change and according to the preset time interval, namely uniformly covering the suspension and recovery instructions in the whole running process of the target state machine.
Description
Technical Field
The present application relates to the field of non-volatile memory technologies, and in particular, to a method, an apparatus, a device, and a medium for verifying a suspend function of a flash memory chip.
Background
Suspend instructions are a common instruction for non-volatile memory, but to ensure that the function is normal, a large number of special verifications are required.
The existing verification method of the hang-up function generally sends a hang-up instruction in each flow state of an algorithm which can be inserted and run by the corresponding hang-up function, and then verifies whether the chip hang-up function is normal or not according to a simulation result obtained by corresponding state skip and algorithm operation.
In the algorithm process, a suspend (suspend) is sent to each flow state, a flash memory chip can carry out different state jumps and algorithm operations, and the suspend instruction is sent at different times in the same algorithm to possibly generate different state jumps and algorithm operations.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide a method, a device, equipment and a medium for verifying the suspend function of a flash memory chip, and the completeness of the verification of the suspend function of the flash memory chip is improved.
In a first aspect, the present application provides a method for verifying a suspend function of a flash memory chip, including the following steps:
when the flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command based on clock change and according to a preset time interval until the target state machine finishes running, wherein the target state machine is a state machine with a suspension function to be verified;
the operation result of the flash memory chip is checked.
According to the method and the device, the suspend and recovery instructions are sent according to the preset time interval, the whole running process of the target state machine is uniformly covered with the execution suspend function, the suspend and recovery instructions are sent based on the clock change based on the operation instructions which are easy to cause problems under the clock change, the suspend function of the operation instructions under the target state machine is verified, and the completeness of verification of the suspend function of the flash memory chip is improved.
Optionally, the method for verifying the suspend function of the flash memory chip according to the present application, wherein the step of sending the suspend and resume instruction according to the preset time interval based on the clock change comprises:
and sending the suspend and resume instructions according to a preset time interval during the running of the target state machine based on the rising edge and/or the falling edge of the clock.
According to the method and the device, the suspend and recovery instruction is sent at the rising edge and/or the falling edge of the clock, so that the suspend function can be verified more accurately, and errors are easy to occur at the rising edge and the falling edge of the clock when the flash memory chip executes the suspend operation.
Optionally, in the verification method for a suspend function of a flash memory chip of the present application, the operation command includes a plurality of target state machines.
By verifying the suspension function of the operation command in multiple target state machine stages, the time can be saved and the verification efficiency can be improved.
Optionally, in the verification method for the suspend function of the flash memory chip of the present application, the target state machine is an algorithm state machine of a bottommost command in the flash memory chip.
Optionally, in the verification method for the suspend function of the flash memory chip of the present application, the preset time interval is more than half of a clock cycle.
Optionally, the step of sending suspend and resume instructions comprises:
and sending a suspension instruction, and sending a recovery instruction after a preset recovery interval.
Optionally, in the verification method for the suspend function of the flash memory chip of the present application, during the operation of the target state machine, the suspend and resume instruction is sent when a rising edge occurs in a clock.
In a second aspect, the present application further provides a verification apparatus for a suspend function of a flash memory chip, the apparatus comprising:
the transmitting module is used for transmitting a suspension and recovery instruction based on clock change and according to a preset time interval when the flash memory chip executes an operation command to a target state machine to run until the target state machine runs, wherein the target state machine is a state machine with a suspension function to be verified;
and the checking module is used for checking the operation result of the flash memory chip.
According to the verification device for the hanging-up function of the flash memory chip, the hanging-up and recovery instructions are executed for multiple times during the running period of the target state machine based on the clock change and according to the preset time interval, namely, the hanging-up and recovery instructions averagely cover the running process of the whole target state machine, and complete verification of the running process of the whole target state machine is achieved.
In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer-readable instructions, and the computer-readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a fourth aspect, the present application provides a storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method as provided in the first aspect above.
From the above, the present application provides a method, an apparatus, a device, and a medium for verifying a suspend function of a flash memory chip, wherein the method uniformly covers an execution suspend function in the whole operation process of a target state machine by sending suspend and resume instructions according to a preset time interval, and verifies the suspend function of an operation command in the target state machine by sending the suspend and resume instructions based on a clock change based on that the operation command is easy to cause a problem in the clock change, thereby improving completeness of verification of the suspend function of the flash memory chip.
Drawings
Fig. 1 is a flowchart of a method for suspending a flash memory chip according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a device with a suspend function for a flash memory chip according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 201. a sending module; 202. an inspection module; 31. A processor; 32. a memory; 33. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, as shown in fig. 1, the present application provides a method for verifying a suspend function of a flash memory chip according to some embodiments, the method including the following steps:
s1, when a flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command according to a preset time interval based on clock change until the target state machine runs, wherein the target state machine is a state machine with a suspension function to be verified;
s2, checking the operation result of the flash memory chip.
Specifically, the operation command may be erase, program, or read, etc.; the operation command is executed according to a state machine switched according to the time sequence.
Specifically, the target state machine is a state machine which needs to be verified, and generally, the situation that an operation command goes wrong after a suspend and resume instruction is executed is mainly concentrated on some state machines; the target state machine is generally selected based on the state machine that has more errors in performing the suspend function, the state machine that has a higher requirement for completeness of the suspend function verification, the state machine that involves multiple state jumps, and so on.
Specifically, the suspend and resume instructions include a suspend instruction and a resume instruction, which are used in cooperation, and suspend the current operation command when the suspend function is executed, and continue to execute the operation command after the resume instruction is executed.
Specifically, the verification of the suspend function is actually to verify whether an abnormal jump or a stuck condition occurs in the operation of the flash memory chip after the suspend and resume instruction processing is performed by the target state machine, so as to ensure that the suspend function can operate normally.
Specifically, the operation command executed by the chip is executed depending on the clock change, generally, the suspend function executed by the operation command at the time of the clock change is more prone to error, when the operation command runs to the target state machine, the suspend and resume commands are sent based on the clock change and according to the preset time interval, the suspend and resume commands are sent according to the preset time interval, a plurality of suspend and resume commands are evenly sent according to the preset time interval in the whole running process of the target state machine, the sending time of the suspend and resume commands evenly covers the whole running process of the target state machine, the suspend and resume commands are sent based on the clock change, the sending time of the suspend and resume commands is overlapped with the time of the clock change, namely, the suspend function is executed under the condition of being prone to error, and complete verification of the running process of the whole target state machine is achieved.
Specifically, it should be understood that, in the method of the embodiment of the present application, the operation result of the flash memory chip is checked by monitoring the jump condition of the algorithm before and after the suspend and resume instruction is executed by the flash memory chip, or based on log data generated by the operation of the flash memory chip, or based on the voltage change condition before and after the suspend and resume instruction is executed by the flash memory chip, or by performing logic analysis through an externally connected logic analyzer, so as to determine whether the suspend and resume instruction is normally executed, that is, to verify whether the suspend function is normal.
More specifically, the suspending and resuming instructions are preferably sent based on the clock change and according to the preset time interval during the running process of the target state machine, that is, the time interval is calculated only according to the actual running time of the target state machine, so as to ensure that the sending time of the suspending and resuming instructions is uniformly covered in each time period of the running of the target state machine.
According to the method and the device, the suspend and recovery instructions are sent according to the preset time interval, the whole running process of the target state machine is uniformly covered with the execution suspend function, the suspend and recovery instructions are sent based on the clock change based on the operation instructions which are easy to cause problems under the clock change, the suspend function of the operation instructions under the target state machine is verified, and the completeness of verification of the suspend function of the flash memory chip is improved.
In some preferred embodiments, the step of sending suspend and resume instructions based on the clock change and according to the preset time interval comprises:
and sending the suspend and resume instructions according to a preset time interval during the running of the target state machine based on the rising edge and/or the falling edge of the clock.
Specifically, from practical experience, when the flash memory chip executes the suspend operation, it is generally easier to make an error at the rising edge and the falling edge of the clock, so that the suspend and resume instructions are triggered at preset time intervals, and the triggering time is just the rising edge and/or the falling edge of the clock, so that the suspend function can be verified more accurately.
In some preferred embodiments, the operation command includes several target state machines.
Specifically, the target state machines need to be set according to the verification, and when one operation command includes multiple target state machines, the operation command can be executed once to complete verification of corresponding suspend functions performed on the multiple target state machines; or the suspension function corresponding to different target state machines can be verified by separately executing multiple operation commands; preferably, the former is adopted, and the verification of a plurality of target state machines is performed by executing one operation command, so that the time can be saved and the verification efficiency can be improved.
In particular, the plurality of target state machines may be continuous or discontinuous.
In some preferred embodiments, the target state machine is an algorithmic state machine of the lowest level commands in the flash chip.
Specifically, the bottommost command algorithm state mainly includes five states of idle (idle), send instruction (cmd), send address (addr), send dummy, send data (data) and receive data (rdata); the operation commands can consist of the bottommost command algorithm state machine described above.
Specifically, according to the distribution of the state machines, the more the types of the state machines on the lower layer are, one operation command comprises a plurality of layers of state machines, and the upper layer of state machines is triggered by the lower layer of state machines, that is, whether the lower layer of state machines normally operates determines whether the upper layer of state machines can normally operate or not, so that the algorithm state machines of the lower layer of command are used as target state machines to verify the target object of the suspend function, and the suspend function can be verified more accurately.
In some preferred embodiments, the predetermined time interval is more than half a clock cycle.
Specifically, the half clock cycle is a minimum clock interval including a rising edge and a falling edge, when the preset time interval is the half clock cycle, the operation command triggers the suspend and resume instruction when running to the target state machine, and is the rising edge of the first clock, the suspend and resume instruction is executed after the half clock cycle, that is, the suspend and resume instruction is executed again on the falling edge of the clock, and then the suspend and resume instruction is executed again after the half clock cycle, that is, the suspend and resume instruction is executed on the rising edge of the clock, and the time of all clock changes can be verified by setting the preset time interval to the half clock cycle, so that the verification completeness is improved.
Specifically, the preset time interval is preferably one clock cycle, and when the operation command is executed to the target state machine, if the suspend and resume instruction is triggered on the rising edge or the falling edge of the first clock, after the one clock cycle, the suspend and resume instruction is sent on the rising edge or the falling edge of the second clock.
In some preferred embodiments, the step of sending suspend and resume instructions comprises:
and sending a suspension instruction, and sending a recovery instruction after a preset recovery interval.
Specifically, the preset recovery interval is the time required by the flash memory chip to execute the suspend instruction, and the recovery instruction is sent after the suspend instruction is completed; in actual operation, the preset recovery interval may be a long period of time, and the preset recovery interval is set to improve verification efficiency and verify the suspend function with the minimum recovery time.
In some preferred embodiments, the suspend and resume instructions are sent on a rising edge of the clock during the running of the target state machine.
Specifically, as can be seen from practical experience, the chip operation is based on the rising edge sending instruction or triggering state machine switching, so that problems are most likely to occur in the two cases, and therefore, when the rising edge occurs in the target state machine, the suspend and resume instructions are sent, so that the suspend function can be verified more accurately.
Specifically, the preset time interval is more preferably one clock cycle, and during the running of the target state machine, the suspend and resume instruction is triggered from the first rising edge that appears, and the suspend and resume instruction is triggered again through one clock cycle, that is, the suspend and resume instruction is sent to verify the suspend function at each rising edge in the running of the target state machine, because the state jump is generally triggered based on the rising edge, and the problem is more likely to occur at the rising edge, the suspend function when the rising edge appears is verified; according to the method and the device, the suspending and recovering instruction is sent when the clock rises during the running of the target state machine, so that the effect of saving resources while ensuring the completeness of verification is achieved.
In some preferred embodiments, the method further comprises the step performed after step S1 of:
and S3, when the operation of the target state machine is finished, terminating the operation of the operation command.
Specifically, after the flash memory chip executes an operation command to the target state machine to run, the operation command is directly terminated after the suspend and resume instructions are sent according to the preset time interval based on the clock change; it is also possible to terminate the execution of the operation command before checking the operation result of the flash memory chip.
Specifically, the verification suspend function is completed during the running of the target state machine, and at the end of the running of the target state machine, the running of the current operation command is terminated to reduce the operation amount.
Hereinafter, the present application will provide specific examples to illustrate the technical solutions of the present application:
the operation command runs based on the clock instruction change, the preset time interval delta t is one clock period, and the suspend and resume instructions are triggered by the rising edge to verify the suspend function of all rising edges.
The method comprises the following specific steps:
the method comprises the steps that a flash memory chip executes an operation command to a target state machine to run, the operation command enters the target state machine based on rising edge switching, a suspension command is sent at the first rising edge, a recovery command is sent after a preset recovery interval, the operation command continues to run, the suspension and recovery commands are sent when the next clock rising edge is waited (namely the target state machine runs by a delta t), and the like until the target state machine runs to the end, the suspension and recovery commands are stopped being sent, and the running result of the flash memory chip is checked.
In a second aspect, as shown in fig. 2, which is a schematic structural diagram of a verification apparatus for a suspend function of a flash memory chip according to an embodiment of the present application, the apparatus includes:
a sending module 201, configured to send a suspend and resume instruction based on a clock change and according to a preset time interval when the flash memory chip executes an operation command to the target state machine to run, until the target state machine runs to an end, where the target state machine is a state machine with a suspend function to be verified;
the checking module 202 is used for checking the operation result of the flash memory chip.
According to the verification device for the hanging function of the flash memory chip, the hanging and recovering instruction is sent according to the preset time interval, the execution hanging function is uniformly covered in the whole running process of the target state machine, the hanging and recovering instruction is sent based on the clock change on the basis that the operation instruction is easy to cause problems under the clock change, the hanging function of the operation instruction under the target state machine is verified, and the completeness of verification of the hanging function of the flash memory chip is improved.
Specifically, when the flash memory chip executes an operation command to the target state machine, the sending module 201 sends suspend and resume instructions based on the clock change and according to the preset time interval until the target state machine finishes running, and then the checking module 202 checks the running result of the flash memory chip.
In some preferred embodiments, the verification apparatus for a suspend function of a flash memory chip proposed in the embodiments of the present application further includes:
and the termination module is used for terminating the running of the operation command when the running of the target state machine is finished.
In some preferred embodiments, the method for verifying the suspend-to-flash-memory-chip function provided in the first aspect is preferably performed by using the verifying apparatus for the suspend-to-flash-memory-chip function provided in the second aspect.
In a third aspect, referring to fig. 3, fig. 3 shows an electronic device provided in the present application, including: the processor 31 and the memory 32, the processor 31 and the memory 32 being interconnected and communicating with each other via a communication bus 33 and/or other form of connection mechanism (not shown), the memory 32 storing a computer program executable by the processor 31, the processor 31 executing the computer program when the electronic device is running to perform any of the alternative implementations of the above embodiments to implement the following functions: when the flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command based on clock change and according to a preset time interval until the target state machine finishes running, wherein the target state machine is a state machine with a suspension function to be verified; the operation result of the flash memory chip is checked.
In a fourth aspect, the present application provides a storage medium having a computer program stored thereon, where the computer program, when executed by a processor 31, performs the method in any one of the alternative implementations of the above embodiments to implement the following functions: when the flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command based on clock change and according to a preset time interval until the target state machine runs, wherein the target state machine is a state machine with a suspension function to be verified; the operation result of the flash memory chip is checked.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some communication interfaces, indirect coupling or communication connection between devices or units, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A verification method for a suspend function of a flash memory chip is characterized by comprising the following steps:
when a flash memory chip executes an operation command to a target state machine to run, sending a suspension and recovery command based on clock change and according to a preset time interval until the target state machine finishes running, wherein the target state machine is a state machine with a suspension function to be verified;
checking the operation result of the flash memory chip;
the preset time interval is a half clock cycle or a clock cycle.
2. The method of claim 1, wherein the step of sending suspend and resume commands based on clock changes and according to a predetermined time interval comprises:
based on the rising edge and/or the falling edge of the clock, a suspend and resume instruction is sent according to a preset time interval during the running of the target state machine.
3. The method of claim 1, wherein the operation command comprises a number of the target state machines.
4. The method of claim 1, wherein the target state machine is an algorithm state machine of a lowest level command in the flash memory chip.
5. The method of claim 1, wherein the step of sending suspend and resume commands comprises:
and sending a suspension instruction, and sending a recovery instruction after a preset recovery interval.
6. The method of claim 1, wherein a suspend and resume command is issued on a rising edge of the clock during operation of the target state machine.
7. An apparatus for verifying suspend functionality of a flash memory chip, the apparatus comprising:
the transmitting module is used for transmitting a suspension and recovery instruction based on clock change and according to a preset time interval when the flash memory chip executes an operation command to a target state machine to run until the target state machine runs, wherein the target state machine is a state machine with a suspension function to be verified;
the checking module is used for checking the operation result of the flash memory chip;
the preset time interval is a half clock cycle or a clock cycle.
8. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-6.
9. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any of claims 1-6.
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