CN103149529B - Polycaryon processor and method of testing thereof and device - Google Patents
Polycaryon processor and method of testing thereof and device Download PDFInfo
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Abstract
The invention discloses a kind of polycaryon processor and method of testing thereof and device.Wherein, the proving installation of polycaryon processor comprises: main control module and multiple from control module, multiplely to connect successively from control module, one is provided with from control module in each processor core, eachly all be connected with main control module from control module, wherein, main control module is for generating enable signal and main test signal, and send enable signal at least one from control module, and send main test signal to initial input end; Multiple from control module generate respectively to the processor core at place test from test signal; At least one receiving enable signal utilizes the processor core to place from test signal and main test signal generated to test from control module.By the present invention, solve the testing scheme of polycaryon processor in prior art and there is the problem of steering logic more complicated, and then reach the effect simplifying polycaryon processor structure.
Description
Technical field
The present invention relates to polycaryon processor field, in particular to a kind of polycaryon processor and method of testing thereof and device.
Background technology
Polycaryon processor has become a development trend of industry member now, and complicated polycaryon processor chip at a high speed brings the challenge of each side such as control, power consumption to test.
First, in testing and control, concurrent testing mode (that is, simultaneously sending test massage to each kernel of processor) faces huge test control signal interconnect problem.Due to the restriction of explained hereafter, the I/O number of pins on single polycaryon processor, can not along with transistor size integrated in this chip growth in proportion.The two kinds of chips being respectively 180 nanometers and 35 nanometers with technology feature size contrast, and wherein, the number of transistors object of core Embedded increases by 45 times that ratio reaches signal pins number increase ratio on chip.And for a chip, it can be limited as the pin of test, use if a chip has 10 pins to can be used as test, when core each in this chip is tested, need the test mode that 8 pin observation is inner, then, when this chip is 4 core processor, need 4 control signals to carry out enable to 4 kernels, for this kind of situation, remaining 2 pins are also enough to decoding and produce 4 control signals; But when this chip is 8 core processors or more kernel, the control signal that remaining 2 pins are just not enough to generation 8 or more is come enable, occurs pin shortage of resources.That is, adopt test signal and control signal interconnected, each kernel of polycaryon processor is carried out to the mode of concurrent testing, there is the shortage of test resource in the increase understood along with processor cores, and this kind of test mode also can produce very high testing power consumption.
In order to reduce testing power consumption, propose the method for a kind of sub-module test (that is, carrying out to each kernel of processor test of dividing into groups), the power consumption making each organize the logical block consumption of parallel running is no more than the maximum power dissipation that chip can bear; In sub-module test, need to carry out enable to test kernel, and non-test kernel is turned off, existing a kind of in the serial polycaryon processor testing scheme be described of Intel Itanium processor, propose a kind of DFX(Xincludestestanddebug based on " T-Ring " structure, be test and debug the design carried out) access architectures.In this framework, achieve based on IEEE1149.1TAP(TestAccessPoints, test access point, being called for short TAP) the central test control device of controller realizes the testing and control of chip-scale, each core testing and control of having the IEEE1149.1TAP controller of core level to realize core simultaneously.The TAP of TAP and 8 core level of central control unit forms a TAP ring in the configurable mode of a kind of user, can access the TAP feature outside core and in core, and can turn off the kernel not needing to test.This kind has two features based on the testing scheme of " T-Ring " structure: the first, and the register outside all core and in core is all same length (8 bit); Second, except the instruction of standard, (namely steering order outside core and in core uses disjoint instruction space, namely the instruction in core is completely different from the instruction of the central control unit outside core), wherein, the instruction of so-called standard comprises bypass (BYPASS) instruction, access chip identification register (IDCODE) instruction etc.But, for a polycaryon processor, because the control outside the control relatively core in core, control usually fairly simple in core, in prior art, the equal meeting of register length outside core and in core causes the waste in space in core, and because the two uses the different instruction spaces, when testing processor core, needing to control to carry out the mutual of test signal and test data outward by the circuit arrangement of complexity and core, causing steering logic more complicated.
There is the problem of steering logic more complicated for the testing scheme of polycaryon processor in correlation technique, not yet propose effective solution at present.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of polycaryon processor and method of testing thereof and device, there is the problem of steering logic more complicated to solve the testing scheme of polycaryon processor in prior art.
To achieve these goals, according to an aspect of the present invention, provide a kind of proving installation of polycaryon processor, polycaryon processor comprises multiple processor core, proving installation comprises: main control module and multiple from control module, multiplely to connect successively from control module, one is provided with from control module in each processor core, eachly all to be connected with main control module from control module, wherein, main control module is for generating enable signal and main test signal, and send enable signal at least one from control module, and send main test signal to initial input end, wherein, initial input end is the multiple test inputs from control module after series connection, multiple from control module generate respectively to the processor core at place test from test signal, at least one receiving enable signal utilizes the processor core to place from test signal and main test signal generated to test from control module.
Further, main control module comprises: master controller; Master instruction register, is connected with master controller; And multiple master data register, all be connected with master instruction register with master controller, wherein, master instruction register is used for the master data register in the multiple master data register of gating, and the master data register be strobed produces enable signal or main test signal under the control of master controller.
Further, multiple master data register comprises the kernel enable data register for generation of enable signal, the number of bits of kernel enable data register equals the number of polycaryon processor inner treater core, wherein, main control module sends enable signal at least one from control module in the following manner: the logical value of each bit master controller configuration kernel enable data register; And the logical value correspondence of each bit exports to multiple from control module by main controller controls kernel enable data register, wherein, one receives the logical value of a bit from control module, and enable signal is logical one.
Further, master instruction register comprises the first shift circuit, for carrying out displacement generation first gating command to coded data under the control of primary controller, wherein, coded data is from the system host residing for external tester or polycaryon processor, first shift circuit is shifted into different sequences to coded data, produces different first gating command, the different master data register of gating.
Further, eachly to include from control module: from controller; From order register, be connected with from controller; First from data register, be connected respectively with from order register with from controller, wherein, first stores pattern configurations value from data register, first is used for when being produced from test signal by from order register gating from data register, or when not by from output mode Configuration Values when order register gating; And multiple second from data register, all with from controller, be connected from data register from order register with first, wherein, corresponding with pattern configurations value second is used for producing from test signal from the control of controller from data register.
To achieve these goals, according to a further aspect in the invention, provide a kind of polycaryon processor, this polycaryon processor comprises the proving installation of any one polycaryon processor that foregoing of the present invention provides.
To achieve these goals, according to a further aspect in the invention, provide a kind of method of testing of polycaryon processor, polycaryon processor comprises multiple processor core, main control module and multiple from control module, multiplely to connect successively from control module, one is provided with from control module in each processor core, eachly all to be connected with main control module from control module, main control module is for generating enable signal and main test signal, multiple from control module generate respectively to the processor core at place test from test signal, method of testing comprises: main control module sends enable signal at least one from control module, and send main test signal to initial input end, initial input end is the multiple test inputs from control module after series connection, and at least one receiving enable signal utilizes the processor core to place from test signal and main test signal generated to test from control module.
Further, main control module comprises master controller, master instruction register and multiple master data register, wherein, main control module generates enable signal and main test signal in the following manner: the master data register in the multiple master data register of main controller controls master instruction register gating; And the master data register that main controller controls is strobed produces enable signal or main test signal.
Further, multiple master data register comprises the kernel enable data register for generation of enable signal, the number of bits of kernel enable data register equals the number of polycaryon processor inner treater core, and main control module sends enable signal at least one from control module in the following manner: the logical value of each bit master controller configuration kernel enable data register; And the logical value correspondence of each bit exports to multiple from control module by main controller controls kernel enable data register, wherein, one receives the logical value of a bit from control module, and enable signal is logical one.
Further, comprise from controller, from instruction control unit, first from data register and multiple second from data register from control module, wherein, produce in the following manner from test signal from control module: control from order register gating first from data register from controller, or gating multiple second is from second data register from data register; If first is strobed from data register, then controls first from controller and produce from test signal from data register; If first is not strobed from data register, then first from data register output mode Configuration Values; And to control from controller and pattern configurations is worth corresponding second and produces from test signal from data register.
Pass through the present invention, adopt and comprise the proving installation of the polycaryon processor of following structure: main control module and multiple from control module, multiplely to connect successively from control module, and be arranged in multiple processor core respectively, eachly all to be connected with main control module from control module, wherein, main control module is for generating enable signal and main test signal, and send enable signal at least one from control module, and sending main test signal to initial input end, initial input end is the multiple test inputs from control module after series connection; Multiple from control module generate respectively to multiple processor core test from test signal; At least one receiving enable signal utilizes the processor core to place from test signal and main test signal generated to test from control module.By arranging main control module in polycaryon processor, be used for producing enable signal and main test signal, simultaneously, arrange respectively from control module in each processor core, be used for producing from test signal, achieve when needs are tested certain processor core, can by enable signal to carrying out enable from control module in this processor core, then utilize main test signal and this processor core is tested from test signal by producing from control module in this processor core; When needs are tested certain several processor core, can by enable signal to all carrying out enable from control module in these processor cores, then for concrete processor core, concrete utilization is by the testing these processor cores from test signal with from the main test signal of main control module from control module generation in these processor cores.By being produced the main test signal that can be used for testing the total characteristic of each processor core by main control module, by in concrete processor core from control module produce for the peculiar characteristic of this processor core carry out testing from test signal, when testing processor core, due to can produce from control module for test from test signal, without the need to obtaining a lot of test signal from main control module, all characteristics of processor core are tested, thus avoid needing to support calling of test signal by the circuit arrangement of complexity, solve the testing scheme of polycaryon processor in prior art and there is the problem of steering logic more complicated, and then reach the effect simplifying polycaryon processor structure.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of the proving installation according to the embodiment of the present invention;
Fig. 2 is the schematic diagram of main control module in the proving installation according to the embodiment of the present invention;
Fig. 3 is the schematic diagram from control module in the proving installation according to the embodiment of the present invention;
Fig. 4 is another schematic diagram of the proving installation according to the embodiment of the present invention; And
Fig. 5 is the process flow diagram of the method for testing according to the embodiment of the present invention.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the present invention in detail in conjunction with the embodiments.
Embodiments provide a kind of proving installation of polycaryon processor, below the proving installation of the polycaryon processor that the embodiment of the present invention provides be specifically introduced:
Fig. 1 is the schematic diagram of the proving installation of polycaryon processor according to the embodiment of the present invention, as shown in Figure 1, the proving installation of the polycaryon processor of the embodiment of the present invention comprises main control module 10 and multiple from control module 31 to 3n, multiplely to connect successively from control module 31 to 3n, and be arranged in multiple processor core 21 to 2n respectively, eachly all to be connected with main control module from control module, namely, one is all arranged from control module in each processor core, first is arranged on first processor core 21 from control module 31, and is connected with main control module 10; Second is arranged on the second processor core 22 from control module 32, and is connected with main control module 10; By that analogy, n-th is arranged on the n-th processor core 2n from control module 3n, and is connected with main control module 10, and wherein, the value of n equals the number of processor core in polycaryon processor.When testing the processor core in polycaryon processor, main control module 10 generates enable signal and main test signal, and sends enable signal at least one from control module, and to initial input end I
0send main test signal, so-called initial input end is the multiple test inputs from control module after series connection, multiple from control module generate respectively to multiple processor core test from test signal, that is, first from control module 31 generate to first processor core 21 test from test signal, second from control module 32 generate to the second processor core 22 test from test signal, n-th from control module 3n generate to the n-th processor core 2n test from test signal, what receive enable signal then utilizes from control module testing residing processor core from test signal with from the main test signal of main control module of self generating, suppose that first have received enable signal from control module 31 and n-th from control module 3n, then first main test signal and first is utilized to test from test signal first processor core 21 from control module 31, n-th utilizes main test signal and n-th to test from test signal the n-th processor core 2n from control module 3n, wherein, first processor core is for first from the processor core residing for control module 31, first from test signal be first from control module 31 produce test signal, n-th processor core is for n-th from the processor core residing for control module 3n, n-th from test signal be n-th from control module 3n produce test signal.
The embodiment of the present invention by arranging main control module in polycaryon processor, be used for producing enable signal and main test signal, simultaneously, arrange respectively from control module in each processor core, be used for producing from test signal, achieve when needs are tested certain processor core, can by enable signal to carrying out enable from control module in this processor core, then utilize main test signal and this processor core is tested from test signal by producing from control module in this processor core; When needs are tested certain several processor core, can by enable signal to all carrying out enable from control module in these processor cores, then for concrete processor core, concrete utilization is by the testing these processor cores from test signal with from the main test signal of main control module from control module generation in these processor cores.The main test signal that can be used for testing the total characteristic of each processor core is produced by main control module, by in concrete processor core from control module produce for the peculiar characteristic of this processor core carry out testing from test signal, when testing processor core, due to can produce from control module for test from test signal, without the need to obtaining a lot of test signal from main control module, all characteristics of processor core are tested, thus avoid needing to support calling of test signal by the circuit arrangement of complexity, solve the testing scheme of polycaryon processor in prior art and there is the problem of steering logic more complicated, and then reach the effect simplifying polycaryon processor structure.
Particularly, Fig. 2 is the structural representation of main control module in the proving installation according to the embodiment of the present invention, as shown in Figure 2, main control module 10 mainly comprises master controller, master instruction register, multiple master data register, first MUX and the second MUX, and direct input block, wherein, master instruction register is all connected with master controller with multiple master data register, multiple master data register is also all connected with the first MUX, the parallel output of master instruction register is connected to the gating end of the first MUX, the Serial output of master instruction register is connected to the input of the second MUX, the output of the first MUX is connected to the input of the second MUX, the gating end of the second MUX is connected with master controller (not shown), the coded data sent from serial data input TDI outputs in master instruction register and each master data register by direct input block, the various director datas that coded data uses when being and testing processor core, below illustrate effect and the principle of work of each structure composition in main control module:
Master controller is at test clock signals TCK, under the control of test mode select signal TMS and test macro reset signal TRST, produce the order register control signal and the data register control signal that act on each register in main control module, control master instruction register and multiple master data register processes the coded data sent from serial data input TDI, wherein, coded data, test clock signals TCK, test mode select signal TMS and test macro reset signal TRST is all from the system host residing for external tester or polycaryon processor, the order register control signal that master controller produces comprises: order register lock-on signal, instruction register shift signal and order register update signal, order register lock-on signal controls master instruction register by specific sequence capturing in master instruction register, this specific sequence is generally the initial value of master instruction register, the test instruction that instruction register shift signal control master instruction register pair is sent by TDI is shifted, order register update signal controls master instruction register and is updated in master instruction register by the new instruction be shifted, the data register control signal that master controller produces comprises: data register lock-on signal, data register shift signal and data register update signal, data register lock-on signal controls master data register and captures in master data register by specific logic sequence, so-called specific logic sequence is generally the parallel initial value of master data register herein, data register shift signal controls master data register and is shifted to the test data sent by TDI, data register update signal is used for the test data be shifted to be updated in master data register.
The principle producing main test signal is: master instruction register is shifted to coded data under the control of master controller, produce the first gating command, this first gating command is used for a master data register in the multiple master data register of gating, wherein, master instruction register comprises shift circuit (hereinafter referred to as the first shift circuit), master controller carries out displacement to produce the first gating command by controlling the first shift circuit to coded data, if controlling the first shift circuit is shifted into different sequences to coded data, then produce the first different gating command, the master data register that correspondingly gating is different, if the master data register of gating is the kernel enable data register with ena-bung function, then produce enable signal by main controller controls kernel enable data register further, wherein, it is different that master controller carries out the configuration of bit logic to kernel enable data register, produce different enable signals, illustrate, if kernel enable data register is 4bit position, if configuring its output signal is 0010, then be equivalent to the enable signal producing the kernel corresponding with the 3rd bit, if the master data register of gating is non-core enable data register, then produce main test signal by the data register of this gating of main controller controls further.
Particularly, if master controller is under the control of TCK and TMS, produce order register control signal.Particularly, the specific logic sequence of master instruction registers capture is controlled by order register lock-on signal; After holding the test instruction sent to be shifted by instruction register shift signal control master instruction register pair TDI; Control master instruction register by order register update signal the new instruction after being shifted is upgraded.When instruction register shift signal is effective, control the second MUX and select master instruction register Serial output, output to outside chip via TDO, until after end-of-shift, value in master instruction register reaches steady state (SS), to utilize the shift value reaching steady state (SS) in master instruction register to select master data register.
If master controller is under the control of TCK and TMS, produce data register control signal, then data register control signal control data register exports via the second MUX, specifically which data register exports, the signal being exported to the first MUX gating end by master instruction register decides, master instruction register carrys out the different master data register of gating by the different instruction that is shifted, multiple master data register comprises carries out enable master data register to processor core, each corresponding processor core of this data register, after this master data register with core ena-bung function is strobed, this core enable data register can be configured according to the concrete test instruction received from TDI, with make main control module issue enable signal to need carry out in the processor core tested from control module.When the follow-up kernel enable to this is tested, main test signal is sent to the kernel after enable again by the different master data register of master instruction register gating, the main test signal of carrying out kernel test can comprise test pattern configuration-direct, EXTEST instruction, IDCODE instruction etc., such as, when the test pattern configuration data register in multiple master data register is strobed, test pattern configuration-direct kernel being carried out to test pattern configuration can be produced; When the master data register that can produce EXTEST instruction is strobed, can produce EXTEST instruction, this instruction is called external testing instruction, tests for and peripheral circuit interconnected to the plate level of kernel; When the master data register that can produce IDCODE instruction is strobed, can produce IDCODE instruction, this instruction is called the instruction of access chip identification register, for carrying out gating to the ID register in kernel.
Fig. 3 is a structural representation from control module in the proving installation according to the embodiment of the present invention, as shown in Figure 3, mainly comprise from controller from control module, from order register, first from data register, multiple second from data register, 3rd to the 6th MUX, and direct input block, wherein, from order register, first all with from controller is connected from data register from data register with multiple second, multiple second is also all connected with the 3rd MUX from data register, first is connected to the gating end of the 3rd MUX from data register, and be connected with the 4th MUX, 4th MUX is also connected with the output of the 3rd MUX, the gating end of the 4th MUX is connected to from order register, and be connected with the 5th MUX, 5th MUX is also connected with the output of the 4th MUX, the gating end of the 5th MUX is connected with from controller (not shown), 6th MUX can be a two-way selector switch, its output of input for connecting the 5th MUX, another input is for connecting serial data input TDI, its gating termination receives the enable signal TAP_SEL sended over from the master data register with ena-bung function in main control module, below illustrate effect and the principle of work of each structure composition from control module:
From controller at test clock signals TCK, under the control of test mode select signal TMS and test macro reset signal TRST, produce the order register control signal and the data register control signal that act on each register from control module, control from order register, first processes the coded data sent from serial data input TDI from data register and multiple second from data register, wherein, control from order register, the test pattern configuration-direct of immigration to be updated to from order register from controller, this test pattern configuration-direct is used for the gating signal of gating first from data register through producing after the decoding scheme in order register, control first from controller, from data register, displacement renewal is carried out to the mode configuration data coded data, and in mode the value of configuration data be parameter, by the 3rd MUX gating multiple second from certain data register second from data register, the value gating of different mode configuration data different second from data register, second stores in the test control signal data captured from coded data under the control of controller from data register, or test mode observation signal data.By the way gating certain second after data register, because the test instruction parallel output received from TDI can produce from test signal from the control of controller from data register by this second, and after test terminates, test mode is caught, obtain test mode data, after it is strobed, can be shifted under the control of controller, by the data serial displacement stored in it, and output to chip External Observation via TDO.
If the 6th MUX do not receive from main control module enable signal (namely, TAP_SEL is logical zero), then should be bypassed from control module, and be equivalent to this TDI from control module end to hold with TDO directly connect, this is not tested from control module; If the 6th MUX receive from main control module enable signal (namely, TAP_SEL is logical one), then should be strobed from control module, in such cases by this from performing this test from processor core described in control module from controller control module.Particularly, if from controller under the control of TCK and TMS, produce order register control signal, then order register control signal controls to export from order register via the 5th MUX, realizes gating from order register Serial output, if from controller under the control of TCK and TMS, produce data register control signal, then data register control signal controls first and second to export via the 5th MUX from data register from data register or certain, realize gating first from data register or certain is second from data register, specifically first from data register or certain is second from data register, decided by the command value of the parallel output from order register, if pass through the 4th MUX gating first from data register from order register, then first carries out serial-shift from data register, output to TDO, if from order register by the 4th MUX gating second from data register, then under the first gating from data register, determine that concrete second carries out serial-shift from data register, output to TDO.Specifically which is second from data register, decides from the value of the configuration mode data register by first.
In the embodiment of the present invention, by being set to carry out gating by first from the configuration data register from data register by second, be set to carry out gating by from the shift value order register from data register by first, this kind is by the mode of secondary gating, can make from the length of order register shorter, thus simplify from the instruction realization control module.
Based on above principle, achieve when testing certain processor core, only need issue enable signal and a part of test signal (namely by main control module, main test signal), be arranged in this processor core from control module utilize self to produce from test signal and the main test signal that receives, this processor core is tested, this test mode is without the need to obtaining a lot of test signal from main control module, all characteristics of processor core are tested, avoid needing to support calling of test signal by the circuit arrangement of complexity, reach the effect simplifying polycaryon processor structure.
In embodiments of the present invention, in order to simplify test logic further, two classes can be set to by from second in control module from data register, one class is used to the test control signal data in memory encoding data, one class is used to the state observation signal data in memory encoding data, wherein, under test control signal data are used for being configured in certain specific test pattern, need the control signal that the test controlled is correlated with, under state observation signal data is used for being stored in certain specific test pattern, need the test mode signal of observation.
Preferably, in the proving installation of the embodiment of the present invention, can the number in master data register with the bit of the kernel enable data register of ena-bung function be arranged equal with the number of polycaryon processor inner treater core, such as, polycaryon processor is n core processor, then kernel enable data register is set to n-bit.
By the number of the bit of kernel enable data register in master data register is arranged to equal with the processor core number of polycaryon processor, avoid as main control module distributes the processor space that too much register space causes waste, it also avoid and carry out circuit arrangement to support this part space, further simplify the structure of polycaryon processor.
Fig. 4 is another schematic diagram of the proving installation according to the embodiment of the present invention, for four core processor chips in this figure, particularly illustrate the annexation from control module in main control module and each processor core, as shown in Figure 4: main control module and all utilize JTAG(JointTestActionGroup from control module, combined testing action group) signal carries out control observation, namely, main control module and including from control module: test data serial input (TDI) is held, test pattern selects (TMS) end, test clock (TCK) is held, test data Serial output (TDO) end and test reset signal (TRST) end.
From the kernel enable register in main control module output signal TAP_SEL by logical device with behind the door, access is held from the TMS of control module, each TMS from control module end all outputs signal TAP_SEL by coupled receiving with door A1, the tms signal in the direct received code data of another input end of this logical device and door; The output signal TAP_SEL of kernel enable register by another logical device with behind the door, access TCK end, each TCK from control module end all outputs signal TAP_SEL by coupled receiving with door A2, tck signal in coded data by this logical device with behind the door, access and hold from the TCK of control module; The output signal TAP_SEL of kernel enable register also directly accesses the gating end of the 6th MUX A.When certain is logical zero from the enable signal that control module receives, is equivalent to this and is bypassed from control module; When certain is logical one from the enable signal that control module receives, this is from the mode of control module by matching with main control module, test from the processor core residing for control module this, concrete test philosophy is same as described above, repeats no more herein.
Composition graphs 2-4 can find out, order register in master & slave control module is cascaded, receive enable signal from control module in which processor core, be in this processor core from control module from order register just together with the master instruction register string main control module.In master & slave control module, the annexation of data register has different from the annexation of order register in the two, when not needing to test certain kernel, then without the need to conducting interviews from the data register control module to this kernel, can send TAP_SEL is that the signal of logical zero is to this from control module, like this, can arrange in main control module and carry out displacement output to observe the length of the master data register of test data be that the enable length of data register from control module adds 1, reach saving shift time.In embodiments of the present invention, the number of the data register in master & slave control module can arbitrary extension, realizes the control signal configuration effectively meeting different test pattern.
When specifically testing kernel, first send core test enable signal to from control module by main control module, receive being strobed from the data register control module of enable signal, the demand according to test correspondingly produces from test signal.Be strobed from control module also produce corresponding instruction to master controller and gating from the order register control module, to select corresponding data register.The last main test signal that data register produces in main control module, and the data register from control module be strobed produce from test signal acting in conjunction, complete concrete kernel test.
The proving installation of the polycaryon processor proposed in the embodiment of the present invention only uses five of JTAG signals can complete the observation of control to test pattern and test signal, do not need the input/output signal taking other again, thus solve the problem of test pin resource anxiety; Simultaneously this host-guest architecture can be enable and close the test of any one core in part flexibly, effectively reduces testing power consumption; This testing and control structure can be expanded flexibly in addition, only needs corresponding processor core to be connected on ring when needs integrated more processing device core, can meet the demand of future processor flexible structure expansion.And adopting this structure, the instruction of master & slave control module can independent design, simplified design.
The embodiment of the present invention additionally provides a kind of method of testing of polycaryon processor, the proving installation that the method for testing of this embodiment mainly adopts embodiment of the present invention foregoing to provide carries out, Fig. 5 is the process flow diagram of the method for testing according to the embodiment of the present invention, as shown in Figure 5, the detection method of this embodiment comprises the steps S501 and S503:
S501: main control module sends enable signal at least one from control module, and send main test signal to initial input end, initial input end is the multiple test inputs from control module after series connection; In embodiments of the present invention, multiplely to connect successively from control module, and be arranged in multiple processor core respectively, eachly all to be connected with main control module from control module, main control module is for generating enable signal and main test signal, multiple from control module generate respectively to multiple processor core test from test signal, when needs are tested certain or certain several processor core, main control module sends enable signal from control module then in this or these processor core, and main test signal is sent to initial input end.
S503: at least one receiving enable signal utilizes the processor core to place from test signal and main test signal generated to test from control module, namely, receive enable signal from control module, utilize self to produce from test signal and the main test signal that receives, this is tested from the processor core residing for control module.
The embodiment of the present invention by arranging main control module in polycaryon processor, be used for producing enable signal and main test signal, simultaneously, arrange respectively from control module in each processor core, be used for producing from test signal, achieve when needs are tested certain processor core, can by enable signal to carrying out enable from control module in this processor core, then utilize main test signal and this processor core is tested from test signal by producing from control module in this processor core; When needs are tested certain several processor core, can by enable signal to all carrying out enable from control module in these processor cores, then for concrete processor core, concrete utilization is by the testing these processor cores from test signal with from the main test signal of main control module from control module generation in these processor cores.By being produced the main test signal that can be used for testing the total characteristic of each processor core by main control module, by in concrete processor core from control module produce for the peculiar characteristic of this processor core carry out testing from test signal, when testing processor core, due to can produce from control module for test from test signal, without the need to obtaining a lot of test signal from main control module, all characteristics of processor core are tested, avoid needing to support calling of test signal by the circuit arrangement of complexity, solve the testing scheme of polycaryon processor in prior art and there is the problem of steering logic more complicated, and then reach the effect simplifying polycaryon processor structure.
Particularly, main control module comprises master controller, master instruction register and multiple master data register, and wherein, main control module generates enable signal and test signal in the following manner:
Master controller receives test clock signals TCK, test mode select signal TMS and test macro reset signal TRST, and under the effect of TCK and TMS, control master instruction register and multiple master data register processes coded data, wherein, coded data, test clock signals TCK, test mode select signal TMS and test macro reset signal TRST are all from the system host residing for external tester or polycaryon processor, master instruction register is shifted to coded data under the control of master controller, produce the first gating command, this first gating command is used for a master data register in the multiple master data register of gating, if the master data register of gating is the kernel enable data register with ena-bung function, then produce enable signal by main controller controls kernel enable data register further, wherein, it is different that master controller carries out the configuration of bit logic to kernel enable data register, produce different enable signals, illustrate, if kernel enable data register is 4bit position, if configuring its output signal is 0010, then be equivalent to the enable signal producing the kernel corresponding with the 3rd bit, if the master data register of gating is non-core enable data register, then produce main test signal by the data register of this gating of main controller controls further, particularly, controlling master data register mainly through data register lock-on signal captures in master data register by specific logic sequence, control master data register by data register shift signal and the main test signal of displacement output generation is carried out to the test data sent by TDI, and be used for the test data be shifted to be updated in master data register by data register update signal.
Comprise from controller from control module, from instruction control unit, first from data register and multiple second from data register, wherein, produce in the following manner from test signal from control module:
Test clock signals TCK is received from controller, test mode select signal TMS and test macro reset signal TRST, and control from order register under the effect of TCK and TMS, first processes from data register and multiple master data register coded data, coded data is being shifted from the control of controller from order register, produce the second gating command, this second gating command is used for gating first from data register or certain is second from data register, if gating first is from data register, then produce from test signal from data register by controlling first from controller further, concrete control principle is identical with the principle that above-mentioned main controller controls master data register produces main test signal, repeat no more herein, if gating second is from data register, then different from the pattern configurations value of data register parallel output according to first, gating different second from data register, when certain second be strobed from data register after, produce from test signal from data register by control from controller that this is strobed second further, concrete control principle is identical with the principle that above-mentioned main controller controls master data register produces main test signal, repeats no more herein.
In addition, the embodiment of the present invention additionally provides a kind of polycaryon processor, this polycaryon processor can be any polycaryon processor comprising any one proving installation that embodiment of the present invention foregoing provides, and also can be the polycaryon processor of any one method of testing adopting embodiment of the present invention foregoing to provide.
As can be seen from the above description, the invention solves the testing scheme of polycaryon processor in prior art and there is the problem of steering logic more complicated, reach the effect simplifying polycaryon processor structure.
It should be noted that, can perform in the computer system of such as one group of computer executable instructions in the step shown in the process flow diagram of accompanying drawing, and, although show logical order in flow charts, but in some cases, can be different from the step shown or described by order execution herein.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on network that multiple calculation element forms, alternatively, they can realize with the executable program code of calculation element, thus, they can be stored and be performed by calculation element in the storage device, or they are made into each integrated circuit modules respectively, or the multiple module in them or step are made into single integrated circuit module to realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the proving installation of a polycaryon processor, described polycaryon processor comprises multiple processor core, it is characterized in that, described proving installation comprises: main control module and multiple from control module, describedly multiplely to connect successively from control module, be provided with one in each processor core from control module, to be eachly all connected with described main control module from control module, wherein
Described main control module is for generating enable signal and main test signal, and send described enable signal at least one from control module, and send described main test signal to initial input end, wherein, described initial input end is the described multiple test inputs from control module after series connection;
Described multiple from control module generate respectively to the processor core at place test from test signal;
At least one receiving described enable signal utilizes the processor core to place from test signal and described main test signal generated to test from control module.
2. proving installation according to claim 1, is characterized in that, described main control module comprises:
Master controller;
Master instruction register, is connected with described master controller; And
Multiple master data register, all be connected with described master instruction register with described master controller, wherein, described master instruction register is used for the master data register in multiple master data register described in gating, and the master data register be strobed produces described enable signal or described main test signal under the control of described master controller.
3. proving installation according to claim 2, it is characterized in that, described multiple master data register comprises the kernel enable data register for generation of described enable signal, the number of bits of described kernel enable data register equals the number of described polycaryon processor inner treater core, wherein, described main control module sends described enable signal at least one from control module in the following manner:
Described master controller configures the logical value of each bit in described kernel enable data register; And
The logical value correspondence of each bit exports to described multiple from control module by kernel enable data register described in described main controller controls, and wherein, one receives the logical value of a bit from control module, and described enable signal is logical one.
4. proving installation according to claim 2, it is characterized in that, described master instruction register comprises the first shift circuit, for carrying out displacement generation first gating command to coded data under the control of described primary controller, wherein, described coded data is from the system host residing for external tester or described polycaryon processor, and described first shift circuit is shifted into different sequences to described coded data, produce the first different gating command, the master data register that gating is different.
5. proving installation according to claim 1 and 2, is characterized in that, eachly includes from control module:
From controller;
From order register, be connected from controller with described;
First from data register, be connected respectively from order register with described from controller with described, wherein, described first stores pattern configurations value from data register, described first is used for when by described described from test signal from producing order register gating from data register, or when not by described from exporting described pattern configurations value when order register gating; And
Multiple second from data register, all with described from controller, to be describedly connected from data register from order register with described first, wherein, corresponding with described pattern configurations value second from data register be used for described produces from the control of controller described in from test signal.
6. a polycaryon processor, is characterized in that, comprises the proving installation according to any one of claim 1 to 5.
7. the method for testing of a polycaryon processor, it is characterized in that, described polycaryon processor comprises main control module, multiple processor core and multiple from control module, describedly multiplely to connect successively from control module, one is provided with from control module in each processor core, eachly all to be connected with described main control module from control module, described main control module is for generating enable signal and main test signal, described multiple from control module generate respectively to the processor core at place test from test signal, described method of testing comprises:
Described main control module sends described enable signal to described at least one from control module, and sends described main test signal to initial input end, and described initial input end is the described multiple test inputs from control module after series connection; And
At least one receiving described enable signal utilizes the processor core to place from test signal and described main test signal generated to test from control module.
8. method of testing according to claim 7, it is characterized in that, described main control module comprises master controller, master instruction register and multiple master data register, and wherein, described main control module generates described enable signal and described main test signal in the following manner:
Master data register in multiple master data register described in master instruction register gating described in described main controller controls; And
The master data register that described main controller controls is strobed produces described enable signal or described main test signal.
9. method of testing according to claim 8, it is characterized in that, described multiple master data register comprises the kernel enable data register for generation of described enable signal, the number of bits of described kernel enable data register equals the number of described polycaryon processor inner treater core, and described main control module sends described enable signal at least one from control module in the following manner:
Described master controller configures the logical value of each bit in described kernel enable data register; And
The logical value correspondence of each bit exports to described multiple from control module by kernel enable data register described in described main controller controls, and wherein, one receives the logical value of a bit from control module, and described enable signal is logical one.
10. the method for testing according to claim 7 or 8, it is characterized in that, describedly comprise from controller, from instruction control unit, first from data register and multiple second from data register from control module, wherein, described produce in the following manner from control module described from test signal:
Described from controller control described from described in order register gating first from data register, or multiple second from second data register from data register described in gating;
If described first is strobed from data register, then described described from test signal from data register generation from controller control described first;
If described first is not strobed from data register, then described first from data register output mode Configuration Values; And
Described from controller control to be worth with described pattern configurations corresponding described second to produce from data register described in from test signal.
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| CN106443412B (en) * | 2016-09-09 | 2019-04-23 | 杭州万高科技股份有限公司 | A kind of IC test device and method |
| CN108415842B (en) * | 2018-03-21 | 2021-01-29 | 杭州中天微系统有限公司 | Multi-core processor |
| CN109344018B (en) * | 2018-09-10 | 2022-03-29 | 深圳忆联信息系统有限公司 | Multi-core CPU test method and device, computer equipment and storage medium |
| CN111614166B (en) * | 2020-06-10 | 2021-08-24 | 中国科学院近代物理研究所 | Excitation power supply control system and method based on SFP + multi-module accelerator |
| CN112133072B (en) * | 2020-09-23 | 2021-07-06 | 中国兵器工业集团第二一四研究所苏州研发中心 | Test system and test method for LoRa wireless data acquisition device |
| CN113299335B (en) * | 2021-05-24 | 2023-01-31 | 长江存储科技有限责任公司 | Test method, test system and test equipment for memory device |
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