CN103365749B - Multi-core processor debugging system - Google Patents
Multi-core processor debugging system Download PDFInfo
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- CN103365749B CN103365749B CN201310224012.8A CN201310224012A CN103365749B CN 103365749 B CN103365749 B CN 103365749B CN 201310224012 A CN201310224012 A CN 201310224012A CN 103365749 B CN103365749 B CN 103365749B
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Abstract
The invention relates to a multi-core processor debugging system which comprises a master controller, microprocessor IPs (Internet Protocols) and a debugging state controller.Debugging control units in the microprocessor IPs and a debugging control unit in the master controller are connected with the debugging state controller for feeding debugging requests of the microprocessor IPs and the master controller back to the debugging state controller, and transmitting debugging response signals sent by the debugging state controller to the microprocessor IPs and the master controller. In the debugging system, the number of the integrated microprocessor IPs is unrestricted, debugging structures in the microprocessor IPs are not required to be changed, and the debugging system is easy to realize. The debugging state controller receives debugging request signals of the master controller and the microprocessor IPs, and synchronously control debugging of the master controller and the microprocessor IPs, so that cores in the multi-core processor enter or exit a debugging mode simultaneously.
Description
Technical field
The present invention relates to a kind of polycaryon processor, particularly make the polycaryon processor of two-dimensional grid (mesh) framework possess the design of the embedded debug system of on-line debugging ability.
Background technology
Debugging plan for polycaryon processor designs domestic and international research institution and is proposed some oneself solution, although these methods are different, can be classified as two large classes according to its fundamental characteristics:
● based on traditional JTAG adjustment method.
Based on the adjustment method of traditional JTAG generally all by the JTAG mouth on IP kernel different on MPSoC is carried out effective organization and management, thus realize the adjustable of multiple nucleus system.Such Measures compare has typically been studied:
serial approach, the JTAG mouth serial of each IP kernel in system is got up by the method, and (namely system TDI connects the TDI of Core0, the TDO of Core0 connects the TDI of Corel, the TDO of Corel connects the TDI... of CoreN), the method operates very simple, does not need to increase any hardware resource.Because each lP core shares TMS, TCK, TRST tri-signals, so their JTAG mouth works all the time under same state, so they can scan at the pin of synchronization to IP kernels all on System on Chip/SoC, so just can be analyzed the running status at each core of synchronization by feedback data, but its shortcoming also clearly, when needing to debug separately the some core in system, this method almost cannot be accomplished.
increase the multiple nucleus system adjustment method of debugging mode base pin selection, the method by increasing the multiple jtag interfaces for selecting the pin of debugging mode to come in management system on chip, thus realizes the adjustable to independent IP kernel a certain in system.The shortcoming of the method will increase in systems in which more for the pin that debugging mode is selected, and in system, IP kernel is more, and the number of pins of required increase is more, and this is that modern designs is difficult to accept.
● based on the adjustment method of tracking technique.
Main thought is, first arranges monitoring point according to debugging demand, and monitoring point is once be triggered, and will the target information of collecting be needed to write back peculiar buffer memory, first debugger reads cache information, then resolves these information thus reaches debugging purpose.The method has a common drawback, cannot debug communicating between IP kernel in system.
Multinuclear is debugged, even based on the debugging framework of bus, be also very difficult problem, perfectly do not solved especially in the polycaryon processor based on mesh framework, in especially synchronous at multinuclear and cross debugging.
Summary of the invention
The technical matters that the present invention solves is: overcome the deficiencies in the prior art, provide a kind of polycaryon processor debug system, realize the debugging synchro control to master controller and microprocessor IP, make each core in polycaryon processor enter simultaneously or exit debugging mode.
Technical scheme of the present invention is: a kind of polycaryon processor debug system, comprises microprocessor IP, master controller, debugging mode controller, debug command write bus, Debugging message read bus; Described microprocessor IP is arranged in two-dimensional mesh grating texture, and each microprocessor IP comprises microprocessor IP debugging communication link unit and microprocessor IP debugging control module; Described master controller comprises the serial debug interface of master controller, the debugging communication link unit of master controller, the storage space external interface unit of master controller, the debug control unit of master controller; The debugging communication link unit of master controller realizes the serial debug interface of master controller and the mutual conversion between 8 bit data of transmission and 32 bit data of master controller internal bus; 32 output data lines, address wire and write signals that the storage space external interface unit that debug command write bus includes master controller sends, debug command write bus is connected with the storage space external interface unit of master controller, the write bus of debug command simultaneously is also connected with the microprocessor IP debugging communication link unit unit of each microprocessor IP inside, for microprocessor IP debugging communication link unit provides debug command; Debugging message read bus is the data line of 32, be connected with the input data line of the storage space external interface unit of master controller, Debugging message read bus is also connected with the microprocessor IP debugging communication link unit unit of each microprocessor IP inside simultaneously, the Debugging message of each microprocessor IP is outputted to the storage space external interface unit of master controller; Whether the address information exported in the microprocessor IP debugging communication link unit judges debug command write bus in each microprocessor IP is for this microprocessor IP, when judged result is for being, receive the data message in debug command write bus, Parallel debugging information read bus sends debugging reply data; The storage space external interface unit of master controller is also connected with debugging mode controller, for generation of the debug reset signal exiting debugging mode; Each microprocessor IP debugging control module of microprocessor IP inside and the debug control unit of master controller are all connected to debugging mode controller, for the debug request of each microprocessor IP and master controller is fed back to debugging mode controller, the debugging answer signal simultaneously also for being sent by debugging mode controller is sent to each microprocessor IP and master controller; The output data line of master controller serial line interface, the input data line of the master controller serial line interface serial debug Interface realization by master controller and the data information transfer of outside; External interface debugging enable signal and external interface debugging trigger pip all deliver to debugging mode controller, enter debugging mode for judging and triggering polycaryon processor;
Described debugging mode controller comprises or door, with door, not gate, the first two-way selector switch, the second two-way selector switch, the first trigger, the second trigger, the 3rd trigger; By every two microprocessor IP debugging control modules to debugging mode controller send enter debugging mode marking signal deliver to one or, above-mentioned all or door is exported and delivers to another or door more simultaneously; The result that above-mentioned another or door export again with by master controller to debugging mode controller send enter debugging mode marking signal deliver to the 3rd or; Above-mentioned 3rd or a result exported deliver to the S1 port of the first two-way selector switch, and external interface debugging trigger pip inputs to the S0 port of the first two-way selector switch simultaneously; Debug reset signal inputs to the reset terminal R of the first trigger and the reset terminal R of the second trigger simultaneously; The reset signal of external interface inputs to the control end C of the first two-way selector switch and the control end C of the second two-way selector switch simultaneously; One road signal of external interface debugging enable signal delivers to the S0 port of the second two-way selector switch; Polycaryon processor internal clock signal inputs to the CLK port of the first trigger and the CLK port of the second trigger respectively; The D port of the first two-way selector switch is connected to the D port of the first trigger; The D port of the second two-way selector switch is connected to the D port of the second trigger; The S1 port of the second two-way selector switch is connected to the reset terminal R of the second trigger; The Q port of the second trigger is delivered to and door through non-another road signal debugging enable signal behind the door with external interface simultaneously, and the above-mentioned result exported with door is delivered to a clock period of the 3rd flip-flop delays; Result after delay exports the S port of the second trigger to; The signal that the Q port of the second trigger and the Q port of the first trigger export is sent to each microprocessor IP and master controller as debugging answer signal.
The present invention's advantage is compared with prior art:
(1) debugging plan is not only applicable to the design of the microprocessor IP polycaryon processor that is processing unit, also can be used for designing with the polycaryon processor that other IP with debug port is processing unit, there is simplicity of design, change few feature, to greatest extent reduce change bring test, checking workload and design risk;
(2) debugging plan is not by the restriction of microprocessor IP kernel number integrated in polycaryon processor, is applicable to the polycaryon processor of two-dimensional grid (mesh) framework, has extensibility and tailorability;
(3) ensure under external signal reset condition, the debug control signals of the inner each microprocessor IP of polycaryon processor is the external debug interface signal state of chip, so just makes polycaryon processor directly can enter debugging mode in the reset state.
(4) multinuclear process any one core inner owing to performing debug command, run into debugging breakpoints or observation station and after entering debugging mode, all can trigger core all in polycaryon processor chip and enter debugging mode.
(5) be designed with special debugging and exit control signal, make all cores in polycaryon processor chip exit debugging mode simultaneously, continue to run simultaneously, ensure the synchronous of operation.
(6) chip exterior debug enable interface signal effective time, polycaryon processor, under control signal effect is exited in debugging, although can temporarily make the debugging enable signal of each microprocessor of chip internal IP invalid, exits debugging mode; But after a clock delay, the debugging enable signal of each core can revert to effective status again, allows each core again to enter debugging mode.
Accompanying drawing explanation
Fig. 1 is polycaryon processor debug system one-piece construction schematic diagram;
Fig. 2 is debugging mode controller architecture schematic diagram.
Embodiment
The polycaryon processor debug system designed according to this debugging plan, mainly contains following embodiment:
In Fig. 1, microprocessor IP101 is arranged as two-dimensional grid mesh framework, except being configured with normal arithmetic logical unit, also comprises the debugging communication link unit 102 of microprocessor IP and the debug control unit 103 of microprocessor IP.
Master controller 111, except being configured with normal arithmetic logical unit, CACHE system, floating point unit, internal bus and interruption control module, also comprise the debugging communication link unit 110 of the serial debug interface 109 of master controller, master controller, the storage space external interface unit 112 of master controller, the debug control unit 113 of master controller.
Debugging mode controller 108, is responsible for the control entering and exit debugging mode to polycaryon processor.
Debug command write bus 104,32 output data lines, address wire and write signals being sent by the storage space external interface unit 112 of master controller form.Be connected with each microprocessor IP debugging communication link unit 102, for each microprocessor IP101 provides debug command.
Debugging message read bus 105, as the data line of 32, is directly connected with the input data line of the storage space external interface unit 112 of master controller.Be connected with each microprocessor IP debugging communication link unit 102, be responsible for the storage space external interface unit 112 Debugging message of microprocessor IP101 being outputted to master controller.
The control signal 107 that debugging mode controller 108 sends, enters as control microprocessor IP101 and master controller 111 and exits the debugging answer signal of debugging mode.
External interface debugging enable signal 117, only when this signal is effective, just allows polycaryon processor to enter debugging mode, otherwise, exit debugging mode.
External interface debugging trigger pip 118, when this signal is high level, triggers polycaryon processor and enters debugging mode.
The control signal 107 that debugging mode controller 108 sends is connected with the debug control unit 113 of master controller with the debug control unit 103 of each microprocessor IP, and the debugging answer signal sent by debugging mode controller 108 is sent to the debug control unit 103 of microprocessor IP and the debug control unit 113 of master controller.
Input Debugging message in polycaryon processor outside enters master controller serial line interface 109 by the input data line 115 of master controller serial line interface, and master controller serial line interface 109 receives serial data, is reduced to octet data.Octet data assemblies after reduction is become 32 digital data by the debugging communication link unit 110 of master controller, and is divided into address information, write data message, read-write flag information.The debug control unit 113 of master controller utilizes these information, completes the access for master controller internal register, storer and IO space under debugging mode.When polycaryon processor exports Debugging message, the debug control unit 113 of master controller will debug the debugging communication link unit 110 of the 32 bit data input master controllers obtained, the debugging communication link unit 110 of master controller is according to bytewise, divide and output to master controller serial line interface 109 4 times, utilize the output data line 114 of master controller serial line interface to export.
For the debugging of microprocessor IP, the debug command sent from the storage space external interface unit 112 of master controller is by the debugging communication link unit 102 of debug command write bus 104 input microprocessor IP; The debugging communication link unit 102 of microprocessor IP is after the debug command confirming to input is the debug command for this microprocessor IP, by the debug control unit 103 of debug command input microprocessor IP, under debugging mode, complete the access for microprocessor IP internal register, storer.By Debugging message read bus 105, microprocessor IP101 internal information walks abreast and passes out to the storage space external interface unit 112 of master controller by the debugging communication link unit 102 of microprocessor IP.
In FIG, debugging mode controller 108 is responsible for entering and exit debugging mode to whole polycaryon processor and is controlled.Its cut-away view is as shown in Figure 2:
Once have microprocessor IP or master controller in execution break-poing instruction, Hardware Breakpoint or observation station hit occurring and enters debugging mode in polycaryon processor, corresponding core to enter debugging mode marking signal effective, make 1 or 2 effective.
In fig. 2, what 1 and master controller that ' debugging mode controller ' interior processing unit sends sent 2 all carries out or logical operation, like this, as long as there is a core to enter debugging mode, or door 8 exports the S1 end that useful signal enters the first two-way selector switch two-way selector switch 9.First two-way selector switch 9, second two-way selector switch 10 control end C is connected with external reset signal 119, when reset signal 119 is effective, selects S0 signal to export; Otherwise, select S1 signal to export.The input end S0 of the first two-way selector switch 9 is connected with the debugging trigger pip 118 of polycaryon processor external interface; The input end S0 of the second two-way selector switch 10 is connected with the debugging enable signal 117 of polycaryon processor external interface, and the polycaryon processor internal debugging that input end S1 and register 12 export controls enable signal 17 and is connected.Like this, when reset signal is effective, directly select the control signal of state as internal debugging pattern of external signal.
First trigger 11, second trigger 12, the 3rd trigger 15 are register, the input D end of the first trigger 11, second trigger 12 is connected with the output of the first two-way selector switch 9, first two-way selector switch 10 respectively, and trigger exports and is respectively polycaryon processor internal debugging control trigger pip 16, polycaryon processor internal debugging controls enable signal 17; The reset terminal R of the first trigger 11, second trigger 12 exits debugging mode signal 116 with polycaryon processor and is connected, like this, once polycaryon processor exits debugging mode signal 116 effectively, force output hold mode ' 0 ' of the first trigger 11, second trigger 12.Be respectively polycaryon processor internal debugging with the input of door 14 and control the output of enable signal 17 through not gate and the debugging enable signal 117 of polycaryon processor external interface; Postpone to be connected with the set end S-phase of the second trigger 12 after the clock period through the 3rd trigger 15 with the output of door 14.Such design, ensure under external debug enable signal 117 condition for validity, even if can temporarily make processor internal debugging control enable signal 17 when exiting debugging mode invalid, but after the delay of a clock, debugging control enable signal 17 can revert to effective status again, allows new debug request.
The non-detailed description of the present invention is known to the skilled person technology.
Claims (1)
1. a polycaryon processor debug system, is characterized in that: comprise microprocessor IP (101), master controller (111), debugging mode controller (108), debug command write bus (104), Debugging message read bus (105); Described microprocessor IP (101) is arranged in two-dimensional mesh grating texture, and each microprocessor IP (101) comprises microprocessor IP debugging communication link unit (102) and microprocessor IP debugging control module (103); Described master controller (111) comprises the serial debug interface (109) of master controller, the debugging communication link unit (110) of master controller, the storage space external interface unit (112) of master controller, the debug control unit (113) of master controller; The debugging communication link unit (110) of master controller realizes serial debug interface (109) reception of master controller and the mutual conversion between 8 bit data sent and 32 bit data of master controller internal bus; 32 output data lines, address wire and write signal data line that the storage space external interface unit (112) that debug command write bus (104) includes master controller sends, debug command write bus (104) is connected with the storage space external interface unit (112) of master controller, debug command write bus simultaneously (104) is also connected, for microprocessor IP debugging communication link unit (102) provides debug command with microprocessor IP debugging communication link unit (102) unit of each microprocessor IP (101) inside; Debugging message read bus (105) is the data line of 32, be connected with the input data line of the storage space external interface unit (112) of master controller, microprocessor IP debugging communication link unit (102) unit that Debugging message read bus (105) is also inner with each microprocessor IP (101) is simultaneously connected, and the Debugging message of each microprocessor IP (101) is outputted to the storage space external interface unit (112) of master controller; Microprocessor IP debugging communication link unit (102) in each microprocessor IP (101) judges that whether the address information exported in debug command write bus (104) is for this microprocessor IP (101), when judged result is for being, receive the data message in debug command write bus (104), Parallel debugging information read bus (105) sends debugging reply data; The storage space external interface unit (112) of master controller is also connected with debugging mode controller (108), for generation of the debug reset signal (116) exiting debugging mode; The debug control unit (113) of the microprocessor IP debugging control module (103) that each microprocessor IP (101) is inner and master controller is all connected to debugging mode controller (108), for the debug request of each microprocessor IP (101) and master controller (111) is fed back to debugging mode controller (108), the debugging answer signal (107) simultaneously also for being sent by debugging mode controller (108) is sent to each microprocessor IP (101) and master controller (111); The output data line (114) of master controller serial line interface, the input data line (115) of master controller serial line interface are realized and outside data information transfer by the serial debug interface (109) of master controller; External interface debugging enable signal (117) and external interface debugging trigger pip (118) all deliver to debugging mode controller (108), enter debugging mode for judging and triggering polycaryon processor;
Described debugging mode controller (108) comprises or door, with door (14), not gate, the first two-way selector switch (9), the second two-way selector switch (10), the first trigger (11), the second trigger (12), the 3rd trigger (15); By every two microprocessor IP debugging control modules (103) to debugging mode controller (108) send enter debugging mode marking signal (1) deliver to one or, above-mentioned all or door is exported and delivers to another or door more simultaneously; The result that above-mentioned another or door export again with by master controller (111) to debugging mode controller (108) send enter debugging mode marking signal (2) deliver to the 3rd or; Above-mentioned 3rd or a result exported deliver to the S1 port of the first two-way selector switch (9), and external interface debugging trigger pip (118) inputs to the S0 port of the first two-way selector switch (9) simultaneously; Debug reset signal (116) inputs to the reset terminal R of the first trigger (11) and the reset terminal R of the second trigger (12) simultaneously; The reset signal (119) of external interface inputs to the control end C of the first two-way selector switch (9) and the control end C of the second two-way selector switch (10) simultaneously; One road signal of external interface debugging enable signal (117) delivers to the S0 port of the second two-way selector switch (10); Polycaryon processor internal clock signal (7) inputs to the CLK port of the first trigger (11) and the CLK port of the second trigger (12) respectively; The D port of the first two-way selector switch (9) is connected to the D port of the first trigger (11); The D port of the second two-way selector switch (10) is connected to the D port of the second trigger (12); The S1 port of the second two-way selector switch (10) is connected to the reset terminal R of the second trigger (12); The Q port of the second trigger (12) is delivered to and door (14) through non-another road signal debugging enable signal (117) behind the door with external interface simultaneously, and the above-mentioned result exported with door (14) is delivered to the 3rd trigger (15) postpones a clock period; Result after delay exports the S port of the second trigger (12) to; The signal that the Q port of the second trigger (12) and the Q port of the first trigger (11) export is sent to each microprocessor IP (101) and master controller (111) as debugging answer signal (107).
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| CN108415842B (en) * | 2018-03-21 | 2021-01-29 | 杭州中天微系统有限公司 | Multi-core processor |
| CN108768667B (en) * | 2018-04-24 | 2020-08-07 | 中船重工（武汉）凌久电子有限责任公司 | Method for inter-chip network communication of multi-core processor |
| CN109344018B (en) * | 2018-09-10 | 2022-03-29 | 深圳忆联信息系统有限公司 | Multi-core CPU test method and device, computer equipment and storage medium |
| CN114185764A (en) * | 2020-09-14 | 2022-03-15 | 北京希姆计算科技有限公司 | Chip debugging method, chip and chip debugging system |
| CN113608788A (en) * | 2021-07-13 | 2021-11-05 | 芯来智融半导体科技(上海)有限公司 | Multi-core processor debugging method, processor, electronic device and storage medium |
| CN115357515B (en) * | 2022-10-19 | 2023-01-31 | 北京紫光芯能科技有限公司 | Debugging method and device of multi-core system, computer equipment and storage medium |
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