CN105760268B

CN105760268B - A kind of on piece random access memory build-in self-test method and device

Info

Publication number: CN105760268B
Application number: CN201610099762.0A
Authority: CN
Inventors: 王震; 张祥杉
Original assignee: Datang Microelectronics Technology Co Ltd; Datang Semiconductor Design Co Ltd
Current assignee: Datang Microelectronics Technology Co Ltd; Datang Semiconductor Design Co Ltd
Priority date: 2016-02-23
Filing date: 2016-02-23
Publication date: 2018-10-09
Anticipated expiration: 2036-02-23
Also published as: CN105760268A

Abstract

A kind of on piece RAM BIST approaches of offer of the embodiment of the present invention and device, wherein method include：Pre-set write-in functions pattern Pattern and test function Pattern；When RAM BIST modules receive write-in functions Pattern, RAM BIST modules enter program state by RAM write itself is switched to, and RAM is written into the instruction in write-in functions Pattern, value address of cache is read instruction by CPU to corresponding RAM, and according to the value address；When RAM BIST modules receive test function Pattern, March LR algorithms are based on, executes instruction and is tested in RAM since the test initial address, and output test result.The embodiment of the present invention can improve test chip quantity, save detection time, reduce checking procedure, to reduce chip testing cost and improve testing efficiency.

Description

A kind of on piece random access memory build-in self-test method and device

Technical field

The present embodiments relate to technical field of measurement and test more particularly to a kind of on piece arbitrary access for supporting that data are written to deposit Reservoir build-in self-test method and device.

Background technology

RAM (Random-Access Memory, random access memory) is because of low-power consumption, the advantages that silicon-area overhead is small And it is widely used in IC products.As IC products, such as on piece RAM capacity are increasing, quantity is got over Come more, the failure of RAM is unavoidably will appear during manufacturing, the chip with failed storage unit will cause to produce The unpredictable mistake of grade causes to correct cost abruptly increase.Therefore in the Wafer stages, to RAM carry out high coverage rate test and Screening becomes a very important ring in chip Life cycle, and how to be tested by Wafer and quickly position defective unit, carries High detection coverage rate, and then the testing time is reduced, testing efficiency is improved, is to need to analyse in depth at the beginning of chip designs and solve The problem of.

Traditional on piece ram test is usually carried out by external test facility, such as in the test on piece RAM, packet DC characteristic test, AC characteristic test, functional test, reliability test etc. are included, it is usually used to the test of storage failure March algorithms, the March algorithms it is all to cover can to write the resolution chart of certain forms according to the structure of memory Storage unit detects the function of these storage units.However, being directed to different tested RAM, it usually needs the different testing times There is different IPs logical combination on a single die in test system, such as a system on chip, if desired tests all cores Index then needs corresponding all test systems to execute test.Since system on chip scale and integrated level constantly expand, circuit knot Structure is often more complicated, and traditional test method is obviously difficult to meet demand.

BIST (Build-In-Self-Test, built-in self-test) is to be implanted into related functional circuits in circuit in design Technology for providing selftest function reduces degree of dependence of the device detection to automatic test equipment with this.Therefore, RAM BIST is increasingly becoming the main means of on piece ram test.The common detection algorithm of RAM BIST circuits of the prior art is March LR algorithms.The March LR algorithms have the characteristics that detection speed is very fast, the failure in detection single unit and coupling Also it can reach certain coverage rate in failure.However, existing on piece RAM BIST detection circuits, are functionally only detected RAM physical fault defects, and underaction with efficiently.

Invention content

An embodiment of the present invention provides a kind of on piece random access memory built-in self-test (RAM BIST) method and dresses It sets, test chip quantity can be improved, detection time is saved, reduce checking procedure, to reduce chip testing cost and raising Testing efficiency.

An embodiment of the present invention provides a kind of on piece RAM BIST approaches, including：Pre-set write-in functions pattern Pattern and test function Pattern, said write function Pattern include instruction and end mark, the test function Pattern includes instruction, test initial address and end mark；When RAM BIST modules receive write-in functions Pattern, RAM BIST modules itself will be switched to RAM write and enter program state, and RAM is written in the instruction in write-in functions Pattern, Value address of cache is read instruction by CPU to corresponding RAM, and according to the value address；When RAM BIST modules receive When test function Pattern, March LR algorithms are based on, executes instruction and is surveyed in RAM since the test initial address Examination, and output test result.

Further, the instruction in said write function Pattern is 8bits command words, and end mark is the low electricity of 1bit It is flat；The method further includes：Said write function Pattern sends out data, RAM BIST in test clock BIST_clk failing edges Module decodes write-in functions Pattern hardware, executes instruction function in test clock rising edge sampled data.

Further, the instruction in the test function Pattern is 8bits command words, and test initial address is 20bits command words, end mark are 1bit low levels；The test function Pattern is in test clock BIST_clk failing edges Data are sent out, RAM BIST modules decode test function Pattern hardware in test clock rising edge sampled data, execute work( Energy.

Further, described when RAM BIST modules receive write-in functions Pattern, RAM BIST modules by itself It is switched to RAM write and enters program state, and RAM is written into the instruction in write-in functions Pattern, CPU arrives value address of cache Corresponding RAM, and read and instructed according to the value address, specially：When RAM BIST modules by I/O interfaces to writing When entering function Pattern, RAM BIST modules enter program state by RAM write itself is switched to, to write-in functions Pattern hardware Decoding, after decoding is correct, RAM selections are enabled, and RAM write request signal is effective, and RAM BIST modules will refer to since value address It enables from DIN and RAM is written；After the completion of RAM is written, CPU selects value address of cache to corresponding RAM, system reset, RAM Enabled, RAM write request signal is effective, and CPU reads from DOUT and instructs since value address.

Further, described when RAM BIST modules receive test function Pattern, March LR algorithms are based on, It executes instruction and is tested in RAM since the test initial address, and output test result specially：When RAM BIST moulds When block receives test function Pattern, instruction, test initial address and the end mark in test function Pattern are obtained, RAM selections are enabled, are based on March LR algorithms, execute instruction and tested in RAM since testing initial address；If surveying Mistake is not detected during examination, after the completion of waiting for test, exports correct test result, the correct test result includes correct Mark；If detecting mistake during the test, after the completion of waiting for test, output error test result, the error checking As a result include error identification and wrong address.

Further, the method further includes：Concurrent testing is carried out for the RAM of on piece different data width, capacity.

The embodiment of the present invention additionally provides a kind of on piece RAM BIST devices, and RAM BIST modules pass through defeated in described device Enter/output interface receives information, and with RAM connection communications, RAM is by system bus and CPU interactive information, and there are Rom for instruction And Flash, CPU by system bus from Rom and Flash fetchings, decoding and execution；Described device pre-sets write-in functions mould Formula Pattern and test function Pattern, said write function Pattern include instruction and end mark, the test function Pattern includes instruction, test initial address and end mark；When RAM BIST modules receive write-in functions Pattern, RAM BIST modules itself will be switched to RAM write and enter program state, and RAM is written in the instruction in write-in functions Pattern, Value address of cache is read instruction by CPU to corresponding RAM, and according to the value address；When RAM BIST modules receive When test function Pattern, March LR algorithms are based on, executes instruction and is surveyed in RAM since the test initial address Examination, and output test result.

Further, the instruction in said write function Pattern is 8bits command words, and end mark is the low electricity of 1bit It is flat；Instruction in the test function Pattern is 8bits command words, and test initial address is 20bits command words, terminates mark Will is 1bit low levels.

Further, the RAM_BIST module interfaces signal is divided into input signal and output signal, wherein：The input Signal, including clk are clock signal, and rst_n is low reset signal, and en is work enable signal, and all_en is that full sheet is surveyed parallel Trial work enables, and addr_max is the maximum address value for testing RAM；The output signal, including BIST_rd_data read for RAM Go out data, BIST_cen is that RAM selections are enabled, and BIST_addr is address ram, and BIST_we is RAM write request signal, BIST_ Oe is that RAM exports enable signal, and BIST_wr_data is that RAM write enters data, and IO_out is correct/error mark and wrong address Export IO.

Further, the RAM BIST modules carry out concurrent testing for the RAM of on piece different data width, capacity.

On piece RAM build-in self-test methods and device provided in an embodiment of the present invention are based on March LR algorithms, support RAM write enters instruction and executes function, at the same increase output fault address, initial address can match, full sheet parallel test function Scheme can improve test chip quantity, save detection time, reduces checking procedure, reduce chip testing cost to reach With the purpose for improving testing efficiency.

Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification It obtains it is clear that understand through the implementation of the invention.The purpose of the present invention and other advantages can be by specification, rights Specifically noted structure is realized and is obtained in claim and attached drawing.

Description of the drawings

Attached drawing is used for providing further understanding technical solution of the present invention, and a part for constitution instruction, with this The embodiment of application technical solution for explaining the present invention together, does not constitute the limitation to technical solution of the present invention.

Fig. 1 is on piece RAM BIST circuit structural schematic diagrams in the embodiment of the present invention；

Fig. 2 is RAM_BIST module interface signal schematic representations in the embodiment of the present invention；

Fig. 3 is the flow diagram of on piece RAM BIST approaches in the embodiment of the present invention；

Fig. 4 is the simulation waveform schematic diagram of write-in functions Pattern decoding functions in the embodiment of the present invention；

Fig. 5 is the simulation waveform signal of the instruction write-in RAM functions in write-in functions Pattern in the embodiment of the present invention Figure；

Fig. 6 is the simulation waveform schematic diagram of single ram test initial address configuration and startup in the embodiment of the present invention；

Fig. 7 is the simulation waveform schematic diagram that address error data are detected in the embodiment of the present invention；

Fig. 8 is output error mark and the simulation waveform schematic diagram of wrong address after being detected in the embodiment of the present invention；

Fig. 9 is the simulation waveform schematic diagram that correct output identification is detected in the embodiment of the present invention.

Specific implementation mode

To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention Embodiment be described in detail.It should be noted that in the absence of conflict, in the embodiment and embodiment in the application Feature mutually can arbitrarily combine.

Step shown in the flowchart of the accompanying drawings can be in the computer system of such as a group of computer-executable instructions It executes.Also, although logical order is shown in flow charts, and it in some cases, can be with suitable different from herein Sequence executes shown or described step.

Fig. 1 is on piece RAM BIST circuit structural schematic diagrams in the embodiment of the present invention, as shown in Figure 1, RAM BIST modules By I/O (input/output) interface information, and with RAM connection communications, RAM passes through system bus and CPU interactive information； There are Rom and Flash, CPU, from Rom and Flash fetchings, decoding, execution, to configure each module by system bus for instruction, completes Using.

Fig. 2 is RAM_BIST module interface signal schematic representations in the embodiment of the present invention, and wherein clk is clock signal, rst_n For low reset signal, en is work enable signal, and all_en is that the work of full sheet concurrent testing is enabled, and addr_max is test RAM Maximum address value.BIST_rd_data reads data for RAM, and BIST_cen is that RAM selections are enabled (low effective), BIST_ Addr is address ram, and BIST_we is RAM write request signal, and BIST_oe is that RAM exports enable signal, and BIST_wr_data is RAM write enters data, and IO_out is that correct/error mark and wrong address export IO.

Due in Rom and Flash itself design reasons, technological reason, or encapsulation and handling process may caused by chip Rom and Flash program area damage, cause chip that can not execute instruction after the power is turned on, can not test each functions of modules.Rom and Although Flash is damaged, CPU and other modules may be intact, and in the prior art, such chip generally can only also be given up, from And reduce testable number of chips.However, if attempting new process or MPW (Multi Project Wafer) stages, Number of chips to be measured is limited, then the chip of each encapsulation is valuable and can be made full use of.

Compared with the existing technology, function is executed instruction invention increases write-in instruction ram data function and in RAM, Specifically, instruction repertorie is written by RAM by exterior I/O and in RAM, the command function of write-in is executed, so as to test Functions of modules improves test chip quantity, reduces testing cost.

In addition, existing RAM BIST test circuits design underaction with efficiently.It is mainly reflected in：Existing design only exports Test result mark does not export specific wrong address, therefore can not understand memory entirety bad block position, is unfavorable for and chip Manufacturer is linked up, analysis memory bad block proportion is changed and distribution situation；Prior art incremental variations since address " 0 " Detection, initial detecting address cannot configure.After finding mistake such as in previous test and quoting wrong address, need from this place Location starts the case where continuing to understand ram cell below, then cannot achieve；Existing design for configure different capabilities RAM chip, It generally requires different test models to test respectively, increases the testing time, improve testing cost.

In view of the above problems, the present invention provides one kind being based on March LR algorithms, RAM write is supported to enter instruction and execute work( Can, at the same increase output fault address, initial address can match, the scheme of full sheet parallel test function, reach raising test core Piece quantity, the purpose for saving detection time, reducing checking procedure, reduce chip testing cost, improving testing efficiency.

Fig. 3 is the flow diagram of on piece RAM BIST approaches in the embodiment of the present invention.As shown in figure 3, including：

Step 301, write-in functions Pattern (pattern) is pre-set, said write function Pattern includes instruction and knot Bundle flag；When RAM BIST modules receive write-in functions Pattern, RAM BIST modules enter RAM write itself is switched to Program state, and RAM is written into the instruction in write-in functions Pattern, CPU is by value address of cache to corresponding RAM, and root It reads and instructs according to value address.

In this step, write-in functions Pattern structures are pre-set, write-in functions Pattern structures include instruction And end mark, in a specific embodiment of the present invention, as shown in table 1 below, write-in functions Pattern structures can be by The instruction of 8bits command words and the low level end mark compositions of 1bit.

Table 1

When RAM BIST modules by I/O interfaces to write-in functions Pattern when, RAM BIST modules cut itself It is changed to RAM write and enters program state, and RAM is written into the instruction in write-in functions Pattern.

Write-in functions Pattern sends out data in test clock BIST_clk failing edges, and RAM BIST modules are in test clock Rising edge sampled data decodes write-in functions Pattern hardware, executes instruction function.

Such as in one embodiment, simulation waveform is as shown in figure 4, the command word of write-in functions Pattern is 0x03H is followed by 1bit low levels as end mark, after decoding is correct, starts to execute write-in functions Pattern, wr_RAM_ Cos_FLAG hardware sets.At this point, RAM selects CEN to drag down, to be high, with effect, since address 0, write-in work(is written from DIN in WE Energy Pattern, as shown in figure 5,36 ' h8_0402_0100 are written in continuation address.

After the completion of RAM is written in the instruction in write-in functions Pattern, CPU is by value address of cache to corresponding RAM, system reset, CPU reads instruction since value address, so as to subsequent execution instruction repertorie, test system and does not damage Other modules.

Such as in one embodiment, the command word for write-in functions Pattern being executed from RAM is 0x06H, and decoding is correct Later, RAM_cos_en hardware set, fetching address of cache so far RAM.System reset sys_rstn sets, RAM pieces select CEN It drags down, WE is that high reading is effective, since address 0, reads instruction repertorie from DOUT, continuation address reads 36 ' h8_0402_0100.

Step 302, it includes instruction, test starting to pre-set test function Pattern, the test function Pattern Address and end mark；When RAM BIST modules receive test function Pattern, March LR algorithms are based on, from test Initial address, which starts to execute instruction in RAM, is tested, and is outputed test result.

In this step, pre-set test function Pattern structures, test function Pattern structures include instruction, Initial address and end mark are tested, in a specific embodiment of the present invention, as shown in table 2 below, test function Pattern knots Structure can be by the instruction of 8bits command words, the test initial address of 20bits command words and the low level end mark groups of 1bit At.

Table 2

Test function Pattern sends out data in test clock BIST_clk failing edges, and RAM BIST modules are in test clock Rising edge sampled data decodes test function Pattern hardware, executes instruction function.

When RAM BIST modules receive test function Pattern, obtains the instruction in test function Pattern, surveys Try initial address and end mark.It opens and enables, RAM BIST circuits are started to work, and specifically, are based on March LR algorithms, from Test initial address, which starts to execute instruction in RAM, is tested.

If mistake is not detected during the test, after the completion of waiting for test, correct test result is exported, the correct survey Test result includes accurate indication, as shown in table 3, such as output accurate indication " 0x9009H ".

Table 3

0x9009H

If detecting mistake during the test, after the completion of waiting for test, output error test result, the error checking As a result including error identification and wrong address, as shown in table 4, such as output error mark " 0x5555H " and first appearance mistake Address accidentally.

Table 4

0x5555H

20bits mistakes address

Such as in one embodiment, simulation waveform is followed by as shown in fig. 6, the Pattern of single ram test is 0x33H Lbit low levels, followed by initial address (Start_addr)=0x3H, after decoding is correct, RAM_BIST_flag hardware is set " 1 ", RAM BIST modules detect work since address " 3 ".

As shown in fig. 7, RAM BIST modules, in detection process, it is " 0xaH " that error in data is read and write in " 28 " address；Such as Fig. 8 It is shown, output error mark " 0x5555H " after detection, and output error address is " 0x28H "；

As shown in figure 9, mistake is not detected in AM BIST modules in detection process, after the completion of waiting for test, then export just Really mark " 0x9009H ".

It is worth noting that all RAM concurrent testings on supporting pieces of the present invention, hence for different data width, capacity RAM, can simplify testing procedure, reduce detection time, reduce testing cost, improve testing efficiency.

, can be referring to shown in Fig. 1 the present invention also provides a kind of on piece RAM BIST devices, RAM BIST moulds in described device Block by input/output interface receive information, and with RAM connection communications, RAM pass through system bus and CPU interactive information, instruction There are Rom and Flash, CPU is by system bus from Rom and Flash fetchings, decoding and execution；Described device, which is pre-set, to be write Enter functional mode Pattern and test function Pattern, said write function Pattern includes instruction and end mark, described Test function Pattern includes instruction, test initial address and end mark；

When RAM BIST modules receive write-in functions Pattern, RAM BIST modules enter RAM write itself is switched to Program state, and RAM is written into the instruction in write-in functions Pattern, CPU is by value address of cache to corresponding RAM, and root It reads and instructs according to the value address；

When RAM BIST modules receive test function Pattern, March LR algorithms are based on, are originated from the test Address, which starts to execute instruction in RAM, to be tested, and is outputed test result.

Particular technique details in a kind of on piece RAM BIST devices provided by the present invention and a kind of on piece RAM BIST Corresponding technical detail is similar in method, therefore this will not be repeated here.

In the present invention, on piece RAM BIST realize support instruction write-in RAM and operating instruction function, support initially Location can match, mistake address exports, full sheet parallel detection function；In addition, supporting instruction write-in RAM, simultaneously operating instruction, full sheet are parallel Detection realizes efficient, high fault coverage RAM Bist detection schemes.

The apparatus embodiments described above are merely exemplary, wherein the unit illustrated as separating component can It is physically separated with being or may not be, the component shown as unit may or may not be physics list Member, you can be located at a place, or may be distributed over multiple network units.It can be selected according to the actual needs In some or all of module achieve the purpose of the solution of this embodiment.Those of ordinary skill in the art are not paying creativeness Labour in the case of, you can to understand and implement.

Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can It is realized by the mode of software plus required general hardware platform, naturally it is also possible to pass through hardware.Based on this understanding, on Stating technical solution, substantially the part that contributes to existing technology can be expressed in the form of software products in other words, should Computer software product can store in a computer-readable storage medium, such as ROM/RAM, magnetic disc, CD, including several fingers It enables and using so that a computer equipment (can be personal computer, server or the network equipment etc.) executes each implementation Method described in certain parts of example or embodiment.

Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although Present invention has been described in detail with reference to the aforementioned embodiments, it will be understood by those of ordinary skill in the art that：It still may be used With technical scheme described in the above embodiments is modified or equivalent replacement of some of the technical features； And these modifications or replacements, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and Range.

Claims

1. a kind of on piece random access memory ram built-in self-test BIST approach, which is characterized in that including：

Write-in functions pattern and test function pattern are pre-set, said write functional mode includes instruction and end mark, institute It includes instruction, test initial address and end mark to state test function pattern；Said write functional mode is in Rom and Flash When damage, specified by input/output interface；Rom the and Flash middle fingers of instruction and damage in said write functional mode The function of order is identical；

When RAM BIST modules receive write-in functions pattern, RAM BIST modules enter program shape by RAM write itself is switched to State, and RAM is written into the instruction in write-in functions pattern, CPU takes value address of cache to corresponding RAM, and according to described It is worth address and reads instruction；

The test initial address is that 20bits command words are based on when RAM BIST modules receive test function pattern March LR algorithms configure the test initial address by the way that the 20bits command words are arranged, with from the test Initial address, which starts to execute instruction in RAM, is tested, and is outputed test result.

2. according to the method described in claim 1, it is characterized in that, the instruction in said write functional mode is 8bits orders Word, end mark are 1bit low levels；

The method further includes：Said write functional mode sends out data in test clock failing edge, and RAM BIST modules are described Test clock rising edge sampled data decodes write-in functions mode hardware, executes instruction function.

3. according to the method described in claim 1, it is characterized in that, the instruction in the test function pattern is 8bits orders Word, end mark are 1bit low levels；

The test function pattern sends out data in test clock failing edge, and RAM BIST modules are adopted in the test clock rising edge Sample data decode test function mode hardware, execute instruction function.

4. according to the method described in claim 1, it is characterized in that, described when RAM BIST modules receive write-in functions pattern When, RAM BIST modules itself will be switched to RAM write and enter program state, and RAM is written in the instruction in write-in functions pattern, Value address of cache is read instruction by CPU to corresponding RAM, and according to the value address, specially：

When RAM BIST modules by I/O interfaces to write-in functions pattern when, itself is switched to RAM by RAM BIST modules Write-in program state decodes write-in functions mode hardware, and after decoding is correct, RAM selections are enabled, and RAM write request signal is effective, RAM is written from DIN since value address, by instruction in RAM BIST modules；

After the completion of RAM is written, CPU is by value address of cache to corresponding RAM, and system reset, RAM selections are enabled, and RAM write is asked Ask signal effective, CPU reads from DOUT and instructs since value address.

5. according to the method described in claim 4, it is characterized in that, described when RAM BIST modules receive test function pattern When, March LR algorithms are based on, the test initial address is configured by the way that the 20bits command words are arranged, with from institute It states test initial address to start to execute instruction in RAM and tested, and outputs test result specially：

When RAM BIST modules receive test function pattern, obtains the instruction in test function pattern, tests initial address And end mark, RAM selections are enabled, are based on March LR algorithms, execute instruction and surveyed in RAM since testing initial address Examination；

If mistake is not detected during the test, after the completion of waiting for test, correct test result, the correct test are exported As a result include accurate indication；

If detecting mistake during the test, after the completion of waiting for test, output error test result, the error checking knot Fruit includes error flag and wrong address.

6. method according to any one of claims 1 to 5, which is characterized in that the method further includes：Not on piece The RAM progress concurrent testings of same data width, capacity.

7. a kind of on piece random access memory ram built-in self-test BIST device, which is characterized in that RAM in described device BIST module by input/output interface receive information, and with RAM connection communications, RAM pass through system bus and CPU interaction letter Breath, instruction is there are Rom and Flash, and CPU is by system bus from Rom and Flash fetchings, decoding and execution；

Described device pre-sets write-in functions pattern and test function pattern, and said write functional mode includes instruction and terminates Mark, the test function pattern include instruction, test initial address and end mark；Said write functional mode is in Rom When being damaged with Flash, specified by input/output interface；In said write functional mode instruction with damage Rom and The function of being instructed in Flash is identical；

8. device according to claim 7, which is characterized in that the instruction in said write functional mode is 8bits orders Word, end mark are 1bit low levels；

Instruction in the test function pattern is 8bits command words, and end mark is 1bit low levels.

9. device according to claim 7, which is characterized in that the RAM BIST module interface signals are divided into input letter Number and output signal, wherein：

The input signal, including clk are clock signal, and rst_n is low reset signal, and en is work enable signal, all_en For full sheet concurrent testing work enable signal, addr_max is the maximum address for testing RAM；

The output signal, including BIST_rd_data are that RAM reads data, and BIST_cen is that RAM selects enable signal, BIST_addr is address ram, and BIST_we is RAM write request signal, and BIST_oe is that RAM exports enable signal, BIST_wr_ Data is that RAM write enters data, and IO_out is accurate indication output or error flag and wrong address output.

10. device according to claim 7, which is characterized in that described when RAM BIST modules receive write-in functions mould When formula, RAM BIST modules itself will be switched to RAM write and enter program state, and RAM is written in the instruction in write-in functions pattern, Value address of cache is read instruction by CPU to corresponding RAM, and according to the value address, specially：

11. device according to claim 10, which is characterized in that described when RAM BIST modules receive test function mould When formula, be based on March LR algorithms, the test initial address configured by the way that the 20bits command words are arranged, with from The test initial address, which starts to execute instruction in RAM, is tested, and is outputed test result specially：

12. the device according to any one of claim 7~11, which is characterized in that the RAM BIST modules are for piece The RAM progress concurrent testings of upper different data width, capacity.