CN110427292A - The method and device that FLASH is tested using embedded ROM - Google Patents
The method and device that FLASH is tested using embedded ROM Download PDFInfo
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- CN110427292A CN110427292A CN201910688088.3A CN201910688088A CN110427292A CN 110427292 A CN110427292 A CN 110427292A CN 201910688088 A CN201910688088 A CN 201910688088A CN 110427292 A CN110427292 A CN 110427292A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
- G06F11/2635—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers using a storage for the test inputs, e.g. test ROM, script files
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Abstract
The invention discloses the method and devices tested using embedded ROM FLASH, and wherein method includes: to start the BIST test of FLASH by initial signal；Initial address is assigned according to BIST test instruction corresponding address tunnel into FLASH；The data vector of required data type is obtained from embedded ROM；In the data vector write-in FLASH that will acquire.The present invention is avoided by the way that regular data vector is stored in embedded ROM and is inputted data from serial port by turn using SPI interface, to improve testing efficiency.
Description
Technical field
The present invention relates to FLASH tests, more specifically using embedded ROM to the FLASH method tested and dress
It sets.
Background technique
Currently, FLASH test be using SPI interface test address position, test data and test control signal by turn from
It is inputted at serial port.For example, during the test, needing to obtain 1000 times identical data for FLASH, then need to repeat from outer
1000 times identical data are read in the portion port ATE, and the serial clock frequency of SPI interface is also very low, therefore use the method
Test is carried out on the one hand to need using SPI interface test address position, test data and test control signal by turn from serial port
Place's input causes testing efficiency not high, while testing cost is also high；On the other hand, the data and control letter come in from SPI interface
Number, need the test logic of internal design comparison complexity BIST state machine come complete FLASH test, cause chip power consumption and
Area increases, to influence the design of rear end.
Summary of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide the sides tested using embedded ROM FLASH
Method and device.
To achieve the above object, the invention adopts the following technical scheme: the side tested using embedded ROM FLASH
Method, which comprises
Start the BIST test of FLASH by initial signal；
Initial address is assigned according to BIST test instruction corresponding address tunnel into FLASH；
The data vector of required data type is obtained from embedded ROM；
In the data vector write-in FLASH that will acquire.
Its further technical solution are as follows: it is described will acquire data vector write-in FLASH in step after, further include with
Lower step:
Judge whether address is write full in corresponding channel；
If so, determining that data vector write-in terminates；
If it is not, the step of then returning to the data vector for obtaining required data type from embedded ROM.
Its further technical solution are as follows: described to judge that whether address writes full step in corresponding channel, specifically includes following
Step:
Obtain the address value of current data vector address position；
Judge whether the address value of current data vector address position is equal to maximum address value in address tunnel；
If so, determining that address has been fully written in channel.
The device that FLASH is tested using embedded ROM, including start unit, initial address given unit, acquisition list
Member and writing unit；
The start unit, the BIST for starting FLASH by initial signal are tested；
The initial address given unit, for being assigned according to BIST test instruction corresponding address tunnel into FLASH
Initial address；
The acquiring unit, the data vector for data type needed for being obtained from embedded ROM；
Said write unit, the data vector for will acquire are written in FLASH.
Its further technical solution are as follows: further include judging unit and judging unit；
The judging unit, for judging whether address is write full in corresponding channel；
The judging unit, for determining that data vector write-in terminates.
Its further technical solution are as follows: the judging unit includes obtaining module, judgment module and determination module；
The acquisition module, for obtaining the address value of current data vector address position；
The judgment module, for judging whether the address value of current data vector address position is equal in address tunnel
Maximum address value；
The judgment module, for determining that address has been fully written in channel.
Compared with the prior art, the invention has the advantages that: it is provided by the invention that FLASH is surveyed using embedded ROM
The method and device of examination, by the way that regular data vector is stored in embedded ROM, avoiding will be counted using SPI interface
According to being inputted from serial port by turn, to improve testing efficiency.
The above description is only an overview of the technical scheme of the present invention, can in order to better understand technical measure
It is implemented in accordance with the contents of the specification, and in order to make above and other objects of the present invention, feature and advantage brighter
Show understandable, special below to lift preferred embodiment, detailed description are as follows.
Detailed description of the invention
Fig. 1 is the schematic diagram that the present invention is tested using FLASH in the method that embedded ROM tests FLASH；
Fig. 2 is flow chart one of the present invention using embedded ROM to the FLASH method specific embodiment tested；
Fig. 3 is flowchart 2 of the present invention using embedded ROM to the FLASH method specific embodiment tested；
Fig. 4 is structure chart one of the present invention using embedded ROM to the FLASH device specific embodiment tested；
Fig. 5 is structure chart two of the present invention using embedded ROM to the FLASH device specific embodiment tested.
Specific embodiment
In order to more fully understand technology contents of the invention, combined with specific embodiments below to technical solution of the present invention into
One step introduction and explanation, but not limited to this.
It should be appreciated that herein, relational terms such as first and second and the like are used merely to an entity/behaviour
Work/object is distinguished with another entity/operation/object, without necessarily requiring or implying these entity/operation/objects
Between there are any actual relationship or orders.
It is also understood that the terms "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion,
So that the process, method, article or the system that include a series of elements not only include those elements, but also including not having
The other element being expressly recited, or further include for this process, method, article or the intrinsic element of system.Do not having
In the case where having more limitations, the element that is limited by sentence "including a ...", it is not excluded that include the element process,
There is also other identical elements in method, article or system.
Referring to Figure 1,2, the present embodiment provides given a kind of method tested using embedded ROM FLASH, the party
Method the following steps are included:
S10, the BIST for starting FLASH by initial signal are tested；
S20, initial address is assigned according to BIST test instruction corresponding address tunnel into FLASH；
S30, the data vector that required data type is obtained from embedded ROM；
In S40, the data vector that will acquire write-in FLASH；
S50, judge in corresponding channel address whether write it is full, if so, S60, then determining that data vector write-in terminates；If it is not,
Then return step S30.
After the completion of chip manufacturing, manufacturer exports wafer, and testing vendor can be with the testing scheme being pre-designed to crystalline substance
Chip on circle is tested, and FLASH test is mainly carried out.But the data type that usually test FLASH needs has very much
Rule, common data type have following four classes: 32 ' h55555555；32'hAAAAAAAA；32'hFFFFFFFF；32'
h00000000.According to this feature, a ROM can be embedded in the design of chip in advance, these regular data class
The data vector of type is stored in advance in inside ROM, directly repeats to call in FLASH test.In this manner, biography
The data off-chip read-in process of system has become the data transmission procedure in chip, substantially increases testing efficiency.
Referring to Figure 1, for hardware view, when FLASH is tested, signal is controlled by FLASH TEST Control
Converter realize the switching of test data (Test Data) and performance data stream (Function Data).
Further, step S50 specifically includes following steps；
S501, the address value for obtaining current data vector address position；
S502, judge whether the address value of current data vector address position is equal to maximum address in address tunnel
Value, S503, if so, determine channel in address be fully written, if it is not, then return step S501.
Specifically, corresponding address tunnel size is limited in FLASH, the data vector address position before determining
Address value when whether being equal to maximum address value in address tunnel, then illustrated the address of corresponding address tunnel in FLASH
It is fully written.
It should be understood that the size of the serial number of each step is not meant that the order of the execution order in above-described embodiment, each process
Execution sequence should be determined by its function and internal logic, the implementation process without coping with the embodiment of the present invention constitutes any limit
It is fixed.
Corresponding to the method tested using embedded ROM FLASH of above-described embodiment, the present invention also provides utilizations
The device that embedded ROM tests FLASH；Refer to Fig. 3, the device include start unit 1, initial address given unit 2,
Acquiring unit 3 and writing unit 4, judging unit 5 and judging unit 6；
Start unit 1, the BIST for starting FLASH by initial signal are tested；
Initial address given unit 2, it is initial for being assigned according to BIST test instruction corresponding address tunnel into FLASH
Address；
Acquiring unit 3, the data vector for data type needed for being obtained from embedded ROM；
Writing unit 4, the data vector for will acquire are written in FLASH；
Judging unit 5, for judging whether address is write full in corresponding channel；
Judging unit 6, for determining that data vector write-in terminates.
Further, judging unit includes obtaining module 51, judgment module 52 and determination module 53；
Module 51 is obtained, for obtaining the address value of current data vector address position；
Judgment module 52, for judging whether the address value of current data vector address position is equal in address tunnel most
Big address value；
Determination module 53, for determining that address has been fully written in channel.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, the technical solution of the embodiment of the present invention
Substantially all or part of the part that contributes to existing technology or the technical solution can be with software product in other words
Form embody, which is stored in a storage medium, including some instructions use so that one
Computer equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute this hair
The all or part of the steps of each embodiment the method in bright.And storage medium above-mentioned include: USB flash disk, it is mobile hard disk, read-only
Memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or
The various media that can store program code such as person's CD.
It is apparent to those skilled in the art that for convenience of description and succinctly, only with above-mentioned each function
Can unit division progress for example, in practical application, can according to need and by above-mentioned function distribution by different functions
Unit is completed, i.e., the internal structure of described device is divided into different functional units, with complete it is described above whole or
Partial function.Each functional unit in embodiment can integrate in one processing unit, be also possible to the independent object of each unit
Reason exists, and can also be integrated in one unit with two or more units, above-mentioned integrated unit can both use hardware
Form realize, can also realize in the form of software functional units.In addition, the specific name of each functional unit is also only
Convenient for mutually distinguishing, the protection scope that is not intended to limit this application.The specific work process of unit in above-mentioned apparatus, can be with
With reference to the corresponding process in preceding method embodiment, details are not described herein.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
In embodiment provided by the present invention, it should be understood that disclosed device and method can pass through others
Mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the unit, only
A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple units or components can combine or
Person is desirably integrated into another device, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Between coupling or direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or communication of device or unit connect
It connects, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
It is above-mentioned that technology contents of the invention are only further illustrated with embodiment, in order to which reader is easier to understand, but not
It represents embodiments of the present invention and is only limitted to this, any technology done according to the present invention extends or recreation, by of the invention
Protection.Protection scope of the present invention is subject to claims.
Claims (6)
1. the method tested using embedded ROM FLASH, which is characterized in that the described method includes:
Start the BIST test of FLASH by initial signal；
Initial address is assigned according to BIST test instruction corresponding address tunnel into FLASH；
The data vector of required data type is obtained from embedded ROM；
In the data vector write-in FLASH that will acquire.
2. the method according to claim 1 tested using embedded ROM FLASH, which is characterized in that described to obtain
It is further comprising the steps of after the step in data vector write-in FLASH taken:
Judge whether address is write full in corresponding channel；
If so, determining that data vector write-in terminates；
If it is not, the step of then returning to the data vector for obtaining required data type from embedded ROM.
3. the method according to claim 2 tested using embedded ROM FLASH, which is characterized in that the judgement
Whether address writes full step in corresponding channel, specifically includes the following steps:
Obtain the address value of current data vector address position；
Judge whether the address value of current data vector address position is equal to maximum address value in address tunnel；
If so, determining that address has been fully written in channel.
4. the device tested using embedded ROM FLASH, which is characterized in that assigned including start unit, initial address single
Member, acquiring unit and writing unit；
The start unit, the BIST for starting FLASH by initial signal are tested；
The initial address given unit, it is initial for being assigned according to BIST test instruction corresponding address tunnel into FLASH
Address；
The acquiring unit, the data vector for data type needed for being obtained from embedded ROM；
Said write unit, the data vector for will acquire are written in FLASH.
5. the device according to claim 4 tested using embedded ROM FLASH, which is characterized in that further include sentencing
Disconnected unit and judging unit；
The judging unit, for judging whether address is write full in corresponding channel；
The judging unit, for determining that data vector write-in terminates.
6. the device according to claim 5 tested using embedded ROM FLASH, which is characterized in that the judgement
Unit includes obtaining module, judgment module and determination module；
The acquisition module, for obtaining the address value of current data vector address position；
The judgment module, for judging it is maximum whether the address value of current data vector address position is equal in address tunnel
Address value；
The judgment module, for determining that address has been fully written in channel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910688088.3A CN110427292A (en) | 2019-07-29 | 2019-07-29 | The method and device that FLASH is tested using embedded ROM |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910688088.3A CN110427292A (en) | 2019-07-29 | 2019-07-29 | The method and device that FLASH is tested using embedded ROM |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040230870A1 (en) * | 2003-05-12 | 2004-11-18 | Li Wang | Built-in self test system and method |
| JP2006085769A (en) * | 2004-09-14 | 2006-03-30 | Toshiba Corp | Semiconductor device and its self test method |
| CN105760268A (en) * | 2016-02-23 | 2016-07-13 | 大唐微电子技术有限公司 | On-chip random access memory built-in self-testing method and device |
| CN107301880A (en) * | 2017-06-15 | 2017-10-27 | 西安微电子技术研究所 | A kind of BIST Structure of piece upper embedded Flash |
-
2019
- 2019-07-29 CN CN201910688088.3A patent/CN110427292A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040230870A1 (en) * | 2003-05-12 | 2004-11-18 | Li Wang | Built-in self test system and method |
| JP2006085769A (en) * | 2004-09-14 | 2006-03-30 | Toshiba Corp | Semiconductor device and its self test method |
| CN105760268A (en) * | 2016-02-23 | 2016-07-13 | 大唐微电子技术有限公司 | On-chip random access memory built-in self-testing method and device |
| CN107301880A (en) * | 2017-06-15 | 2017-10-27 | 西安微电子技术研究所 | A kind of BIST Structure of piece upper embedded Flash |
Non-Patent Citations (3)
| Title |
|---|
| 宋毅等: "嵌入式存储器内建自测试方法", 《微计算机信息》 * |
| 鉴海防等: "SOC嵌入式flash存储器的内建自测试设计", 《微电子学与计算机》 * |
| 陆思安等: "嵌入式存储器内建自测试的原理及实现", 《固体电子学研究与进展》 * |
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Application publication date: 20191108 |