CN103137211B - A kind of emulation test system of NVM build-in self-test - Google Patents
A kind of emulation test system of NVM build-in self-test Download PDFInfo
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- CN103137211B CN103137211B CN201110388391.5A CN201110388391A CN103137211B CN 103137211 B CN103137211 B CN 103137211B CN 201110388391 A CN201110388391 A CN 201110388391A CN 103137211 B CN103137211 B CN 103137211B
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Abstract
The invention discloses a kind of emulation test system of NVM build-in self-test, include Test Host; Multiple analog module, NVM chip circuit, NVM build-in self-test, automatic detection module.Described automatic detection module specifically comprises interface signal detection module, system state detection module, instruction execution time-series rules module, test completeness detection module, data outputting module and test vector output module.By emulation test system of the present invention, the workload that NVM build-in self-test is detected can be greatly reduced, and ensure that the integrality of test.
Description
Technical field
The present invention relates to the emulation test system of a kind of NVM (Non-VolatileMemory, nonvolatile memory).
Background technology
Built-in self-test (Built-inSelfTest is called for short BIST) technology is in circuit design, implant the circuit providing self detecting function function, reduces the degree of dependence of device detection to ATE (automatic test equipment) (ATE) with this.BIST technology can be applied to nearly all circuit, is therefore widely used in semi-conductor industry.
Such as, the BIST technology generally used in NVM is included in NVM circuit implants resolution chart circuit for generating, sequential circuit, mode selection circuit and debugging test circuit etc., and they are collectively referred to as BIST circuit.
Refer to Fig. 1, this is the emulation test system of the BIST circuit of a kind of existing NVM.This system includes Test Host 1; Multiple analog module 21,22,23, NVM chip circuit 31; The BIST circuit 32 of NVM.
The process that the BIST circuit 32 of this system to NVM is tested is as follows.Test Host 1 sends test instruction by interface bus STROBE, TDIO, TCK to the BIST circuit 32 of NVM.Described test instruction comprises test pattern (TESTMODE) etc.The BIST circuit 32 of NVM performs the instruction received, to NVM chip circuit 31 and each analog module 21,22,23 ... operate.The BIST circuit 32 of NVM receive again NVM chip circuit 31 and each analog module 21,22,23 ... the simulation waveform generated carries out the checking emulating correctness.
The emulation test system of the BIST circuit of above-mentioned NVM has following shortcoming.First wave test efficiency is low.It two is that workload is large.It three is debug difficulties.It four is to provide silicon test board test vector.It five is the integralities that automatically can not detect test vector.
Summary of the invention
Technical matters to be solved by this invention is to provide the emulation test system that a kind of BIST circuit to NVM carries out automatically detecting, and this system can realize test instruction detection, instruction performs time-series rules, data correctness detects and information output function.
For solving the problems of the technologies described above, the emulation test system of the BIST circuit of a kind of NVM of the present invention includes Test Host; Multiple analog module, NVM chip circuit, the BIST circuit of NVM, automatic detection module;
Described NVM build-in self-test is connected with Test Host, each analog module, NVM chip circuit;
Described automatic detection module is connected with Test Host, each analog module, NVM chip circuit, NVM build-in self-test;
Described automatic detection module specifically comprises:
The accuracy that the interface signal of NVM build-in self-test is connected and NVM build-in self-test receive instruction the interface signal detection module that detects of accuracy;
To the system state detection module that the signal under system state and each state detects;
To NVM build-in self-test receive the sequential of instruction and time-series rules module performed to the instruction that the sequential of the interface signal of each analog module and NVM build-in self-test detects;
Test vector is added up and the test completeness detection module that the integrality of test vector is detected;
The data outputting module that output order information, instruction perform time sequence information, instruction performs data message, error message, error reason; And
To NVM build-in self-test receive instruction and export as the test vector output module of test vector.
Present invention achieves the automatic detection of the BIST circuit to NVM, data output and test vector defeated, tool has the following advantages:
One, achieves the state-detection of system, automatically completes the input under each state.
Its two, achieve interface signal and the command detection of BIST circuit, and each instruction performs sequential and Data Detection.
Its three, what achieve Detection Information classifies output in detail.
Its four, provide the output of test vector, can directly for silicon test board.
Its five, complete the detection testing and become second nature, ensure the integrality of test vector.
Therefore, by emulation test system of the present invention, the workload that the BIST circuit of NVM is detected can be greatly reduced, and ensure that the integrality of test.
Accompanying drawing explanation
Fig. 1 is the structural representation of the emulation test system of the BIST circuit of a kind of existing NVM;
Fig. 2 is the structural representation of the emulation test system of the BIST circuit of NVM of the present invention.
Description of reference numerals in figure:
1 is Test Host; 21,22,23 ... for each analog module; 31 is NVN chip circuit; 32 is the BIST circuit of NVM; 4 is automatic detection module; 41 is interface signal detection module; 42 is system state detection module; 43 is instruction execution time-series rules module; 44 is test completeness detection module; 45 is data outputting module; 46 is test vector output module.
Embodiment
Refer to Fig. 2, this is the emulation test system of the BIST circuit of a kind of NVM of the present invention.This system includes Test Host 1; Multiple analog module 21,22,23, NVM chip circuit 31; The BIST circuit 32 of NVM; Automatic detection module 4.
The BIST circuit 32 of described NVM and Test Host 1, each analog module 21,22,23 ..., NVM chip circuit 31 is connected.Test Host 1, multiple analog module 21,22,23 ... the normal operation circumstances of the BIST circuit 32 of NVM is formed with NVM chip circuit 31.
Described automatic detection module 4 and Test Host 1, each analog module 21,22,23 ..., NVM chip circuit 31, NVM BIST circuit 32 be connected.This automatic detection module 4 detects connected each module, realizes Data Detection and time-series rules, and can carry out analyzing and positioning to relevant issues.
Described automatic detection module 4 specifically comprises:
---the accuracy that the interface signal of the BIST circuit 32 of NVM is connected and the BIST circuit of NVM receive instruction the interface signal detection module 41 that detects of accuracy;
---to the system state detection module 42 that the signal under system state and each state detects;
---to the BIST circuit 32 of NVM receive instruction sequential and to each analog module 21,22,23 ... time-series rules module 43 is performed with the instruction that the sequential of the interface signal of the BIST circuit 32 of NVM carries out detecting;
---test vector is added up and the test completeness detection module 44 that the integrality of test vector is detected;
---the data outputting module 45 that output order information, instruction perform time sequence information, instruction performs data message, error message, error reason; And
---to the BIST circuit 32 of NVM receive instruction and export test vector output module 46 for test vector.
The process that the BIST circuit 32 of this system to NVM is tested is as follows.
Test Host 1 sends test instruction by interface bus STROBE, TDIO, TCK to the BIST circuit 32 of NVM.Described test instruction comprises test pattern (TESTMODE) etc.The BIST circuit 32 of NVM performs the instruction received, to NVM chip circuit 31 and each analog module 21,22,23 ... operate.The BIST circuit 32 of NVM receive again NVM chip circuit 31 and each analog module 21,22,23 ... the simulation waveform generated.Meanwhile, automatic detection module 4 synchronously detects:
Interface signal detection module 41 detects the interface signal of the BIST circuit 32 of NVM, and carries out automatic comparison to the instruction that the instruction received by the BIST circuit 32 of NVM and Test Host 1 send, and detects the correctness that instruction sends; The correctness that the BIST circuit 32 also detecting NVM is connected with the interface signal of Test Host 1.
The current state of system state detection module 43 detection system whether be in emulation initial, reset start, reset terminate, system is initial, system performs and test pattern and non-test, mode etc., and under detecting each state, whether coherent signal consistent with design specification.
Instruction performs time-series rules module 43 and analyzes its sequential according to the effective instruction detected, as the deration of signal, set up retention time, signal sequence etc., and accordingly to each analog module 21,22,23 ... detect with the relevant interface signal of NVM chip circuit 31, confirm that its sequential is correct.
Test completeness detection module 44, according to the effective instruction detected, judges the correctness of current data.Also test vector is added up, complete the detection of test vector integrality.
The test result of automatic detection module 4 is exported by data outputting module 45, comprise system state, current test, command information (such as present instruction), instruction performs time sequence information, instruction performs data message, error message, error reason, detection integrality etc., output of all classifying.
Test vector exports by 16 systems, 8 systems, 2 systems by test vector output module 46, for silicon test board directly, can facilitate the debugging of silicon test board.
The simulation detection system of the BIST circuit of described NVM is by automatically detecting, automatically can detect that the BIST circuit 32 of NVM and NVM chip circuit 31 are being connected and Problems existing in performing, and navigate to corresponding circuit and instruction, really achieve the automatic detection to BIST circuit.This system can greatly reduce the emulation testing time, and acceleration problem is located, and makes detection more accurate.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. an emulation test system for NVM build-in self-test, is characterized in that, includes Test Host, multiple analog module, NVM chip circuit, NVM build-in self-test, automatic detection module;
Described NVM build-in self-test is connected with Test Host, each analog module, NVM chip circuit;
Described automatic detection module is connected with Test Host, each analog module, NVM chip circuit, NVM build-in self-test;
Described automatic detection module specifically comprises:
The accuracy that the interface signal of NVM build-in self-test is connected and NVM build-in self-test receive instruction the interface signal detection module that detects of accuracy;
System state is detected, and to whether consistent with the design specification system state detection module detected of the coherent signal under each system state; Wherein, system state comprises: emulation is initial, reset start, reset terminate, system is initial, system performs, test pattern and non-test, mode;
To NVM build-in self-test receive instruction sequential detect, and time-series rules module is performed to the instruction that the sequential of the interface signal of each analog module and NVM build-in self-test detects;
Test vector is added up and the test completeness detection module that the integrality of test vector is detected;
The data outputting module that output order information, instruction perform time sequence information, instruction performs data message, error message, error reason; And
To NVM build-in self-test receive instruction and export as the test vector output module of test vector;
Wherein, NVM refers to nonvolatile memory.
2. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, described interface signal detection module detects the correctness that NVM build-in self-test is connected with the interface signal of Test Host.
3. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, described interface signal detection module also carries out automatic comparison to the instruction that the instruction received by NVM build-in self-test and Test Host send, and detects the correctness that instruction sends.
4. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, described instruction performs the sequential that time-series rules module 43 pairs of NVM build-in self-tests institute receives instruction and analyzes, and analysis content comprises the deration of signal, sets up the retention time, signal sequence; And accordingly the sequential of the interface signal of each analog module and NVM chip circuit is detected, confirm that its sequential is correct.
5. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, described test completeness detection module also judges the correctness of current data according to the instruction detected.
6. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, the test result of described automatic detection module is carried out classification by data outputting module and is exported, described test result comprises system state, current test, command information, and instruction performs time sequence information, instruction performs data message, error message, error reason, detection integrality.
7. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, test vector exports for silicon test board directly by 16 systems, 8 systems or 2 systems by described test vector output module.
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| US10372566B2 (en) * | 2016-09-16 | 2019-08-06 | Micron Technology, Inc. | Storing memory array operational information in nonvolatile subarrays |
| CN110600071B (en) * | 2018-06-12 | 2021-06-01 | 华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| CN115691632B (en) * | 2022-10-19 | 2023-07-07 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
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| CN1170936A (en) * | 1996-05-15 | 1998-01-21 | 三星电子株式会社 | Semiconductor integrated circuit having test circuit |
| CN201522856U (en) * | 2009-11-11 | 2010-07-07 | 盛科网络（苏州）有限公司 | Device for carrying out on-line debugging to memory interface circuit |
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| JP2007294015A (en) * | 2006-04-25 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit and bist circuit design method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1170936A (en) * | 1996-05-15 | 1998-01-21 | 三星电子株式会社 | Semiconductor integrated circuit having test circuit |
| CN201522856U (en) * | 2009-11-11 | 2010-07-07 | 盛科网络（苏州）有限公司 | Device for carrying out on-line debugging to memory interface circuit |
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| SoC嵌入式flash存储器的内建自测试设计;鉴海防等;《微电子学与计算机》;20050430;第22卷(第4期);第87-91页 * |
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