CN103137211A - Simulation testing system of non-volatile memory (NVM) built-in self-testing circuit - Google Patents
Simulation testing system of non-volatile memory (NVM) built-in self-testing circuit Download PDFInfo
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- CN103137211A CN103137211A CN2011103883915A CN201110388391A CN103137211A CN 103137211 A CN103137211 A CN 103137211A CN 2011103883915 A CN2011103883915 A CN 2011103883915A CN 201110388391 A CN201110388391 A CN 201110388391A CN 103137211 A CN103137211 A CN 103137211A
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Abstract
The invention discloses a simulation testing system of a non-volatile memory (NVM) built-in self-testing circuit. The simulation testing system of the NVM built-in self-testing circuit comprises a testing host computer, a plurality of simulation modules, an NVM chip circuit, the NVM built-in self-testing circuit, and an automatic detection module. The automatic detection module specifically comprises an interface signal detecting module, a system state detecting module, an instruction execution timing sequence detecting module, a test integrity detecting module, a data output module, and a test vector output module. According to the simulation testing system of the NVM built-in self test circuit, workload of detection of the NVM built-in self-testing circuit is greatly reduced, and integrity of a test is guaranteed.
Description
Technical field
The present invention relates to the emulation test system of a kind of NVM (Non-Volatile Memory, nonvolatile memory).
Background technology
Built-in self-test (Built-in Self Test is called for short BIST) technology is to implant the circuit that the self detecting function function is provided in circuit design, reduces device detection to the degree of dependence of ATE (automatic test equipment) (ATE) with this.The BIST technology can be applied to nearly all circuit, therefore is widely used in semi-conductor industry.
For example, the BIST technology of generally using in NVM is included in implants resolution chart circuit for generating, sequential circuit, mode selection circuit and debugging test circuit etc. in the NVM circuit, and they are collectively referred to as the BIST circuit.
See also Fig. 1, this is the emulation test system of the BIST circuit of a kind of existing NVM.This system includes Test Host 1; A plurality of analog modules 21,22,23, NVM chip circuit 31; The BIST circuit 32 of NVM.
The process that this system tests the BIST circuit 32 of NVM is as follows.Test Host 1 sends test instruction by interface bus STROBE, TDIO, TCK to the BIST circuit 32 of NVM.Described test instruction comprises test pattern (TESTMODE) etc.The BIST circuit 32 of NVM is carried out the instruction that receives, to NVM chip circuit 31 and each analog module 21,22,23 ... operate.The BIST circuit 32 of NVM receive again NVM chip circuit 31 and each analog module 21,22,23 ... the simulation waveform that generates carries out the checking of emulation correctness.
The emulation test system of the BIST circuit of above-mentioned NVM has following shortcoming.First wave test efficient is low.It two is that workload is large.It three is debug difficulties.It four is that silicon test board test vector can not be provided.It five is the integralities that can not automatically detect test vector.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of BIST circuit to NVM and carries out the emulation test system of detection automatically, and this system can realize that the sequential detection is carried out in test instruction detection, instruction, data correctness detects and information output function.
For solving the problems of the technologies described above, the emulation test system of the BIST circuit of a kind of NVM of the present invention includes Test Host; A plurality of analog modules, NVM chip circuit, the BIST circuit of NVM, automatic detection module;
Described NVM build-in self-test is connected with Test Host, each analog module, NVM chip circuit;
Described automatic detection module is connected with Test Host, each analog module, NVM chip circuit, NVM build-in self-test;
Described automatic detection module specifically comprises:
The interface signal detection module that the accuracy that the interface signal of NVM build-in self-test is connected and the accuracy of NVM instruction that build-in self-test receives detect;
The system state detection module that signal under system state and each state is detected;
Carry out the sequential detection module to the sequential of NVM instruction that build-in self-test receives and to the instruction that the sequential of the interface signal of each analog module and NVM build-in self-test detects;
The test completeness detection module that test vector is added up and the integrality of test vector is detected;
The data outputting module of time sequence information, instruction executing data information, error message, error reason is carried out in output order information, instruction; And
Instruction that build-in self-test receives is output as the test vector output module of test vector to NVM.
The present invention has realized the automatic detection of the BIST circuit of NVM, data output and test vector defeated, has following advantage:
One has been realized the state-detection of system, has automatically completed the input under each state.
Its two, realized interface signal and the command detection of BIST circuit, and sequential and Data Detection are carried out in each instruction.
Its three, realized the output classifyed in detail of the information that detects.
Its four, the output of test vector is provided, can be directly for the silicon test board.
Its five, completed testing the detection that becomes second nature, guarantee the integrality of test vector.
Therefore, by emulation test system of the present invention, can greatly reduce the workload that the BIST circuit to NVM detects, and guarantee the integrality of test.
Description of drawings
Fig. 1 is the structural representation of emulation test system of the BIST circuit of a kind of existing NVM;
Fig. 2 is the structural representation of emulation test system of the BIST circuit of NVM of the present invention.
Description of reference numerals in figure:
1 is Test Host; 21,22,23 ... be each analog module; 31 is the NVN chip circuit; 32 is the BIST circuit of NVM; 4 is automatic detection module; 41 is the interface signal detection module; 42 is the system state detection module; 43 are instruction execution sequential detection module; 44 is the test completeness detection module; 45 is data outputting module; 46 is the test vector output module.
Embodiment
See also Fig. 2, this is the emulation test system of the BIST circuit of a kind of NVM of the present invention.This system includes Test Host 1; A plurality of analog modules 21,22,23, NVM chip circuit 31; The BIST circuit 32 of NVM; Automatic detection module 4.
The BIST circuit 32 of described NVM and Test Host 1, each analog module 21,22,23 ..., NVM chip circuit 31 is connected.Test Host 1, a plurality of analog module 21,22,23 ... consist of the normal operation circumstances of the BIST circuit 32 of NVM with NVM chip circuit 31.
Described automatic detection module 4 and Test Host 1, each analog module 21,22,23 ..., NVM chip circuit 31, NVM BIST circuit 32 be connected.Each module that 4 pairs of this automatic detection modules connect detects, and realizes that Data Detection and sequential detect, and can carry out analyzing and positioning to relevant issues.
Described automatic detection module 4 specifically comprises:
---the interface signal detection module 41 that the accuracy of the accuracy that the interface signal of the BIST circuit 32 of NVM is connected and the BIST instruction that circuit receives of NVM detects;
---the system state detection module 42 that the signal under system state and each state is detected;
---to the sequential of BIST circuit 32 instruction that receives of NVM and to each analog module 21,22,23 ... carry out sequential detection module 43 with the instruction that the sequential of the interface signal of the BIST circuit 32 of NVM detects;
---the test completeness detection module 44 that test vector is added up and the integrality of test vector is detected;
---the data outputting module 45 of time sequence information, instruction executing data information, error message, error reason is carried out in output order information, instruction; And
---BIST circuit 32 instruction that receives of NVM is output as the test vector output module 46 of test vector.
The process that this system tests the BIST circuit 32 of NVM is as follows.
Test Host 1 sends test instruction by interface bus STROBE, TDIO, TCK to the BIST circuit 32 of NVM.Described test instruction comprises test pattern (TESTMODE) etc.The BIST circuit 32 of NVM is carried out the instruction that receives, to NVM chip circuit 31 and each analog module 21,22,23 ... operate.The BIST circuit 32 of NVM receive again NVM chip circuit 31 and each analog module 21,22,23 ... the simulation waveform that generates.Meanwhile, automatic detection module 4 synchronously detects:
Interface signal detection module 41 detects the interface signal of the BIST circuit 32 of NVM, and received instruction is carried out automatic comparison with the instruction that Test Host 1 sends to the BIST circuit 32 of NVM, detects the correctness of instruction transmission; Also detect the correctness that the BIST circuit 32 of NVM is connected with the interface signal of Test Host 1.
Whether the current state of system state detection module 43 detection systems is in that emulation is initial, the beginning that resets, ends that reset, system initially, system's execution and test pattern and non-test pattern etc., and detect under each state coherent signal and whether follow design specification consistent.
Instruction is carried out sequential detection module 43 and is analyzed its sequential according to the effective instruction that detects, as the deration of signal, set up retention time, signal sequence etc., and accordingly to each analog module 21,22,23 ... detect with the relevant interface signal of NVM chip circuit 31, confirm that its sequential is correct.
Test completeness detection module 44 judges the correctness of current data according to the effective instruction that detects.Also test vector is added up, completed the detection of test vector integrality.
The test result of automatic detection module 4 is exported by data outputting module 45, comprise system state, current test, command information (for example present instruction), time sequence information, instruction executing data information, error message, error reason, detection integrality etc. are carried out in instruction, all classification output.
Test vector output module 46 by 16 systems, 8 systems, 2 system outputs, can for the silicon test board directly, facilitate the debugging of silicon test board with test vector.
The simulation detection system of the BIST circuit of described NVM is by automatically detecting, the problem that the BIST circuit 32 that can automatically detect NVM and NVM chip circuit 31 exist in being connected and carrying out, and navigate to corresponding circuit and instruction, really realized the automatic detection to the BIST circuit.This system can greatly reduce the emulation testing time, and acceleration problem is located, and makes detection more accurate.
These are only the preferred embodiments of the present invention, be not intended to limit the present invention.For a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (8)
1. the emulation test system of a NVM build-in self-test, is characterized in that, includes Test Host; A plurality of analog modules, NVM chip circuit, NVM build-in self-test, automatic detection module;
Described NVM build-in self-test is connected with Test Host, each analog module, NVM chip circuit;
Described automatic detection module is connected with Test Host, each analog module, NVM chip circuit, NVM build-in self-test;
Described automatic detection module specifically comprises:
The interface signal detection module that the accuracy that the interface signal of NVM build-in self-test is connected and the accuracy of NVM instruction that build-in self-test receives detect;
The system state detection module that signal under system state and each state is detected;
Carry out the sequential detection module to the sequential of NVM instruction that build-in self-test receives and to the instruction that the sequential of the interface signal of each analog module and NVM build-in self-test detects;
The test completeness detection module that test vector is added up and the integrality of test vector is detected;
The data outputting module of time sequence information, instruction executing data information, error message, error reason is carried out in output order information, instruction; And
Instruction that build-in self-test receives is output as the test vector output module of test vector to NVM.
2. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, described interface signal detection module detects the correctness that the NVM build-in self-test is connected with the interface signal of Test Host.
3. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, described interface signal detection module also carries out automatic comparison to the instruction that the received instruction of NVM build-in self-test and Test Host send, and detects the correctness that instruction sends.
4. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, whether the current state of described system state detection module detection system is that emulation is initial, the beginning that resets, ends that reset, system initially, system's execution, test pattern, non-test pattern, and whether the signal that detects under each state follows design specification consistent.
5. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, described instruction is carried out the sequential of 43 pairs of NVM instructions that build-in self-test receives of sequential detection module and is analyzed, and the analysis content comprises the deration of signal, sets up the retention time, signal sequence; And accordingly the sequential of the interface signal of each analog module and NVM chip circuit is detected, confirm that its sequential is correct.
6. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, described test completeness detection module also judges the correctness of current data according to the instruction that detects.
7. the emulation test system of NVM build-in self-test according to claim 1, it is characterized in that, the test result of described automatic detection module is by the data outputting module output of classifying, described test result comprises system state, current test, command information, and time sequence information, instruction executing data information, error message, error reason, detection integrality are carried out in instruction.
8. the emulation test system of NVM build-in self-test according to claim 1, is characterized in that, described test vector output module with test vector by 16 systems, 8 systems, 2 system outputs for the silicon test board directly.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110600071A (en) * | 2018-06-12 | 2019-12-20 | 四川华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| US11392468B2 (en) * | 2016-09-16 | 2022-07-19 | Micron Technology, Inc. | Storing memory array operational information in non-volatile subarrays |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
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| CN1170936A (en) * | 1996-05-15 | 1998-01-21 | 三星电子株式会社 | Semiconductor integrated circuit having test circuit |
| US20080040640A1 (en) * | 2006-04-25 | 2008-02-14 | Kazuhiro Okabayashi | Semiconductor integrated circuit and bist circuit design method |
| CN201522856U (en) * | 2009-11-11 | 2010-07-07 | 盛科网络（苏州）有限公司 | Device for carrying out on-line debugging to memory interface circuit |
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| CN1170936A (en) * | 1996-05-15 | 1998-01-21 | 三星电子株式会社 | Semiconductor integrated circuit having test circuit |
| US20080040640A1 (en) * | 2006-04-25 | 2008-02-14 | Kazuhiro Okabayashi | Semiconductor integrated circuit and bist circuit design method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11392468B2 (en) * | 2016-09-16 | 2022-07-19 | Micron Technology, Inc. | Storing memory array operational information in non-volatile subarrays |
| US20220382658A1 (en) * | 2016-09-16 | 2022-12-01 | Micron Technology, Inc. | Storing memory array operational information in non-volatile subarrays |
| CN110600071A (en) * | 2018-06-12 | 2019-12-20 | 四川华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| CN110600071B (en) * | 2018-06-12 | 2021-06-01 | 华大恒芯科技有限公司 | NVM chip reliability test system and test method |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
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| CN103137211B (en) | 2016-04-13 |
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