CN115691632A

CN115691632A - Test control system and method

Info

Publication number: CN115691632A
Application number: CN202211280194.6A
Authority: CN
Inventors: 石昊明; 刘明; 杨媛媛; 李彦
Original assignee: Sunlune Technology Beijing Co Ltd
Current assignee: Shenglong Singapore Pte Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-02-03
Anticipated expiration: 2042-10-19
Also published as: CN115691632B

Abstract

The invention provides a test control system and a method, wherein the system comprises a register, a test vector conversion unit connected with the register, and a BIST unit connected with the test vector conversion unit. The register is used for acquiring N first test instructions in a first test mode from the upper computer; the test vector conversion unit is used for pulling N first test instructions from the register, generating first addresses corresponding to the first test instructions, and sending the first addresses and the first test instructions to the BIST unit according to a preset time sequence; and the BIST unit is used for testing the memory according to the action indicated by the N first test instructions after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively. The memory can be tested at any time, and the time sequence does not need to be considered when the first test instruction is written into the register, so that the test efficiency of the memory is improved.

Description

Test control system and method

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to a test control system and a test control method.

Background

With the development of integrated circuits, chips have larger scale and higher integration level, and meanwhile, the failure rate of memories in the chips is increased. The defect of any bit in the memory can cause the bad phenomena of system halt, application program restart breakdown and the like when the chip is applied to equipment such as a mobile phone, a tablet and the like. Therefore, the problems of how to perform failure testing on the memory in the chip and how to improve the failure testing efficiency of the memory are important in the field of integrated circuits.

The existing memory Test method is to introduce a Built-in Self Test (BIST) unit into a chip, send a Test excitation signal to the BIST unit from an external device of the chip, and perform a fault Test on a memory in the chip by running Built-in Self Test software and hardware after the BIST unit receives the Test excitation signal sent by the external device.

On the one hand, however, the BIST test pin of the chip is not usually packaged in mass production of the chip, so that when the memory in the chip needs to be tested after the chip is packaged, the test stimulus signal cannot be introduced from an external device, and therefore, the memory in the chip cannot be tested for faults; on the other hand, the external device needs to send all information of the test excitation signal to the BIST unit in series according to a strict time sequence, so that the signal sending efficiency is low, errors are easy to send, the test efficiency is reduced, and test resources are wasted.

Disclosure of Invention

The embodiment of the application provides a test control system and a test control method, which can realize the efficient test of a memory at any time.

In a first aspect, an embodiment of the present application provides a test control system, where the system includes a register, a test vector transformation unit connected to the register, and a built-in self-test BIST unit connected to the test vector transformation unit;

the register is used for acquiring N first test instructions in a first test mode from the upper computer, the first test mode is one of M preset test modes, and N and M are positive integers;

the test vector conversion unit is used for pulling the N first test instructions from the register, generating a first address corresponding to each first test instruction in the N first test instructions, and sending the first address and the first test instruction to the BIST unit according to a preset time sequence;

and the BIST unit is used for testing the memory according to the action indicated by the N first test instructions after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively.

In a second aspect, an embodiment of the present application provides a test control method, which is applied to a test control system including a register, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit.

The register acquires N first test instructions in a first test mode from the upper computer, wherein the first test mode is one of M preset test modes, and N and M are positive integers;

the test vector conversion unit pulls the N first test instructions from the register, generates a first address corresponding to each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence;

after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to the actions indicated by the N first test instructions.

In summary, according to the technical solution of the present application, when testing a memory, first, writing N first test instructions in a first test mode into a register through an upper computer; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence; after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to the actions indicated by the N first test instructions. Compared with the existing test method, the test excitation signal is input into the BIST unit from the test pin corresponding to the BIST unit through the external equipment, the first test instruction is written into the register through the pin of the register, and the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged in the mass production of chips is solved; meanwhile, in the existing test method, the external device needs to send all information of the test excitation signals required by the memory to the BIST unit according to a strict time sequence, so that the signal sending efficiency is low, and errors are easy to send. According to the embodiment of the application, only the first test instruction needs to be written in the corresponding position of the register, time sequence does not need to be considered, the efficiency of testing the memory is improved, and the operation complexity of a tester is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a diagram illustrating a conventional memory test system according to an embodiment of the present application;

fig. 2 is a schematic diagram of a test control system according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a control module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another control module provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of another control module provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of another control module provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of another control module provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of another test control system provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of another test control system provided in an embodiment of the present application;

fig. 10 is a flowchart illustrating a test control method according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The test control system and the test control method provided by the embodiment of the application can be applied to any field needing to test the memory.

Along with the development of integrated circuits, the density and speed of the integrated circuits are higher and higher, and meanwhile, the failure rate of the integrated circuits is also improved. For a memory in an integrated circuit chip, when an ECC (Error correction Code) is not performed on the memory, a production defect of any bit in the memory may cause a system crash, a restart application crash, and the like when the chip including the memory is applied to a device such as a mobile phone and a tablet.

At present, the test items for the chip mainly include:

CP (Circuit bonding, wafer test) testing is performed between wafer fabrication and packaging in the whole chip fabrication process, and the testing object is for each Die (Die before chip packaging) in the whole wafer (wafer), so as to ensure that each Die in the whole wafer can substantially meet the characteristics of the device or the design specification, which usually includes verification of voltage, current, timing and function. Can be used to check the process level of factory manufacturing.

The FT (Final Test) Test is the Final functional and performance Test performed on the chip after packaging is completed. After the CP test is finished, the chip is packaged, and the test object of the FT test is the packaged chip. The process level of the packaging plant can be detected by the FT test.

At present, in the CP and FT test stages, a method for testing a memory in a chip includes introducing a BIST unit into the chip, sending a test stimulus signal to the BIST unit from an external device of the chip, and performing a fault test on the memory in the chip by running built-in self-test software and hardware after the BIST unit receives the test stimulus signal sent by the external device.

The BIST test is to embed a test circuit and a test algorithm into a chip to be tested, the test circuit can be controlled to automatically generate test excitation and obtain a test response only by introducing a control signal from the outside, and the test circuit can automatically compare the test response with an expected response to determine whether the circuit has a fault.

Fig. 1 is a schematic diagram of a conventional memory test system according to an embodiment of the present disclosure.

As shown in fig. 1, a built-in self test BIST unit is added to the design of the chip. In CP and FT testing stage, generating all information of test excitation signal required by the memory by external equipment (such as computer, upper computer, etc.), and inputting all information of test excitation signal required by the memory into the BIST unit in series through test pin led out by test probe or BIST unit, the BIST unit issuing test data to the memory according to the received test excitation signal by running built-in self-test hardware and software, checking the defect or fault of the circuit to be tested, obtaining test result data, and feeding back the test result data to the external equipment through test pin led out by test probe or BIST unit; and after the external equipment receives the test result data, analyzing the test result data to obtain the dead pixel condition in the memory.

As described above, on one hand, in the prior art, the test pins corresponding to the BIST unit are not usually packaged during mass production of chips, so that after the chips are packaged, when a memory inside the chip needs to be tested, test stimulus signals cannot be introduced from an external device, and thus the memory cannot be tested for faults; on the other hand, the prior art does not consider the repeated information in the test stimulus signal required by the memory, and each time the test stimulus signal is input to the BIST unit, all information of the test stimulus signal required by the memory needs to be serially transmitted to the BIST unit according to strict timing requirements, so that the signal transmission efficiency is low, transmission errors are easy, the test efficiency is reduced, and test resources are wasted.

In order to solve the above technical problems, embodiments of the present application provide a test control system and method, where the system includes a register disposed inside a chip, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit. When the memory is tested, writing N first test instructions in a first test mode into the register through the upper computer; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence; after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to the actions indicated by the N first test instructions. Compared with the existing test method, the test method has the advantages that all information of the test excitation signals required by the memory is input into the BIST unit from the test pin corresponding to the BIST unit through the external equipment, the first test instruction is written into the register through the pin of the register, and the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during the mass production of chips is solved; meanwhile, in the existing test method, the external device needs to send all information of the test excitation signals required by the memory to the BIST unit according to a strict time sequence, so that the signal sending efficiency is low, and errors are easy to send. According to the embodiment of the application, only the first test instruction needs to be written in the corresponding position of the register, time sequence does not need to be considered, the efficiency of testing the memory is improved, and the operation complexity of a tester is reduced.

The technical solutions of the embodiments of the present application are described in detail below with reference to some embodiments. The following several embodiments may be combined with each other and may not be described in detail in some embodiments for the same or similar concepts or processes.

Fig. 2 is a schematic diagram of a test control system according to an embodiment of the present disclosure.

As shown in fig. 2, a test control system includes a register, a test vector conversion unit connected to the register, and a built-in self test BIST unit connected to the test vector conversion unit;

the test vector conversion unit is used for pulling N first test instructions from the register, generating a first address corresponding to each of the N first test instructions, and sending the first address and the first test instructions to the BIST unit according to a preset time sequence;

It should be noted that the M test patterns are the test patterns required by the BIST unit to perform a complete test on the memory.

It should be noted that the number of registers in fig. 2 is merely an example, and the present application does not specifically limit the number of registers.

Memory testing requires the use of a large number of test instructions, and therefore, it is important to select an efficient test method within the limited test time.

The existing test method is to use external equipment to operate a signal line connected to a serial input pin of the BIST unit, and form high and low levels by switching on and off to send all information of test excitation signals to the BIST unit. However, in the conventional test method, the bandwidth of the signal line connected to the serial input pin of the BIST unit is small, and only 1 bit can be transmitted per one clock, so that the transmission efficiency of the test stimulus signal is low, and transmission errors are liable to occur. The test excitation signal required by the BIST unit is analyzed to obtain the repeated information in the test excitation signal, the test vector conversion unit is introduced, the test vector conversion unit generates the repeated information in the test excitation signal, the upper computer writes different information in the test excitation signal into the register, and the test vector conversion unit sends the repeated information in the generated test excitation signal and different information in the test excitation signal obtained from the register to the BIST unit according to the time sequence and bandwidth required by the BIST unit, so that the BIST unit tests the memory based on the test excitation signal. When the tester operates the upper computer to write different information in the test excitation signal into the register, the time sequence does not need to be considered, the complexity of test operation is reduced, and the test efficiency is improved.

In the embodiment of the application, the upper computer configures the first test instruction to the register, and the test vector conversion unit automatically generates the first address corresponding to the first test instruction by considering that the repeated information in the test excitation signal required by the BIST unit is address information, and the address information corresponding to the N first test instructions in each first test mode is the same; and sending a first address corresponding to the first test instruction and the first test instruction to the BIST unit. Therefore, when the instructions are sent to the BIST unit, a tester only needs to operate the upper computer to write the N first test instructions in the first test mode into the register without considering the time sequence, and under each clock signal, the multi-bit first test instructions can be written into the register, for example, the first test instructions are 32 bits, and the 32 bits can be written into the register under one clock signal, so that the issuing time of the test instructions is shortened; the test vector conversion unit can automatically generate the first address corresponding to each first test instruction without continuously sending high and low levels to the serial input pin of the BIST unit by operating external equipment to send address information, so that the test method is more efficient and simpler for testers.

The embodiment of the present application does not specifically limit the type of the memory.

In one example, the Memory is a DRAM (Dynamic Random Access Memory).

In another example, the Memory is a Synchronous Dynamic Random Access Memory (SDRAM).

The present embodiment does not specifically limit the order in which the test vector conversion unit sends the BIST unit the first address and the first test instruction corresponding to the first test instruction.

In one example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction, and sends the first address to the BIST unit before sending the first test instruction to the BIST unit.

In another example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction, and sends the first test instruction to the BIST unit first, and then sends the first address to the BIST unit.

In another example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction and sends the first test instruction and the first address corresponding to the first test instruction to the BIST unit at the same time.

The embodiment of the present application does not specifically limit the manner in which the test vector conversion unit sends the first address and the first test instruction corresponding to the first test instruction to the BIST unit.

In one example, the test vector conversion unit sends a first address corresponding to the first test instruction to the BIST unit through one address signal line; the first test instruction is sent to the BIST unit through 32 data signal lines.

In another example, the test vector conversion unit sends a first address corresponding to the first test instruction to the BIST unit through a signal line, and then sends the first test instruction to the BIST unit.

In some embodiments, the test vector conversion unit is specifically configured to generate a first address corresponding to the first test instruction when the first signal is detected, where the first signal is used to instruct the upper computer to successfully write the N first test instructions into the register.

Specifically, after the upper computer writes N first test instructions in the first test mode into the register, the upper computer sends a first signal to the test vector conversion unit through the register; when the test vector conversion unit detects the first signal, a first address corresponding to the first test instruction is generated; for each first test instruction in the N first test instructions, the test vector conversion unit sends the generated first address corresponding to the first test instruction and the first test instruction to the BIST unit.

In the prior art, an external device operates a signal line connected to a serial input pin of a BIST unit, and transmits address information and instruction information to the BIST unit by switching on and off to form high and low levels, so that the BIST unit cannot be prevented from receiving the address information and the instruction information once data transmission is wrong, and the BIST unit receives the wrong information. According to the embodiment of the application, the upper computer controls the test vector conversion unit, and when the upper computer writes the first test instruction into the register, if the first test instruction is wrongly written, the first signal cannot be sent to the test vector conversion unit, so that the test vector conversion unit cannot send the first test instruction to the BIST unit, the BIST unit is prevented from receiving wrong information, and wrong operation is performed on the register.

It should be noted that the test vector conversion unit may be an independent functional unit in the test control system, or the test vector conversion unit and other functional units may be integrated in the control module, which is not limited in this application.

The following embodiments illustrate the present application by taking the example that the test vector conversion unit is integrated in the control module.

Fig. 3 is a schematic diagram of a control module according to an embodiment of the present disclosure.

As shown in fig. 3, the control module includes a test vector conversion unit and a result acquisition unit.

In some embodiments, the BIST unit is configured to send a third signal to the test vector conversion unit after receiving a last test instruction in the first test mode;

and the test vector conversion unit is used for sending a fourth signal to the register based on the third signal so as to send a second signal to the result acquisition unit when the upper computer determines that the first test mode is the last test mode in the M test modes based on the fourth signal.

The upper computer writes a first test instruction corresponding to the last test mode in the M test modes into the register and sends a first signal to the test vector conversion unit, and after the test vector conversion unit detects the first signal, the test vector conversion unit generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions in the last test mode and sends the first address corresponding to the first test instruction and the first test instruction to the BIST unit; when the BIST unit receives the last first test instruction in the N first test instructions, the BIST unit sends a third signal to the test vector conversion unit; the test vector conversion unit sends a fourth signal to the register based on the third signal, and after the upper computer connected with the register detects the fourth signal, the BIST unit is determined to successfully receive a first test instruction corresponding to the last test mode in the M test modes, and sends a second signal to the result acquisition unit.

In some embodiments, the result obtaining unit is configured to send a first request to the BIST unit when the second signal is detected, where the first request is used to request a test result of the memory, and the second signal is triggered after the test of each test instruction in the M test modes is finished;

and the BIST unit is used for acquiring the test result from the memory based on the first request and sending the test result to the result acquisition unit.

In some embodiments, the result obtaining unit is configured to generate a result obtaining instruction and a second address corresponding to the result obtaining instruction when the second signal is detected, and send the second address corresponding to the result obtaining instruction and the result obtaining instruction to the BIST unit;

and the BIST unit is used for acquiring the test result from the memory according to the result acquisition instruction after receiving the result acquisition instruction and the second address, and sending the test result to the result acquisition unit.

The embodiment of the present application does not specifically limit the number of bits that the result obtaining unit obtains the test result from the memory each time through the BIST unit.

In one example, the result obtaining unit sends a result obtaining instruction to the BIST unit upon detecting the second signal, and the BIST unit obtains 32-bit test result data from the memory each time based on the result obtaining instruction and sends the test result data to the result obtaining unit.

In another example, the result obtaining unit sends a result obtaining instruction to the BIST unit when the second signal is detected, and the BIST unit obtains 64-bit test result data from the memory at a time based on the result obtaining instruction and sends the test result data to the result obtaining unit.

Fig. 4 is a schematic diagram of another control module provided in an embodiment of the present application.

As shown in fig. 4, the control module includes a test vector conversion unit, a result acquisition unit, and a result processing unit.

In some embodiments, the result processing unit is configured to obtain the test result from the result obtaining unit, analyze the test result, obtain the problem data of the memory, and send the problem data to the register.

The problem data comprises at least one of the number of rows with dead pixels in the memory, the row number of the previous P rows in the rows with dead pixels in the memory and the total number of the dead pixels in the memory, wherein P is a positive integer.

In one example, the result processing unit is configured to obtain the test result from the result obtaining unit, analyze the test result to obtain the number of rows with bad pixels in the memory and the row number of the previous P rows in the rows with bad pixels in the memory, and send the number of rows with bad pixels in the memory and the row number of the previous P rows in the rows with bad pixels in the memory to the register.

In another example, the result processing unit is configured to obtain the test result from the result obtaining unit, and analyze the test result to obtain the number of rows with dead pixels in the memory, the row number of the previous P rows in the rows with dead pixels in the memory, and the total number of dead pixels in the memory; and the number of the rows with the dead pixel in the memory, the row number of the previous P rows in the rows with the dead pixel in the memory and the total number of the dead pixels in the memory are sent to the register.

In the prior art, the BIST unit feeds back only the test result to the external device, and in order to obtain the condition that a dead pixel exists in the memory, a tester is required to analyze the test result. According to the embodiment of the application, the result processing unit is introduced into the control module in the chip, the test result of the memory can be directly counted and analyzed in the chip, the row number of the row with the dead pixel in the memory, the row number of the previous P row in the row with the dead pixel and the number of the total dead pixels in the memory are obtained, the row number of the row with the dead pixel in the memory, the row number of the previous P row in the row with the dead pixel and the number of the total dead pixels in the memory are sent to the register, and a tester can directly obtain the dead pixel condition of the memory through the upper computer.

Fig. 5 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 5, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, and a timeout detection unit.

When the BIST unit has a defect or an abnormality, which may cause the BIST unit to fail to send the third signal to the test vector conversion unit when receiving the last first test instruction of the N first test instructions in the first test mode, or the BIST unit delays sending the third signal; the test vector conversion unit cannot receive the third signal in time and sends a fourth signal to the register based on the third signal, so that the control module is blocked and the test of the memory is influenced. According to the embodiment of the application, the overtime detection unit is introduced to time the execution time of the first test mode, and when the execution time of the first test mode exceeds the preset execution time, the test is stopped, so that the control module is prevented from being stuck.

In some embodiments, the timeout detecting unit is configured to start timing after detecting the first signal, stop timing after receiving the third signal sent by the BIST unit, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector converting unit when the execution time of the first test mode is greater than a preset execution time, where the fifth signal is used to instruct to stop testing the memory.

In some embodiments, the timeout detecting unit is configured to start timing after the first signal is detected, stop timing when the timing time of the timeout detecting unit reaches a preset execution time of the first test mode or after receiving the third signal sent by the BIST unit, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector converting unit when the execution time is greater than the preset execution time, where the fifth signal is used to instruct to stop testing the memory.

In some embodiments, the test vector converting unit is further configured to send a tenth signal to the timeout detecting unit when the first signal is detected, where the tenth signal is used to instruct the timeout detecting unit to start timing;

the overtime detection unit is used for starting timing when detecting the tenth signal, stopping timing when the timing time of the overtime detection unit reaches the preset execution time of the first test mode or after receiving the third signal sent by the BIST unit, obtaining the execution time corresponding to the first test mode, and sending a fifth signal to the test vector conversion unit when the execution time is greater than the preset execution time, wherein the fifth signal is used for indicating that the test on the memory is stopped.

In some embodiments, the timeout detecting unit is further configured to send a sixth signal to the register when the execution time corresponding to the first test mode is greater than the preset execution time, where the sixth signal is used to indicate that the execution time of the first test mode exceeds the preset execution time.

In some embodiments, the preset execution time is a maximum execution time corresponding to the first test pattern sent by the register.

In some embodiments, the preset execution time is an average execution time corresponding to the first test pattern sent by the register.

Due to the structural characteristics of memory cells, refreshing is required to maintain the stored data information for a period of time, referred to as a refresh period.

In order to avoid the problem that in the process of obtaining the test result, when the refresh cycle of the memory is close, the test result is not stopped being obtained, and the memory is refreshed, so that the test result in the memory is lost, and the test result cannot be obtained any more, a refresh control unit is introduced into the control module in the embodiment of the application.

Fig. 6 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 6, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, and a refresh control unit.

The refresh control unit is configured to send a seventh signal to the result obtaining unit when detecting that a difference between a starting time of a next refresh cycle of the memory and a current time is smaller than a preset value, where the seventh signal is used to instruct to stop obtaining the test result.

The refresh control unit is further configured to send an eighth signal to the test vector conversion unit when detecting that a difference between a starting time of a next refresh cycle of the memory and a current time is smaller than a preset value, where the eighth signal is used to instruct the test vector conversion unit to send a refresh instruction to the BIST unit;

and the BIST unit is used for refreshing the memory once based on the refresh command.

Fig. 7 is a schematic diagram of another control module provided in an embodiment of the present application.

As shown in fig. 7, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, a refresh control unit, and a storage unit.

And the result acquisition unit is used for sending the test result to the storage unit when receiving the test result, the storage unit stores the test result, and after the storage unit finishes storing the test result, the ninth signal is sent to the register and is used for indicating that the storage of the test result is finished.

The embodiment of the present application does not specifically limit the type of the memory cell.

In one example, the Memory cell is an SRAM (Static Random Access Memory).

In another example, the storage unit is Flash (Flash memory).

In the prior art, when the external device reads the test result from the BIST unit, the test result of one bit needs to be read in a serial manner each time, and the reading efficiency is low. According to the embodiment of the application, the storage unit is introduced, the test data of the BIST unit is stored in the storage unit, and when the external equipment needs to read the test result, the multi-bit test result can be read from the storage unit at one time, so that the reading efficiency of the test result is improved.

After the result processing unit sends the problem data to the register, the problem data comprises at least one of the line number of the bad points in the memory, the line number of the previous P line in the line of the bad points in the memory and the total number of the bad points in the memory, P is a positive integer, and after the upper computer connected with the register receives the problem data, the storage unit of the bad points in the memory indicated in the problem data can be turned off, and the storage unit of the bad points in the memory can be repaired. In order to repair a memory cell with a dead pixel in a memory, a repair unit is introduced into a test control system.

Fig. 8 is a schematic diagram of another test control system according to an embodiment of the present application.

As shown in fig. 8, the test system includes a repair unit, a register, a control module connected to the register, and a built-in self-test BIST unit connected to the control module, where the control module includes a test vector conversion unit, a result obtaining unit, a result processing unit, a timeout detection unit, a storage unit, and a refresh control unit.

In some embodiments, P redundant rows and P redundant columns are included in the memory.

When the number of rows with dead pixels in the memory is less than or equal to P, the repair unit is used for sending the row number with dead pixels in the memory to the memory, so that the memory repairs the rows with dead pixels in the memory by using the P redundant rows.

When the number of the rows with dead pixels in the memory is larger than P, only the row repair function is used, and all the memory units with dead pixels in the memory cannot be repaired. In the embodiment of the application, when the number of rows of the dead pixels in the memory is larger than P, the row and column repair function is used.

When the number of rows of the dead points in the memory is larger than P, the repair unit is used for determining column information of Q redundant columns for dead point repair from P redundant columns based on the dead point positions in the test result, determining row information of R redundant rows for dead point repair from P redundant rows, and sending the column information of the Q redundant columns and the row information of the R redundant rows to the memory, so that the memory determines Q redundant columns from the P redundant columns based on the column information of the Q redundant columns and the row information of the R redundant rows, determines R redundant rows from the P redundant rows, and repairs the storage units with the dead points in the memory by using the Q redundant columns and the R redundant rows, wherein Q and R are positive integers.

In summary, according to the technical solution of the present application, when testing a memory, first, writing N first test instructions in a first test mode into a register through an upper computer; then, the test vector conversion unit connected with the register automatically generates a first address corresponding to the first test instruction when receiving the first signal, and sends the first address corresponding to the first test instruction and the first test instruction to the BIST unit according to a preset time sequence; the BIST unit tests the memory according to the N first test instructions. Compared with the existing test method, the test method has the advantages that all information of the test excitation signals required by the memory is input into the BIST unit from the test pin corresponding to the BIST unit through the external equipment, the first test instruction is written into the register through the pin of the register, and the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during the mass production of chips is solved; meanwhile, in the existing testing method, the external device needs to send all information of the testing excitation signals required by the memory to the BIST unit according to a strict time sequence.

Fig. 9 is a schematic diagram of a test control system according to an embodiment of the present application.

Taking a test control system comprising a repair unit, a register, a control module (LTC) connected with the register, and a built-in self-test BIST unit connected with the control module, wherein the control module comprises a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, a storage unit and a refresh control unit as an example; take the example of the memory to be tested as DRAM.

Table 1 shows the test patterns required for a complete test of a DRAM.

TABLE 1

As shown in table 1, the M preset test patterns include 3 first test patterns, a first test pattern 1, a first test pattern 2, and a first test pattern 3. The first test pattern 1 includes first test instructions P1, P2, P3, P4, and P5 and first addresses a, B, C, D, and E corresponding to the first test instructions P1, P2, P3, P4, and P5; the first test pattern 2 comprises first test instructions P6, P7, P8, P9 and P10, and corresponding first addresses a, B, C, D and E; the first test pattern 3 includes first test instructions P11, P12, P13, P14, and P15, and corresponding first addresses a, B, C, D, and E.

The above-mentioned P1 to P15 are 32-bit data.

As a result of analyzing the BIST test instructions required by the DRAM, the address information corresponding to all of the three first test modes is a, B, C, D, and E, and therefore, the upper computer only needs to write 5 first test instructions P1 to P5 (ltc _ cmd = { P5, P4, P3, P2, P1 }) corresponding to the first test mode 1, 5 first test instructions P6 to P10 (ltc _ cmd = { P10, P9, P8, P7, P6 }) corresponding to the first test mode 2, and 5 first test instructions P11 to P15 (ltc _ cmd = { P15, P14, P13, P12, P11 }) corresponding to the first test mode 3 into the register in a separate manner, and the test vector conversion unit generates the first addresses a, B, C, D, and E corresponding to the first test instructions in the three first test modes.

The memory test procedure is as follows:

and the upper computer writes the preset execution time corresponding to the first test mode 1 into the overtime detection unit through the register.

After writing the preset execution time corresponding to the first test pattern 1 into the register, the upper computer writes 5 first test instructions P1 to P5 corresponding to the first test pattern 1 into the register (ltc _ cmd = { P5, P4, P3, P2, P1 }), and after writing the last first test instruction, pulls up the test enable signal (the test enable signal after pulling up is equivalent to the first signal in the above embodiment).

When detecting that the test enable signal is pulled high, the test vector conversion unit generates a first address A corresponding to the P1 and sequentially sends the first address A and the P1 to the BIST unit; generating a first address B corresponding to the P2 and sequentially sending the first address B and the P2 to the BIST unit; generating a first address C corresponding to the P3 and sequentially sending the first address C and the P3 to the BIST unit; generating a first address D corresponding to the P4 and sequentially sending the first address D and the P4 to the BIST unit; and generating a first address E corresponding to the P5 and sequentially sending the first address E and the P5 to the BIST unit.

When the upper computer pulls up the test enabling signal through the register after writing in the last first test instruction in the first test mode 1, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled-up test enabling signal, and the tenth signal is used for indicating the timeout detection unit to start timing.

When the BIST unit receives the last first test instruction P5 of the 5 first test instructions, it pulls down the test busy signal (the test busy signal after pulling down is equivalent to the third signal in the above embodiment); when the BIST unit detects the first addresses corresponding to the 5 first test instructions P1-P5 and the first test instructions P1-P5 in the first test mode 1, the BIST unit performs corresponding operation on the memory once according to the actions indicated by P1, P2, P3, P4 and P5.

And the overtime detection unit stops timing when detecting that the test busy signal after being pulled down or the timing time of the overtime detection unit reaches the preset execution time of the first test mode 1.

If the overtime detection unit does not detect a low test busy signal when the timing time reaches the preset execution time of the first test mode 1, sending a fifth signal to the test vector conversion unit, wherein the fifth signal is used for indicating to stop testing the memory; the timeout detecting unit also feeds back the timeout information (corresponding to the sixth signal in the above-described embodiment) of the first test pattern 1 to the register.

After detecting that the test busy signal is pulled down, the test vector conversion unit pulls up the test completion signal (the test completion signal after pulling up is equivalent to the fourth signal in the above embodiment).

And after the upper computer connected with the register detects that the test completion signal is pulled up, the upper computer writes the preset execution time corresponding to the first test mode 2 into the overtime detection unit through the register.

After writing the preset execution time corresponding to the first test mode 2 into the register, the upper computer writes 5 first test instructions P6 to P10 under the first test mode 2 into the register, (ltc _ cmd = { P10, P9, P8, P7, P6 }), and after writing the last first test instruction P10, pulls up the test enable signal (the pulled-up test enable signal is equivalent to the first signal in the above embodiment), and when detecting that the test enable signal is pulled up, the test vector conversion unit generates a first address a corresponding to P6 and sequentially sends the first address a and P6 to the BIST unit; generating a first address B corresponding to the P7 and sequentially sending the first address B and the P7 to the BIST unit; generating a first address C corresponding to the P8 and sequentially sending the first address C and the P8 to the BIST unit; generating a first address D corresponding to the P9 and sequentially sending the first address D and the P9 to the BIST unit; and generating a first address E corresponding to the P10 and sequentially sending the first address E and the P10 to the BIST unit.

When the upper computer pulls up the test enable signal through the register after writing in the last first test instruction P10 in the first test mode 2, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled-up test enable signal, and the tenth signal is used for indicating the timeout detection unit to start timing.

When the BIST unit receives the last first test instruction P10 in the 5 first test instructions, the test busy signal is pulled down (the test busy signal after being pulled down is equivalent to the third signal in the above embodiment); when detecting the first addresses corresponding to the 5 first test instructions P6 to P10 and the first test instructions P6 to P10 in the first test mode 1, the BIST unit performs a corresponding operation on the memory according to the operations indicated by P6, P7, P8, P9 and P10.

And the overtime detection unit stops timing when detecting the pulled-down test busy signal or the timing time of the overtime detection unit reaches the preset execution time of the first test mode 2.

If the overtime detection unit does not detect the lowered test busy signal when the timing time reaches the preset execution time of the first test mode 2, a fifth signal is sent to the test vector conversion unit and used for indicating that the test on the memory is stopped; the timeout detection unit also feeds back the timeout information of the first test pattern 2 to the register.

And after the test vector conversion unit detects that the test busy signal is pulled down, pulling up the test completion signal.

And after the upper computer connected with the register detects that the test completion signal is pulled up, the upper computer writes the preset execution time corresponding to the first test mode 3 into the timeout detection unit through the register.

After writing the preset execution time corresponding to the first test mode 3 into the register, the upper computer writes 5 first test instructions P11 to P15 under the first test mode 3 into the register, (ltc _ cmd = { P15, P14, P13, P12, P11 }), and after writing the last first test instruction P15, pulls up the test enable signal (the test enable signal after pulling up is equivalent to the first signal in the above embodiment), and when detecting that the test enable signal is pulled up, the test vector conversion unit generates a first address a corresponding to P11 and sequentially sends the first address a and the BIST P11 to the unit; generating a first address B corresponding to the P12 and sequentially sending the first address B and the P12 to the BIST unit; generating a first address C corresponding to the P13 and sequentially sending the first address C and the P13 to the BIST unit; generating a first address D corresponding to the P14 and sequentially sending the first address D and the P14 to the BIST unit; and generating a first address E corresponding to the P15 and sequentially sending the first address E and the P15 to the BIST unit.

When the upper computer pulls up the test enable signal through the register after writing in the last first test instruction P15 in the first test mode 3, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled-up test enable signal, and the tenth signal is used for indicating the timeout detection unit to start timing.

The BIST unit pulls down the test busy signal when receiving the last first test instruction P15 in the 5 first test instructions (the test busy signal after pulling down is equivalent to the third signal in the above embodiment); the BIST unit performs a corresponding operation on the memory according to the operations indicated by P11, P12, P13, P14 and P15 when detecting 5 first test instructions P11 to P15 in the first test mode 3 and when detecting the first addresses corresponding to the first test instructions P11 to P15, respectively.

And the overtime detection unit stops timing when detecting that the test busy signal after being pulled down or the timing time of the overtime detection unit reaches the preset execution time of the first test mode 3.

If the overtime detection unit does not detect the lowered test busy signal when the timing time reaches the preset execution time of the first test mode 3, a fifth signal is sent to the test vector conversion unit and used for indicating that the test on the memory is stopped; the timeout detection unit also feeds back the timeout information of the first test pattern 3 to the register.

5 first test instructions in each first test mode in three first test modes required by the DRAM and a first address corresponding to the first test instructions are sent to the BIST unit according to a time sequence required by the BIST unit, the BIST unit respectively carries out three operations on the DRAM according to the three first test modes, and after the three operations are finished, the BIST unit shows that the DRAM is completely tested once.

After detecting that the test completion signal is pulled high, the upper computer connected with the register confirms that the first test instruction in the last first test mode of the three first test modes required by the DRAM is successfully received by the BIST unit, pulls up the result acquisition enable signal through the register (the pulled-up result acquisition enable signal is equivalent to the second signal in the above embodiment), and when detecting that the result acquisition enable signal is pulled high, the upper computer generates the result acquisition instruction and the second address corresponding to the result acquisition instruction, and sends the second address and the result acquisition instruction to the BIST unit.

Mode(s) for	Second Address (F)	Second Address (G)	Second Address (H)
				Result acquisition mode	P16	P17	P18

TABLE 2

Table 2 shows a test result obtaining instruction for BIST required by the DRAM, and as shown in table 2, the result obtaining unit generates a second address F corresponding to the result obtaining instruction P16 and the result obtaining instruction P16, and sends the second address F and the result obtaining instruction P16 to the BIST unit; the result obtaining unit generates a second address G corresponding to the result obtaining instruction P17 and the result obtaining instruction P17, and sends the second address G and the result obtaining instruction P17 to the BIST unit; the result obtaining unit generates a second address H corresponding to the result obtaining instruction P18 and the result obtaining instruction P18, and sends the second address H and the result obtaining instruction P18 to the BIST unit.

When the BIST unit detects second addresses F, G and H corresponding to 3 result obtaining instructions P16, P17 and P18 and P16, P17 and P18 respectively, the BIST unit obtains a test result from the memory according to the actions indicated by P16, P17 and P18 and sends the test result to the result obtaining unit.

Take the example that the DRAM includes 2048 rows, each row including 128 bits.

The BIST unit acquires 32-bit test result data from the memory every time, and the test result of each row in the DRAM returns to the result acquisition unit 4 times, wherein in the test result, 0 represents that the corresponding position in the DRAM is normal, and 1 represents that the corresponding position in the DRAM is a dead pixel.

When the result acquiring unit receives the test result, the test result is respectively sent to the storage unit (SRAM) and the result processing unit.

When the memory cell completes storing the test result, a result read completion signal (corresponding to the ninth signal in the above embodiment) is sent to the register, and the result read completion signal is used to instruct the memory cell to complete storing the test result.

The external device may read the test result from the memory cell after detecting the result read completion signal, and may read the test result of the plurality of bits from the memory cell at a time.

When detecting that the difference value between the starting time of the next refreshing period of the memory and the current time is smaller than a preset value, the refreshing control unit sends a seventh signal to the result obtaining unit, wherein the seventh signal is used for indicating to stop obtaining the test result; simultaneously sending an eighth signal to the test vector converting unit, wherein the eighth signal is used for instructing the test vector converting unit to send a refresh instruction to the BIST unit; and the BIST unit is used for refreshing the memory once based on the refreshing instruction.

In the embodiment of the present application, the memory DRAM includes 16 redundant rows and 16 redundant columns.

The result processing unit analyzes the received test result to obtain problem data of the memory, wherein the problem data comprises: the number of rows with dead pixels in the DRAM, the row number of the first 16 rows in the rows with dead pixels in the DRAM and the total number of the dead pixels in the DRAM; and sends the issue data to the register.

When the number of rows with dead pixels in the DRAM is less than or equal to 16, the repair unit sends the row number with dead pixels to the DRAM so that the DRAM uses 16 redundant rows to repair the rows with dead pixels in the DRAM.

When the number of rows of the dead pixels in the DRAM is more than 16, the upper computer acquires a test result from the storage unit and sends the test result to the repair unit; the repair unit determines column information of a plurality of redundant columns for the dead spot repair from the 16 redundant columns and row information of a plurality of redundant rows for the dead spot repair from the 16 redundant rows based on the dead spot position of the memory cell in the DRAM indicated by the test result, and transmits the column information of the redundant columns for the dead spot repair and the row information of the redundant rows for the dead spot repair to the DRAM, so that the DRAM determines the redundant columns for the dead spot repair from the 16 redundant columns based on the column information of the redundant columns for the dead spot repair and the row information of the redundant rows, determines the redundant rows for the dead spot repair from the 16 redundant rows, and repairs the memory cell having the dead spot in the DRAM using the redundant columns for the dead spot repair and the redundant rows.

In summary, according to the technical scheme of the application, when the memory is tested, N first test instructions in a first test mode are written into the register through the upper computer, and the first test mode is one test mode of preset M test modes; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence; after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to the actions indicated by the N first test instructions. Therefore, when the memory is tested, all information of the test excitation signals required by the memory does not need to be generated according to strict time sequence, only first test instructions belonging to different parts in the test excitation signals need to be written into the register by the upper computer, the time sequence does not need to be considered, and first addresses belonging to the same part in the test excitation signals are automatically generated by the test vector conversion unit; the test vector conversion unit sends the generated first address and the first test instruction to the BIST unit according to a preset time sequence; the BIST unit tests the memory based on the received first test instruction. The testing efficiency of the memory is improved, and the operation complexity of testing personnel is reduced. Compared with the existing test method, the test excitation signal is input to the BIST unit from the test pin corresponding to the BIST unit through the external equipment, the first test instruction is written into the register through the pin of the register, the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during the mass production of chips is solved, and the memory can be tested at any time.

Fig. 10 is a flowchart illustrating a test control method applied to a test control system according to an embodiment of the present application, where the test control method includes a register, a test vector transformation unit connected to the register, and a built-in self test BIST unit connected to the test vector transformation unit. As shown in fig. 10, the test control method includes the steps of:

s101, a register acquires N first test instructions in a first test mode from an upper computer, wherein the first test mode is one of M preset test modes, and N and M are positive integers;

s102, the test vector conversion unit pulls N first test instructions from the register, generates a first address corresponding to each of the N first test instructions, and sends the first address and the first test instructions to the BIST unit according to a preset time sequence;

s103, after detecting first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to actions indicated by the N first test instructions.

In some embodiments, after the upper computer successfully writes the N first test instructions into the register, the upper computer sends a first signal to the test vector conversion unit; the test vector conversion unit generates a first address corresponding to the first test instruction when detecting the first signal.

In some embodiments, the test control system further includes a result obtaining unit.

The BIST unit sends a third signal to the test vector conversion unit after receiving the last test instruction in the first test mode; the test vector conversion unit sends a fourth signal to the register based on the third signal; the upper computer sends a second signal to the result acquisition unit when detecting a fourth signal corresponding to the last test mode in the M test modes; the result acquiring unit transmits a first request to the BIST unit when the second signal is detected, and the BIST unit acquires the test result from the memory based on the first request and transmits the test result to the result acquiring unit.

In some embodiments, the test control system further comprises a timeout detection unit.

The operation modes of the timeout detection unit include mode 1 and mode 2.

Mode 1: the overtime detection unit starts timing after detecting the first signal, stops timing after receiving a third signal sent by the BIST unit to obtain execution time corresponding to the first test mode, and sends a fifth signal to the test vector conversion unit when the execution time is greater than preset execution time; and the test vector conversion unit stops testing the memory when detecting the fifth signal.

Mode 2: when the execution time corresponding to the first test mode is greater than the preset execution time, the overtime detection unit sends a fifth signal to the test vector conversion unit and also sends a sixth signal to the register; and when the register detects the sixth signal, determining that the execution time of the first test mode exceeds the preset execution time.

In some embodiments, the preset execution time is a maximum execution time corresponding to the first test mode sent by the register to the timeout detection unit.

In some embodiments, the test control system further includes a refresh control unit.

The working mode of the refresh control unit comprises the following steps: mode 1 and mode 2.

Mode 1: when detecting that the difference value between the starting time of the next refresh period of the memory and the current time is smaller than the preset value, the refresh control unit sends a seventh signal to the result acquisition unit; the result acquisition unit stops acquiring the test result when detecting the seventh signal.

Mode 2: when detecting that the difference value between the starting time of the next refreshing period of the memory and the current time is smaller than the preset value, the refreshing control unit sends a seventh signal to the result acquisition unit and also sends an eighth signal to the test vector conversion unit; when the test vector conversion unit detects the eighth signal, a refresh instruction is sent to the BIST unit; the BIST unit refreshes the memory based on the refresh instruction.

In some embodiments, the test control system further comprises a storage unit.

When receiving the test result, the result acquisition unit sends the test result to the storage unit; after the storage unit finishes receiving the test result, a ninth signal is sent to the register; and when the register detects the ninth signal, determining that the test result is completely stored.

In some embodiments, the test control system further comprises a result processing unit.

The result processing unit acquires the test result from the result acquisition unit, analyzes the test result to obtain problem data of the memory and sends the problem data to the register;

the problem data comprises at least one of the number of rows with dead pixels in the memory, the row number of the previous P rows in the rows with dead pixels in the memory and the total number of dead pixels in the memory, wherein P is a positive integer.

In some embodiments, the test control system further includes a repair unit, and the memory includes P redundant rows and P redundant columns.

The repair method of the repair unit to the memory includes a method 1 and a method 2.

Mode 1: when the number of rows with dead pixels in the memory is less than or equal to P, the repair unit sends the row number with dead pixels in the memory to the memory; when the memory receives the line number with the dead pixel, the line with the dead pixel in the memory is repaired by using the P redundant lines.

Mode 2: when the number of rows of the dead pixels in the memory is larger than P, the repair unit determines column information of Q redundant columns for dead pixel repair from the P redundant columns and row information of R redundant rows for dead pixel repair from the P redundant rows based on the dead pixel positions in the test result, and sends the column information of the Q redundant columns and the row information of the R redundant rows to the memory; the memory determines Q redundant columns from P redundant columns and R redundant rows based on column information of the Q redundant columns and row information of the R redundant rows, and repairs memory cells with dead pixels in the memory by using the Q redundant columns and the R redundant rows, wherein Q and R are positive integers.

According to the technical scheme, when the memory is tested, N first test instructions in a first test mode are written into the register through the upper computer, and the first test mode is one of M preset test modes; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence; after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively, the BIST unit tests the memory according to the actions indicated by the N first test instructions. Therefore, when the memory is tested, all information of the test excitation signals required by the memory does not need to be generated according to strict time sequence, only first test instructions belonging to different parts in the test excitation signals need to be written into the register by the upper computer, the time sequence does not need to be considered, and first addresses belonging to the same part in the test excitation signals are automatically generated by the test vector conversion unit; the test vector conversion unit sends the generated first address and the first test instruction to the BIST unit according to a preset time sequence; the BIST unit tests the memory based on the received first test instruction. The testing efficiency of the memory is improved, and the operation complexity of testing personnel is reduced. Compared with the existing test method, the test excitation signal is input to the BIST unit from the test pin corresponding to the BIST unit through the external equipment, the first test instruction is written into the register through the pin of the register, the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during the mass production of chips is solved, and the memory can be tested at any time.

The preferred embodiments of the present application have been described in detail with reference to the accompanying drawings, however, the present application is not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the present application within the technical idea of the present application, and these simple modifications are all within the protection scope of the present application. For example, the various features described in the foregoing detailed description may be combined in any suitable manner without contradiction, and various combinations that may be possible are not described in this application in order to avoid unnecessary repetition. For example, various embodiments of the present application may be arbitrarily combined with each other, and the same shall be considered as the disclosure of the present application as long as the concept of the present application is not violated.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed system may be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the unit is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be an indirect coupling or communication connection through some interfaces, circuits or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment. For example, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A test control system is characterized by comprising a register, a test vector conversion unit connected with the register and a built-in self-test BIST unit connected with the test vector conversion unit;

the register is used for acquiring N first test instructions in a first test mode from an upper computer, wherein the first test mode is one of M preset test modes, and N and M are positive integers;

the test vector conversion unit is configured to pull the N first test instructions from the register, generate a first address corresponding to each of the N first test instructions, and send the first address and the first test instruction to the BIST unit according to a preset timing;

the BIST unit is used for testing the memory according to the action indicated by the N first test instructions after detecting the first addresses corresponding to the N first test instructions and the N first test instructions respectively.

2. The system of claim 1,

the test vector conversion unit is specifically configured to generate a first address corresponding to the first test instruction when a first signal is detected, where the first signal is used to instruct the upper computer to successfully write the N first test instructions into the register.

3. The system of claim 2, further comprising a result acquisition unit;

the result obtaining unit is configured to send a first request to the BIST unit when a second signal is detected, where the first request is used to request a test result of the memory, and the second signal is triggered after the test of each test instruction in the M test modes is finished;

the BIST unit is used for acquiring the test result from the memory based on the first request and sending the test result to the result acquiring unit.

4. The system of claim 3,

the BIST unit is used for sending a third signal to the test vector conversion unit after receiving the last test instruction in the first test mode;

the test vector conversion unit is used for sending a fourth signal to the register based on the third signal so as to enable the upper computer to send the second signal to the result acquisition unit when determining that the first test mode is the last test mode in the M test modes based on the fourth signal.

5. The system of claim 4, further comprising a timeout detection unit;

the overtime detection unit is configured to start timing after the first signal is detected, stop timing after a third signal sent by the BIST unit is received, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector conversion unit when the execution time is greater than a preset execution time, where the fifth signal is used to instruct to stop testing the memory.

6. The system according to claim 5, wherein the timeout detecting unit is further configured to send a sixth signal to the register when the execution time corresponding to the first test mode is greater than a preset execution time, and the sixth signal is used to indicate that the execution time of the first test mode exceeds the preset execution time.

7. The system according to claim 6, wherein the preset execution time is a maximum execution time corresponding to the first test pattern sent by the register.

8. The system of claim 5, further comprising a refresh control unit, configured to send a seventh signal to the result obtaining unit when detecting that a difference between a starting time of a next refresh cycle of the memory and a current time is smaller than a preset value, wherein the seventh signal is used for instructing to stop obtaining the test result.

9. The system of claim 8, wherein the refresh control unit is further configured to send an eighth signal to the test vector translation unit when detecting that a difference between a starting time of a next refresh cycle of the memory and a current time is less than the preset value, the eighth signal being configured to instruct the test vector translation unit to send a refresh instruction to the BIST unit;

the BIST unit is used for refreshing the memory based on the refreshing instruction.

10. The system of claim 8, further comprising a storage unit configured to obtain the test result from the result obtaining unit and send a ninth signal to the register after the test result is obtained, wherein the ninth signal indicates that the test result is completely stored.

11. The system of claim 10, further comprising a results processing unit;

the result processing unit is used for acquiring the test result from the result acquisition unit, analyzing the test result to obtain problem data of the memory and sending the problem data to the register;

12. The system of claim 11, wherein the memory comprises P redundant rows, and wherein the system further comprises a repair unit, and when the number of rows in the memory with dead pixels is less than or equal to P, the repair unit is configured to send the row number in the memory with dead pixels to the memory, so that the memory repairs the row in the memory with dead pixels using the P redundant rows.

13. The system according to claim 12, wherein the memory further includes P redundant columns, and when the number of rows of the defective pixels in the memory is greater than P, the repair unit is configured to determine column information of Q redundant columns for defective pixel repair from the P redundant columns and row information of R redundant rows for defective pixel repair from the P redundant rows based on the defective pixel position in the test result, and send the column information of the Q redundant columns and the row information of the R redundant rows to the memory, so that the memory determines the Q redundant columns from the P redundant columns and the R redundant rows based on the column information of the Q redundant columns and the row information of the R redundant rows, and repairs the memory cells in which the defective pixels exist in the memory using the Q redundant columns and the R redundant rows, where Q and R are both positive integers.

14. A test control method is applied to a test control system, wherein the system comprises a register, a test vector conversion unit connected with the register, and a built-in self-test BIST unit connected with the test vector conversion unit;

the register acquires N first test instructions in a first test mode from an upper computer, wherein the first test mode is one of M preset test modes, and N and M are positive integers;

the test vector conversion unit pulls the N first test instructions from the register, generates a first address corresponding to each of the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence;