CN114067899A - Memory built-in self-test system and method for realizing rapid test - Google Patents
Memory built-in self-test system and method for realizing rapid test Download PDFInfo
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- CN114067899A CN114067899A CN202010757710.4A CN202010757710A CN114067899A CN 114067899 A CN114067899 A CN 114067899A CN 202010757710 A CN202010757710 A CN 202010757710A CN 114067899 A CN114067899 A CN 114067899A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
Abstract
The invention relates to a memory built-in self-test system capable of realizing rapid test, which comprises a test control circuit module, a test control circuit module and a test control module, wherein the test control circuit module is used for receiving an external test enabling signal bist _ en and controlling the operation of a test circuit; the test vector selection circuit module is used for selecting one or more test vectors to test according to the test vector selection signal pattern _ sel; the test vector generating circuit module is used for generating test vectors; the response analysis circuit module is used for comparing the values read from the memory with the test vectors. The invention also relates to a built-in self-test method for the memory, which can realize rapid test. The memory built-in self-test system and the method for realizing the rapid test are also applicable to other memories and algorithms, one or more different test vectors can be selected according to specific memory faults, different test vectors can be selected according to different memory faults, and the memory built-in self-test system and the method are applicable to different memories and algorithms.
Description
Technical Field
The invention relates to the technical field of information, in particular to the field of test circuit design, and specifically relates to a memory built-in self-test system and a method thereof for realizing rapid test.
Background
With the development of information technology, the IC design is more and more complex, the embedded memory also occupies more and more area in the SoC chip, and since the unit density of the embedded memory is high, the embedded memory easily causes silicon chip defects, and the yield of the chip is reduced, it is more and more important to realize fast and effective memory testing.
Currently, memory built-in self-test (MBIST) is a cost-effective and important technique for testing embedded memories, and MBIST usually employs one or more algorithms designed specifically for testing the defect types of the memory. For the conventional test method, if the bit width of the memory is N, X sets of test vectors are required, where X is log2N + 1. The following description will be given by taking a March C-algorithm test as an example of a 2K × 32bit SRAM.
The March C-algorithm is a well-tested algorithm that covers memory faults such as fix fault SAF, transition fault TF, coupling fault CF and address decode fault AF. The March C-algorithm expression is as follows:
{↑(W0)；↑(R0，W1)；↑(R1，W0)；↓(R0，W1)；↓(R1，W0)；↓(R0)}
wherein ↓and ↓ respectively indicate reading and writing operations to the address unit in the ascending order and the descending order of the memory address, R0 indicates reading 0 operation to the memory unit, W0 indicates writing 0 operation to the memory unit, similarly R1 indicates reading 1, and W1 indicates writing 1. The operation on the next memory location can continue to be performed only after all operations specified for the current memory location have been completed. The 1 set of test vectors requires 6 stages of the above algorithm (6 address traversals) before the next 1 set of test vectors can be performed. For 2K × 32bit SRAM, there are 6 sets of test vectors, which are:
that is, 6 times of algorithm execution (36 address traversals) is required before the test is completed.
Nowadays, the processes for manufacturing the memory are relatively mature, one mature process only generates one or more same memory defects, but some defects never appear, and all test vectors are used for testing all the time, so that much useless work is done, and the test time is wasted. At this point, it is necessary to select one or several test vectors for this particular defect to enable fast and efficient testing.
The MBIST designs a test circuit inside a chip, all test processes are carried out inside the chip, and only excitation signals need to be applied and test results need to be observed outside the chip. A typical memory built-in self-test circuit typically includes three parts, a test vector generation circuit, a test control circuit, and a response analysis circuit. The function of the test vector generating circuit is to generate test vectors, the number and value of which are determined by the bit width of the memory to be tested, and the larger the bit width, the larger the number of the test vectors. The function of the test control circuit is to control the operation of the whole test circuit, including controlling the ascending and descending order of addresses and the reading and writing of the memory. The function of the response analyzing circuit is to compare the values read from the memory with the test vectors and to derive the result whether the test was successful or not. As shown in fig. 1, the test circuit can test itself by only applying a test enable signal bist _ en externally, and finally, a test completion signal bist _ done and a test success signal bist _ ok are applied.
Taking 2K × 32bit SRAM as an example, the test vector generation circuit generates 6 sets of test vectors altogether, and each test requires that the 6 sets of test vectors be measured, and 36 address traversals are required. For memory failures that are known to not occur, it becomes inefficient to also test using the test vectors that cover it, wasting test costs.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a memory built-in self-test system and a method thereof, which have the advantages of short test time, low test cost and wide application range and can realize rapid test.
In order to achieve the above object, the memory built-in self-test system and method for realizing rapid test of the present invention are as follows:
the built-in self-test system for realizing the memory capable of being tested quickly is mainly characterized by comprising the following components:
the test control circuit module receives an external test enable signal bist _ en, and the output end of the test control circuit module is respectively connected with the test vector selection circuit module and the circuit to be tested and used for controlling the operation of the test circuit;
the test vector selection circuit module receives the test vector selection signal pattern _ sel, and the receiving end is connected with the output end of the test control circuit module and is used for selecting one or more test vectors to test according to the test vector selection signal pattern _ sel;
the receiving end of the test vector generating circuit module is connected with the output end of the test vector selecting circuit module, and the output end of the test vector generating circuit module is connected with the circuit to be tested and used for generating test vectors;
and the input end of the response analysis circuit module is connected with the test vector selection circuit module and the circuit to be tested, and is used for comparing the numerical value read from the memory with the test vector and outputting a test completion signal bist _ done and a test success signal bist _ ok.
Preferably, the test vector selection circuit module includes:
the test vector selection signal temporary storage unit is connected with the test control circuit module, receives a test vector selection signal pattern _ sel configured by a user and a primary algorithm completion signal fsm _ complete output by the test control circuit module, and outputs a temporary storage intermediate value psel _ temp;
the receiving end of the test vector coding signal generating unit is connected with the test vector selection signal temporary storage unit, the output end of the test vector coding signal generating unit is connected with the test vector generating circuit module, and the test vector selection signal pattern _ sel configured by a user is received; the test vector code signal pattern _ id is output, and the vector test complete signal pattern _ complete is used to generate the test vector signal bist _ pattern.
Preferably, the test vector selection circuit module further comprises:
and the receiving end of the NOR operation unit is connected with the test vector selection signal temporary storage unit, the output end of the NOR operation unit is connected with the response analysis circuit module, and the NOR operation unit outputs a complete vector test signal pattern _ complete for generating a test complete signal bist _ done.
Preferably, the test vector selection signal temporary storage unit comprises X groups of output subunits, and the X groups of output subunits are sequentially connected and used for sequentially testing the test vectors according to the operation priority; each group of output subunits sequentially corresponds to the bits of the temporary storage intermediate value psel _ temp, and under the condition that the test of the nth output subunit is finished, the value of the output psel _ temp [ n-1] is 0, wherein n is more than or equal to 1 and less than or equal to X.
Preferably, the test vector selection signal temporary storage unit includes 6D flip-flops, 5 and gates and 5 not gates, D ends of the 6D flip-flops all receive the test vector selection signal pattern _ sel, clock ends all receive the same clock signal, Q ends all output the temporary storage intermediate value psel _ temp, the 5 and gates and the 5 not gates constitute 5 nand gates, and the 6D flip-flops are connected through the 5 nand gates.
Preferably, the test vector code signal generating unit includes X groups of coding subunits, which are sequentially connected to each other and are configured to sequentially output a test vector code signal pattern _ id according to the operation priority and according to the temporary intermediate value; and each group of coding subunits sequentially judges whether the bit number of the temporary storage intermediate value psel _ temp is valid or not, and outputs a corresponding test vector coding signal pattern _ id under the condition that the value of psel _ temp [ m ] is 1.
Preferably, the test vector code signal generating unit comprises a D flip-flop, 7 two-way selectors, 4 or gates, 5 and gates and 5 not gates, the 7 two-way selectors are connected in sequence, the two-way selector with the highest priority is connected with the D end of the D trigger, the 5 AND gates and the 5 NOT gates form 5 NAND gates, the 5 alternative two-way selectors with lower priority are connected with the output ends of the 5 NAND gates, the output ends of the 4 OR gates are respectively connected with the input ends of the NAND gates of the 4 alternative two-way selectors with lower priority, the NAND gate and the OR gate both input a temporary storage intermediate value psel _ temp, the two-way selector with the highest priority receives a test enable signal bist _ en, and the Q end of the D trigger outputs a test vector coding signal pattern _ id.
Preferably, the test control circuit module controls the ascending order and the descending order of the addresses and the reading and writing of the memory.
Preferably, the bit width of the test vector selection signal pattern _ sel is X bits, and each bit width corresponds to a set of test vectors.
The built-in self-test method of the memory, which can realize the rapid test by utilizing the system, is mainly characterized by comprising the following steps:
(1) inputting a test vector selection signal pattern _ sel;
(2) assigning the temporary storage intermediate value psel _ temp to be equal to the test vector selection signal pattern _ sel, setting the initial value of the test vector coding signal pattern _ id to be 0, and setting the initial value of the internal signal n to be 0;
(3) calculating pattern _ complete- (| psel _ temp), outputting pattern _ complete, judging whether the pattern _ complete is 1, if so, continuing the step (5); otherwise, continuing the step (4);
(4) testing the set of test vectors;
(5) the all vector test complete signal pattern _ complete is output as 1.
Preferably, the step (4) specifically includes the following steps:
(4.1) outputting a complete all vector test signal pattern _ complete ═ 0;
(4.2) inputting a one-time algorithm completion signal fsm _ complete;
(4.3) judging whether the fsm _ complete signal of one time algorithm is equal to 1, if so, continuing to the step (4.6); otherwise, continuing the step (4.4);
(4.4) judging whether the temporary storage intermediate value psel _ temp [ n ] is equal to 1, if so, continuing the step (4.5); otherwise, increasing the value of n by 1, and continuing the step (4.4);
(4.5) assigning the pattern _ id to be n +1, outputting the test vector coding signal pattern _ id at the moment, and continuing to the step (4.2);
(4.6) assigning psel _ temp [ n ] to 0, n being n +1, and continuing to step (3) after the test of the group of test vectors is finished.
The memory built-in self-test system and the method for realizing the rapid test are also applicable to other memories and algorithms, one or more different test vectors can be selected according to specific memory faults, different test vectors can be selected according to different memory faults, and the memory built-in self-test system and the method are applicable to different memories and algorithms. The invention can select the test vector according to the memory fault, and has short test time, low test cost and wider application range.
Drawings
FIG. 1 is a block diagram of a prior art memory built-in self-test circuit.
FIG. 2 is a block diagram of a memory built-in self-test system for implementing fast testing according to the present invention.
FIG. 3 is a block diagram of a test vector selection circuit for implementing a fast testable memory built-in self-test system according to the present invention.
FIG. 4 is a schematic circuit diagram of a test vector selection signal register unit for implementing a fast testable memory built-in self-test system according to the present invention.
FIG. 5 is a schematic circuit diagram of a test vector code signal generating unit for implementing a fast testable memory built-in self-test system according to the present invention.
FIG. 6 is a flowchart of the operation of the test vector selection circuit for implementing the memory built-in self-test method for fast testing according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The memory built-in self-test system capable of realizing rapid test of the invention comprises:
the test control circuit module receives an external test enable signal bist _ en, and the output end of the test control circuit module is respectively connected with the test vector selection circuit module and the circuit to be tested and used for controlling the operation of the test circuit;
the test vector selection circuit module receives the test vector selection signal pattern _ sel, and the receiving end is connected with the output end of the test control circuit module and is used for selecting one or more test vectors to test according to the test vector selection signal pattern _ sel;
the receiving end of the test vector generating circuit module is connected with the output end of the test vector selecting circuit module, and the output end of the test vector generating circuit module is connected with the circuit to be tested and used for generating test vectors;
and the input end of the response analysis circuit module is connected with the test vector selection circuit module and the circuit to be tested, and is used for comparing the numerical value read from the memory with the test vector and outputting a test completion signal bist _ done and a test success signal bist _ ok.
As a preferred embodiment of the present invention, the test vector selection circuit module includes:
the test vector selection signal temporary storage unit is connected with the test control circuit module, receives a test vector selection signal pattern _ sel configured by a user and a primary algorithm completion signal fsm _ complete output by the test control circuit module, and outputs a temporary storage intermediate value psel _ temp;
the receiving end of the test vector coding signal generating unit is connected with the test vector selection signal temporary storage unit, the output end of the test vector coding signal generating unit is connected with the test vector generating circuit module, and the test vector selection signal pattern _ sel configured by a user is received; the test vector encoded signal pattern _ id is output for generating the test vector signal bist _ pattern.
As a preferred embodiment of the present invention, the test vector selection circuit module further includes:
and the receiving end of the NOR operation unit is connected with the test vector selection signal temporary storage unit, the output end of the NOR operation unit is connected with the response analysis circuit module, and the NOR operation unit outputs a complete vector test signal pattern _ complete which is used for generating a complete test signal bist _ done.
As a preferred embodiment of the present invention, the test vector selection signal temporary storage unit includes X groups of output subunits, and the X groups of output subunits are sequentially connected to one another and are used for sequentially testing test vectors according to an operation priority; each group of output subunits sequentially corresponds to the bits of the temporary storage intermediate value psel _ temp, and under the condition that the test of the nth output subunit is finished, the value of the output psel _ temp [ n-1] is 0, wherein n is more than or equal to 1 and less than or equal to X.
As a preferred embodiment of the present invention, the test vector selection signal temporary storage unit includes 6D flip-flops, 5 and gates, and 5 not gates, D ends of the 6D flip-flops all receive the test vector selection signal pattern _ sel, clock ends all receive the same clock signal, Q ends all output the temporary storage intermediate value psel _ temp, the 5 and gates and 5 not gates constitute 5 nand gates, and the 6D flip-flops are connected through the 5 nand gates.
As a preferred embodiment of the present invention, the test vector code signal generating unit includes X groups of coding subunits, which are sequentially connected to each other and are configured to sequentially output a test vector code signal pattern _ id according to an operation priority and according to a temporary intermediate value; and each group of coding subunits sequentially judges whether the bit number of the temporary storage intermediate value psel _ temp is valid or not, and outputs a corresponding test vector coding signal pattern _ id under the condition that the value of psel _ temp [ m ] is 1.
As the preferred implementation mode of the invention, the test vector code signal generating unit comprises a D flip-flop, 7 alternative two-way selectors, 4 OR gates, 5 AND gates and 5 NOT gates, the 7 two-way selectors are connected in sequence, the two-way selector with the highest priority is connected with the D end of the D trigger, the 5 AND gates and the 5 NOT gates form 5 NAND gates, the 5 alternative two-way selectors with lower priority are connected with the output ends of the 5 NAND gates, the output ends of the 4 OR gates are respectively connected with the input ends of the NAND gates of the 4 alternative two-way selectors with lower priority, the NAND gate and the OR gate both input a temporary storage intermediate value psel _ temp, the two-way selector with the highest priority receives a test enable signal bist _ en, and the Q end of the D trigger outputs a test vector coding signal pattern _ id.
As a preferred embodiment of the present invention, the test control circuit module controls the ascending order and the descending order of the addresses and the reading and writing of the memory.
As a preferred embodiment of the present invention, the bit width of the test vector selection signal pattern _ sel is X bits, and each bit width corresponds to a group of test vectors.
The invention discloses a memory built-in self-test method capable of realizing rapid test by utilizing the system, which comprises the following steps:
(1) inputting a test vector selection signal pattern _ sel;
(2) assigning the temporary storage intermediate value psel _ temp to be equal to the test vector selection signal pattern _ sel, setting the initial value of the test vector coding signal pattern _ id to be 0, and setting the initial value of the internal signal n to be 0;
(3) calculating pattern _ complete- (| psel _ temp), outputting pattern _ complete, judging whether the pattern _ complete is 1, if so, continuing the step (5); otherwise, continuing the step (4);
(4) testing the set of test vectors;
(4.1) outputting a complete all vector test signal pattern _ complete ═ 0;
(4.2) inputting a one-time algorithm completion signal fsm _ complete;
(4.3) judging whether the fsm _ complete signal of one time algorithm is equal to 1, if so, continuing to the step (4.6);
otherwise, continuing the step (4.4);
(4.4) judging whether the temporary storage intermediate value psel _ temp [ n ] is equal to 1, if so, continuing the step (4.5); otherwise, increasing the value of n by 1, and continuing the step (4.4);
(4.5) assigning the pattern _ id to be n +1, outputting the test vector coding signal pattern _ id at the moment, and continuing to the step (4.2);
(4.6) assigning psel _ temp [ n ] to be 0, wherein n is n +1, and continuing to the step (3) after the test of the group of test vectors is finished;
(5) the all vector test complete signal pattern _ complete is output as 1.
In the specific implementation manner of the invention, the invention provides a built-in self-test method of a memory, which can select one or more test vectors for effective and rapid test aiming at specific defects, shorten the test time and reduce the test cost.
The invention needs to provide an additional test vector selection signal pattern _ sel to select the required test vector for testing.
Taking a 2K × 32bit SRAM as an example, if a coupling fault between two adjacent memory cells is to be tested, pattern1 and pattern2 can be selected for testing; if the coupling fault between two memory cells spaced by 1 bit is to be tested, only pattern3 can be selected for testing; if the coupling fault between two memory cells spaced by 3 bits needs to be tested, only pattern4 can be selected for testing; if coupling faults between two memory cells spaced by 7 bits need to be tested, only pattern5 can be selected for testing; if coupling faults between two memory cells separated by 15 bits need to be tested, only pattern6 can be selected for testing; of course, if the coupling fault is to be completely tested, all patterns can be selected for testing. Compared with March C-algorithm, the test method can still cover the fix fault SAF, the conversion fault TF, the coupling fault CF and the address decoding fault AF, and the test time can be reduced to 1/6 of the traditional test time at most. The user only needs to freely select the test vector to test according to the requirements of the coverage fault and the test time.
As shown in fig. 2, the present invention adds a test vector selection circuit on the basis of the conventional MBIST circuit, and can select one or more test vectors for testing according to the requirement control signal pattern _ sel covering faults, so as to shorten the testing time and reduce the testing cost while achieving the testing purpose.
The bit width of the test vector selection signal pattern _ sel is X bits, each bit corresponds to a group of patterns, and the pattern _ sel [ n ] ═ 1 indicates that the (n + 1) th pattern test is selected, as follows:
pattern _ sel [0] ═ 1 indicates that the pattern1 test was selected,
pattern _ sel [1] ═ 1 indicates that the pattern2 test was selected,
pattern _ sel [2] ═ 1 indicates that the pattern3 test was selected,
pattern _ sel [4] ═ 1 indicates that the pattern4 test was selected,
by analogy, when all pattern tests are selected, each bit of pattern _ sel should be 1, i.e., pattern _ sel [ X-1:0] ═ X' b111 … 1.
The function of the test vector selection circuit is that a user selects a test vector to perform targeted and rapid test by controlling the test vector selection signal pattern _ sel according to the type of a fault which may occur, and the functional structure of the test vector selection circuit is shown in fig. 3.
The input signal of the test vector selection circuit comprises a test vector selection signal pattern _ sel and a one-time algorithm completion signal fsm _ complete, wherein the pattern _ sel is configured by a user, and the fsm _ complete is an internal signal and is generated when the test control circuit executes one-time algorithm;
the output signal of the test vector selection circuit has a test vector encoding signal pattern _ id and an all vector test completion signal pattern _ complete, the pattern _ id is sent to the test vector generation circuit for generating a test vector signal bist _ pattern, and the pattern _ complete is sent to the response analysis circuit for generating a test completion signal bist _ done.
Taking a 2K × 32bit SRAM as an example, the corresponding relationship between the test vector bist _ pattern and the test vector code pattern _ id is shown in fig. 3, and when the pattern _ id is 3' b001, the bist _ pattern selects pattern 1; when pattern _ id is 3' b010, the bist _ pattern selects pattern 2; when the pattern _ id is 3' b011, the bist _ pattern selects pattern 3; when pattern _ id is 3' b100, the bist _ pattern selects pattern 4; when pattern _ id is 3' b101, the bist _ pattern selects pattern 5; when pattern _ id is 3' b110, the bist _ pattern selects pattern 6.
The specific structure of the test vector selection circuit is related to the bit width of the test memory, and the structure of the test vector selection circuit is discussed in detail below by taking a 2K × 32bit SRAM as an example.
The main circuit structure of the pattern _ sel register module is shown in fig. 4, and includes 6D flip-flops, 5 and gates and 5 not gates.
The 6D flip-flops are respectively numbered as DFF 0-DFF 5, and the operation priority is DFF0> DFF1> DFF2> DFF3> DFF4> DFF 5. When the MBIST circuit starts to work, the D end of the D trigger is given to a psel _ temp initial value psel _ temp [5:0] ═ pattern _ sel [5:0 ];
then when the first pattern test is completed, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [0] of the D flip-flop DFF0 is 0, and the output values of the DFFs 1 to 5 are still their initial values psel _ temp [5:1] ═ pattern _ sel [5:1 ];
when the second pattern test is completed, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [1] of the D flip-flop DFF1 is 0, and the output values of the DFFs 2 to 5 are still the initial values psel _ temp [5:2] ═ pattern _ sel [5:2 ];
when the third set of patterns is tested, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [2] of the D flip-flop DFF0 is 0, and the output values of the DFFs 3 to 5 are still the initial values psel _ temp [5:3] ═ patterns _ sel [5:3 ];
when the fourth group of patterns is tested, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [3] of the D flip-flop DFF3 is 0, and the output values of the DFFs 4 to 5 are still the initial values psel _ temp [5:4] ═ patterns _ sel [5:4 ];
when the fifth pattern test is completed, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [4] of the D flip-flop DFF4 is 0, and the output value of the DFF5 is still the initial value psel _ temp [5] — pattern _ sel [5 ];
when the sixth pattern test is completed, the test algorithm completion signal fsm _ complete is 1, the output psel _ temp [5] of the D flip-flop DFF5 is 0, and the psel _ temp [5:0] is 6' b000000, so that the entire vector test is completed.
The main circuit structure of the pattern _ id generation module is shown in fig. 5, and is composed of 1D flip-flop, 7 one-out-of-two selectors, 4 or gates, 5 and gates, and 5 not gates.
The 7 two-way selectors are respectively numbered as MUX 0-MUX 6, and the operation priorities are MUX0> MUX1> MUX2> MUX3> MUX4> MUX5> MUX 6.
When the test is not started, bist _ en is equal to 0, pattern _ id is a default value of 3 ' b000, when the test is started, bist _ en is equal to 1, the selector MUX1 preferentially operates to judge whether psel _ temp [0] is valid (high-valid), and if psel _ temp [0] is equal to 1, 3 ' b001 is selected to be output, namely, pattern _ id is equal to 3 ' b 001;
if psel _ temp [0] is 0, the selector MUX2 begins operation. When the selector MUX2 operates, it determines whether psel _ temp [1] is valid, and if psel _ temp [1] is equal to 1, it selects 3 'b 010 to output, that is, pattern _ id is equal to 3' b 010;
if psel _ temp [1] is 0, the selector MUX3 begins operation. When the selector MUX3 operates, it determines whether psel _ temp [2] is valid, and if psel _ temp [2] is equal to 1, it selects 3 'b 011 to output, that is, pattern _ id is equal to 3' b 011;
if psel _ temp [2] is 0, the selector MUX4 begins operation. When the selector MUX4 operates, it determines whether psel _ temp [3] is valid, and if psel _ temp [3] is equal to 1, it selects 3 'b 100 to output, i.e. pattern _ id is equal to 3' b 100;
if psel _ temp [3] is 0, the selector MUX5 begins operation. When the selector MUX5 operates, it determines whether psel _ temp [4] is valid, and if psel _ temp [4] is equal to 1, it selects 3 'b 101 for output, i.e. pattern _ id is equal to 3' b 101;
if psel _ temp [4] is 0, the selector MUX6 begins operation. When the selector MUX6 operates, it determines whether psel _ temp [5] is valid, and if psel _ temp [5] is equal to 1, it selects 3 'b 110 to output, i.e. pattern _ id is equal to 3' b 110;
if psel _ temp [5] is 0, it indicates that the entire vector test is complete.
The NOR operation unit is used for performing OR and inversion on each phase of the signal psel _ temp [5:0], and consists of 5 OR gates and 1 NOT gate.
The overall operation flow of the test vector selection circuit is shown in fig. 6, and a 2K × 32bit SRAM will be described as an example. The test vectors of the 2K × 32bit SRAM have 6 sets, and assuming that the user needs all the test vectors to perform the test, the input signal pattern _ sel is 6' b 111111. The input signal fsm _ complete is changed in real time, and becomes effective (high effective) when the test control circuit executes the algorithm once, the effective time is only one clk period, the time becomes ineffective automatically after one clk period, then the test control circuit is effective when the next algorithm is executed, a plurality of clk periods actually pass from ineffective to effective, the time from ineffective to effective is assumed to be only one clk period for simplifying the flow, and the input of fsm _ complete is 0, 1, 0, 1, 0, 1, 0, 1 in sequence.
The process is as follows:
(1) inputting a test vector selection signal pattern _ sel ═ 6' b111111 to step (2);
(2) assigning psel _ temp ═ pattern _ sel ═ 6 'b 111111, n ═ 0, pattern _ id ═ 3' b00 to step (3);
(3) calculating pattern _ complete — (| psel _ temp) — 0, to step (3.1);
(3.1) outputting pattern _ complete to the step (3.2);
(3.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (3.3);
(3.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (3.4);
(3.4) judging whether fsm _ complete is equal to 1, if so, going to the step (3.10); if not, go to step (3.5);
(3.5) judging whether psel _ temp [0] is equal to 1, if yes, going to step (3.6); otherwise, increasing the value of n by 1, and continuing the step (3.5);
(3.6) calculating pattern _ id ═ n +1 ═ 1 (3' b001), to step (3.7);
(3.7) outputting pattern _ id to the step (3.8);
(3.8) inputting an algorithm completion signal fsm _ complete ═ 1 once to step (3.9);
(3.9) determining whether fsm _ complete is equal to 1, yes, go to step (3.10); if not, go to step (3.5);
(3.10) calculating psel _ temp [0] to be 0 and n to be 1, wherein the 1 st group of pattern is tested, and going to the step (4);
(4) calculating pattern _ complete — (| psel _ temp) — 0, to step (4.1);
(4.1) outputting pattern _ complete to the step (4.2);
(4.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (4.3);
(4.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (4.4);
(4.4) judging whether fsm _ complete is equal to 1, if so, going to the step (4.10); if not, go to step (4.5);
(4.5) judging whether psel _ temp [1] is equal to 1, if yes, going to step (4.6); otherwise, increasing the value of n by 1, and continuing the step (4.5);
(4.6) calculating pattern _ id ═ n +1 ═ 2 (3' b010), to step (4.7);
(4.7) outputting pattern _ id to the step (4.8);
(4.8) inputting the algorithm completion signal fsm _ complete to 1 once, and going to step (4.9);
(4.9) determining whether fsm _ complete is equal to 1, yes, go to step (4.10); if not, go to step (4.5);
(4.10) calculating psel _ temp [1] to be 0 and n to be 2, wherein the 2 nd group of pattern is tested, and going to the step (5);
(5) calculating pattern _ complete — (| psel _ temp) — 0, to step (5.1);
(5.1) outputting pattern _ complete to the step (5.2);
(5.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (5.3);
(5.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (5.4);
(5.4) judging whether fsm _ complete is equal to 1, if so, going to the step (5.10); if not, go to step (5.5);
(5.5) judging whether psel _ temp [2] is equal to 1, if yes, going to step (5.6); otherwise, increasing the value of n by 1, and continuing the step (5.5);
(5.6) calculating pattern _ id ═ n +1 ═ 3 (3' b011), to step (5.7);
(5.7) outputting pattern _ id to the step (5.8);
(5.8) inputting the algorithm completion signal fsm _ complete to 1 once, and going to step (5.9);
(5.9) determining whether fsm _ complete is equal to 1, yes, go to step (5.10); if not, go to step (5.5);
(5.10) calculating psel _ temp [2] to be 0 and n to be 3, wherein the 3 rd group pattern is tested, and going to the step (6);
(6) calculating pattern _ complete — (| psel _ temp) — 0, to step (6.1);
(6.1) outputting pattern _ complete to the step (6.2);
(6.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (6.3);
(6.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (6.4);
(6.4) judging whether fsm _ complete is equal to 1, if so, going to step (6.10); if not, go to step (6.5);
(6.5) judging whether psel _ temp [3] is equal to 1, if yes, going to step (6.6); otherwise, increasing the value of n by 1, and continuing the step (6.5);
(6.6) calculating pattern _ id 4 (3' b100), to step (6.7);
(6.7) outputting pattern _ id to the step (6.8);
(6.8) inputting the algorithm completion signal fsm _ complete to 1 once, and going to step (6.9);
(6.9) determining whether fsm _ complete is equal to 1, yes, go to step (6.10); if not, go to step (6.5);
(6.10) calculating psel _ temp [3] to be 0 and n to be 4, wherein the 4 th group of pattern is tested, and going to the step (7);
(7) calculating pattern _ complete — (| psel _ temp) — 0, to step (7.1);
(7.1) outputting pattern _ complete to step (7.2);
(7.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (7.3);
(7.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (7.4);
(7.4) judging whether fsm _ complete is equal to 1, if so, going to step (7.10); if not, go to step (7.5);
(7.5) judging whether psel _ temp [4] is equal to 1, if yes, going to step (7.6); otherwise, increasing the value of n by 1, and continuing to the step (7.5);
(7.6) calculating pattern _ id-5 (3' b101), to step (7.7);
(7.7) outputting pattern _ id to the step (7.8);
(7.8) inputting the algorithm completion signal fsm _ complete to 1 once, and going to step (7.9);
(7.9) determining whether fsm _ complete is equal to 1, yes, go to step (7.10); if not, go to step (7.5);
(7.10) calculating psel _ temp [4] to be 0 and n to be 5, wherein the 5 th group of pattern is tested, and going to the step (8);
(8) calculating pattern _ complete — (| psel _ temp) — 0, to step (8.1);
(8.1) outputting pattern _ complete to step (8.2);
(8.2) judging whether the pattern _ complete is equal to 1, if so, ending the step; if not, go to step (8.3);
(8.3) inputting the algorithm completion signal fsm _ complete to 0 once, and going to step (8.4);
(8.4) judging whether fsm _ complete is equal to 1, if so, going to the step (8.10); if not, go to step (8.5);
(8.5) judging whether psel _ temp [5] is equal to 1, if yes, going to step (8.6); otherwise, increasing the value of n by 1, and continuing to the step (8.5);
(8.6) calculating pattern _ id 6 (3' b110), to step (8.7);
(8.7) outputting pattern _ id to the step (8.8);
(8.8) inputting the algorithm completion signal fsm _ complete to 1 once, and going to step (8.9);
(8.9) determining whether fsm _ complete is equal to 1, yes, go to step (8.10); if not, go to step (8.5);
(8.10) calculating psel _ temp [5] to be 0 and n to be 6, wherein the 6 th pattern is tested, and going to the step (9);
(9) calculating pattern _ complete — (| psel _ temp) — (1), and going to step (10);
(10) outputting pattern _ complete to the step (11);
(11) and judging whether the pattern _ complete is equal to 1, if so, ending.
In the above flow, the changes and the corresponding relationships of the signals pattern _ sel, psel _ temp, pattern _ id, and bist _ pattern are shown in table 1:
TABLE 1 mapping relationship of signals pattern _ sel, psel _ temp, pattern _ id, bist _ pattern
The memory built-in self-test system and the method for realizing the rapid test are also applicable to other memories and algorithms, one or more different test vectors can be selected according to specific memory faults, different test vectors can be selected according to different memory faults, and the memory built-in self-test system and the method are applicable to different memories and algorithms. The invention can select the test vector according to the memory fault, and has short test time, low test cost and wider application range.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (11)
1. A memory built-in self-test system for enabling fast testing, said system comprising:
the test control circuit module receives an external test enable signal bist _ en, and the output end of the test control circuit module is respectively connected with the test vector selection circuit module and the circuit to be tested and used for controlling the operation of the test circuit;
the test vector selection circuit module receives the test vector selection signal pattern _ sel, and the receiving end is connected with the output end of the test control circuit module and is used for selecting one or more test vectors to test according to the test vector selection signal pattern _ sel;
the receiving end of the test vector generating circuit module is connected with the output end of the test vector selecting circuit module, and the output end of the test vector generating circuit module is connected with the circuit to be tested and used for generating test vectors;
and the input end of the response analysis circuit module is connected with the test vector selection circuit module and the circuit to be tested, and is used for comparing the numerical value read from the memory with the test vector and outputting a test completion signal bist _ done and a test success signal bist _ ok.
2. The system of claim 1, wherein the test vector selection circuit module comprises:
the test vector selection signal temporary storage unit is connected with the test control circuit module, receives a test vector selection signal pattern _ sel configured by a user and a primary algorithm completion signal fsm _ complete output by the test control circuit module, and outputs a temporary storage intermediate value psel _ temp;
the receiving end of the test vector coding signal generating unit is connected with the test vector selection signal temporary storage unit, the output end of the test vector coding signal generating unit is connected with the test vector generating circuit module, and the test vector selection signal pattern _ sel configured by a user is received; the test vector encoded signal pattern _ id is output for generating the test vector signal bist _ pattern.
3. The system of claim 2, wherein the test vector selection circuit module further comprises:
and the receiving end of the NOR operation unit is connected with the test vector selection signal temporary storage unit, the output end of the NOR operation unit is connected with the response analysis circuit module, and the NOR operation unit outputs a complete vector test signal pattern _ complete which is used for generating a complete test signal bist _ done.
4. The system of claim 2, wherein the temporary storage unit for the test vector selection signal comprises X groups of output subunits, and the X groups of output subunits are sequentially connected to sequentially test the test vectors according to the operation priority; each group of output subunits sequentially corresponds to the bits of the temporary storage intermediate value psel _ temp, and under the condition that the test of the nth output subunit is finished, the value of the output psel _ temp [ n-1] is 0, wherein n is more than or equal to 1 and less than or equal to X.
5. The system of claim 2, wherein the temporary test vector selection signal storage unit comprises 6D flip-flops, 5 and gates and 5 not gates, the D terminals of the 6D flip-flops receive the test vector selection signal pattern _ sel, the clock terminals thereof are connected to the same clock signal, the Q terminals thereof output the temporary storage intermediate value psel _ temp, the 5 and 5 not gates constitute 5 nand gates, and the 6D flip-flops are connected to each other through the 5 nand gates.
6. The system of claim 2, wherein the test vector code signal generating unit comprises X groups of coding subunits, and the X groups of coding subunits are sequentially connected to sequentially output a test vector code signal pattern _ id according to the operation priority and the temporary intermediate value; and each group of coding subunits sequentially judges whether the bit number of the temporary storage intermediate value psel _ temp is valid or not, and outputs a corresponding test vector coding signal pattern _ id under the condition that the value of psel _ temp [ m ] is 1.
7. The system of claim 2, wherein the test vector code signal generating unit comprises a D flip-flop, 7 one-out-two selectors, 4 OR gates, 5 AND gates and 5 NOT gates, the 7 one-out-two selectors are sequentially connected, the one-out-two selector with the highest priority is connected to the D end of the D flip-flop, the 5 AND gates and the 5 NOT gates form 5 NAND gates, the 5 one-out-two selectors with lower priorities are connected to the output ends of the 5 NAND gates, the output ends of the 4 OR gates are respectively connected to the input ends of the NAND gates of the 4 one-out-two selectors with lower priorities, the NAND gates input the mp temporary storage middle value psel _ teand the MP, the one-out-two selector with the highest priority receives the test enable signal bist _ en, and the Q end of the D trigger outputs a test vector coding signal pattern _ id.
8. The system as claimed in claim 1, wherein the test control circuit module controls the ascending and descending order of the addresses and the reading and writing of the memory.
9. The system of claim 1, wherein the bit width of the test vector select signal pattern _ sel is X bits, and each bit width corresponds to a set of test vectors.
10. A method for implementing a fast testable memory built-in self-test using the system of claim 1, the method comprising the steps of:
(1) inputting a test vector selection signal pattern _ sel;
(2) assigning the temporary storage intermediate value psel _ temp to be equal to the test vector selection signal pattern _ sel, setting the initial value of the test vector coding signal pattern _ id to be 0, and setting the initial value of the internal signal n to be 0;
(3) calculating pattern _ complete- (| psel _ temp), outputting pattern _ complete, judging whether the pattern _ complete is 1, if so, continuing the step (5); otherwise, continuing the step (4);
(4) testing the set of test vectors;
(5) the all vector test complete signal pattern _ complete is output as 1.
11. The method as claimed in claim 10, wherein the step (4) comprises the following steps:
(4.1) outputting a complete all vector test signal pattern _ complete ═ 0;
(4.2) inputting a one-time algorithm completion signal fsm _ complete;
(4.3) judging whether the fsm _ complete signal of one time algorithm is equal to 1, if so, continuing to the step (4.6); otherwise, continuing the step (4.4);
(4.4) judging whether the temporary storage intermediate value psel _ temp [ n ] is equal to 1, if so, continuing the step (4.5); otherwise, increasing the value of n by 1, and continuing the step (4.4);
(4.5) assigning the pattern _ id to be n +1, outputting the test vector coding signal pattern _ id at the moment, and continuing to the step (4.2);
(4.6) assigning psel _ temp [ n ] to 0, n being n +1, and continuing to step (3) after the test of the group of test vectors is finished.
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