CN207541950U - A kind of configurable memory built in self test of sram circuit - Google Patents
A kind of configurable memory built in self test of sram circuit Download PDFInfo
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- CN207541950U CN207541950U CN201721684705.5U CN201721684705U CN207541950U CN 207541950 U CN207541950 U CN 207541950U CN 201721684705 U CN201721684705 U CN 201721684705U CN 207541950 U CN207541950 U CN 207541950U
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Abstract
The utility model belongs to field of computer technology, a kind of configurable memory built in self test of sram circuit is provided, includes configuration and starting module 1, overtime detection module 2, control module 3, control signal buffer module 4, test vector generation module 5, response analysis module 8.The utility model carries out configurability design by number, caching depth to tested CPU core etc., can be suitble to the cpu cache of different model.Configurable time-out error is provided and comparing result mistake output interface, test process controllability are strong.Pass through quick test pattern, it is possible to reduce the testing time.By overtime testing mechanism, test invalidation when institute's survey memory is unresponsive can be solved the problem of.
Description
Technical field
The invention belongs to field of computer technology, are related to a kind of configurable memory built in self test of sram circuit.
Background technology
Memory built in self test of sram circuit is that circuit, sequence circuit, pattern choosing occur for implantation resolution chart in memory
Circuit and debugging test circuit are selected, so as to carry out selftest.When surveyed memory is unresponsive, test result is invalid.
Traditional way is to directly give test result mistake, causes testing reliability poor.It not can configure in test process,
Poor controllability.
Invention content
Goal of the invention：
The main object of the present invention is to provide a kind of configurable memory built in self test of sram circuit, is in-line memory
Test a kind of configurable built-in self-test circuit of overtime testing mechanism is provided, the test for memory provides a kind of spirit
Living, reliable solution, the exploitation for similar product provides guidance.
Technical solution：
A kind of configurable memory built in self test of sram circuit includes configuration and starting module 1, overtime detection module 2, control
Molding block 3, control signal buffer module 4, test vector generation module 5, response analysis module 8；
Configuration and starting module 1 are connected with control module 3 and external memory to be measured, receive and opened from external MBIST
The Ack signals of dynamic signal and memory to be measured export configuration information and test starting signal to control module 3；
Overtime detection module 2 is connected with external memory to be measured；By detecting from external MBIST enabling signals and
The Ack signals of memory to be measured, output overtime error signal to outside；
Control module 3 is connected with configuration with starting module 1, control signal buffer module 4 and test vector generation module 5；
Input is to come the configuration information of self-configuring and starting module 1 and test starting signal and the survey from test vector generation module 5
Try progress information；Test starting signal is used for the initialization of state machine, passes through the shape of test process acquisition of information current state machine
State according to configuration information, generates the state machine state of following clock cycle, generates corresponding control signal, is output to control letter
Number buffer module 4；
Control signal buffer module 4 is connected with control module 3 and test vector generation module 5；It inputs as from control mould
The control signal of block 3 after caching a clock cycle, is output to test vector generation module 5；
Test vector generation module 5 is connected with control module 3, control signal buffer module 4 and external memory to be measured；It is defeated
Enter from the control signal for controlling signal buffer module 4, to generate test process information, being output to control module 3；Generate test
Vector, to external memory to be measured；
Response analysis module 8 is connected with test vector generation module 5 and external memory to be measured；Input be come self-test to
Measure the test vector of generation module 5 and the reading data from external memory to be measured；Compared by comparing the two as a result, generating
Consequential signal is output to outside.
Test vector generation module 5 includes：To production units 6, quick test vector generate unit 7,
Control signal control MUX from control signal buffer module 4 select to production units 6 or it is quick test to
Production units 7 generate test process information to external memory to be measured；Wherein, to production units 6 generate common test into
Journey information, quick test vector generate unit 7 and generate quick test process information.
Advantageous effect：
A kind of configurable memory built in self test of sram circuit provided by the invention, by number to tested CPU core,
It caches depth etc. and carries out configurability design, the cpu cache of different model can be suitble to.Configurable time-out error and comparison are provided
As a result wrong output interface, test process controllability are strong.Pass through quick test pattern, it is possible to reduce the testing time.Pass through time-out
Testing mechanism can solve the problem of test invalidation when institute's survey memory is unresponsive.
Description of the drawings
Fig. 1 is a kind of configuration diagram of configurable memory built in self test of sram circuit of the present invention.
Specific embodiment
The present invention is described further with reference to the accompanying drawings and examples：
As shown in Figure 1, a kind of configurable memory built in self test of sram circuit, is examined comprising configuration and starting module 1, time-out
Survey module 2, control module 3, control signal buffer module 4, test vector generation module 5, to production units 6, quick test
To production units 7, response analysis module 8.
Configuration is connected with starting module 1 with control module 3 and external memory to be measured.It receives and is opened from external MBIST
The Ack signals of dynamic signal and memory to be measured.According to actual demand, corresponding configuration information is generated by different macrodefinitions,
When the Ack signals of external MBIST enabling signals and memory to be measured are effective, test starting signal is generated.Output configuration
Information and test starting signal are to control module 3.
Overtime detection module 2 is connected with external memory to be measured.It inputs as from external MBIST enabling signals and to be measured
The Ack signals of memory.Detected by a configurable counter external MBIST enabling signals it is effective after, waiting is treated
The time of the Ack signals of memory is surveyed, generates time-out error signal.Output overtime error signal to outside.
Control module 3 is connected with configuration with starting module 1, control signal buffer module 4 and test vector generation module 5.
Input is to come the configuration information of self-configuring and starting module 1 and test starting signal and the survey from test vector generation module 5
Try progress information.Corresponding control signal is generated, is output to control signal buffer module 4.
Control signal buffer module 4 is connected with control module 3 and test vector generation module 5.It inputs as from control mould
The control signal of block 3.After caching a clock cycle, it is output to test vector generation module 5.
Test vector generation module 5 is connected with control module 3, control signal buffer module 4 and external memory to be measured.It is defeated
Enter for the control signal from control signal buffer module 4.Test process information is generated, is output to control module 3, generates test
Vector, to external memory to be measured.
Test vector generation module 5 includes：To production units 6, quick test vector generate unit 7,
Control signal control MUX from control signal buffer module 4 select to production units 6 or it is quick test to
Production units 7 generate test process information to external memory to be measured；Wherein, to production units 6 generate common test into
Journey information, quick test vector generate unit 7 and generate quick test process information.
Two sets of test vectors that unit 7 is test vector generation module 5 are generated to production units 6 and quick test vector
Generation circuit.Wherein quick test vector generates the generation that unit 7 quickly carries out test vector by way of to address shift.
Response analysis module 8 is connected with test vector generation module 5 and external memory to be measured.Input be come self-test to
Measure the test vector of generation module 5 and the reading data from external memory to be measured.Compared by comparing the two as a result, generating
Consequential signal is output to outside.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is explained in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic；
And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (2)
1. a kind of configurable memory built in self test of sram circuit, it is characterised in that：Include configuration and starting module (1), time-out
Detection module (2), control module (3), control signal buffer module (4), test vector generation module (5), response analysis module
(8)；
Configuration and starting module (1) are connected with control module (3) and external memory to be measured, receive and opened from external MBIST
The Ack signals of dynamic signal and memory to be measured export configuration information and test starting signal to control module (3)；
Overtime detection module (2) is connected with external memory to be measured；By detecting from external MBIST enabling signals and treating
Survey the Ack signals of memory, output overtime error signal to outside；
Control module (3), with configuration and starting module (1), control signal buffer module (4) and test vector generation module (5)
It is connected；Input be come self-configuring and starting module (1) configuration information and test starting signal and from test vector generate mould
The test process information of block (5)；Test starting signal is used for the initialization of state machine, passes through the current shape of test process acquisition of information
The state of state machine according to configuration information, generates the state machine state of following clock cycle, generates corresponding control signal, output
To control signal buffer module (4)；
Control signal buffer module (4) is connected with control module (3) and test vector generation module (5)；It inputs as from control
The control signal of module (3) after caching a clock cycle, is output to test vector generation module (5)；
Test vector generation module (5) is connected with control module (3), control signal buffer module (4) and external memory to be measured；
It inputs from the control signal for controlling signal buffer module (4), to generate test process information, being output to control module (3)；Production
Raw test vector, to external memory to be measured；
Response analysis module (8) is connected with test vector generation module (5) and external memory to be measured；Input be come self-test to
Measure the test vector of generation module (5) and the reading data from external memory to be measured；By comparing the two as a result, generating ratio
Compared with consequential signal, it is output to outside.
2. a kind of configurable memory built in self test of sram circuit as described in claim 1, it is characterised in that：
Test vector generation module (5) includes：To production units (6), quick test vector generate unit (7),
Control signal control MUX from control signal buffer module (4) select to production units (6) or it is quick test to
Production units (7) generate test process information to external memory to be measured；Wherein, common survey is generated to production units (6)
Progress information is tried, quick test vector generates unit (7) and generates quick test process information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721684705.5U CN207541950U (en) | 2017-12-06 | 2017-12-06 | A kind of configurable memory built in self test of sram circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721684705.5U CN207541950U (en) | 2017-12-06 | 2017-12-06 | A kind of configurable memory built in self test of sram circuit |
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| CN207541950U true CN207541950U (en) | 2018-06-26 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021179603A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Method for testing control chip and related device |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
| US11867758B2 (en) | 2020-03-11 | 2024-01-09 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
-
2017
- 2017-12-06 CN CN201721684705.5U patent/CN207541950U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021179603A1 (en) * | 2020-03-11 | 2021-09-16 | 长鑫存储技术有限公司 | Method for testing control chip and related device |
| US11862268B2 (en) | 2020-03-11 | 2024-01-02 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
| US11867758B2 (en) | 2020-03-11 | 2024-01-09 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
| CN115691632B (en) * | 2022-10-19 | 2023-07-07 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221010 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 710000 No. 15, Jinye Second Road, Xi'an, Shaanxi Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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| TR01 | Transfer of patent right |