CN109254883B - Debugging device and method for on-chip memory - Google Patents
Debugging device and method for on-chip memory Download PDFInfo
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- CN109254883B CN109254883B CN201710575820.7A CN201710575820A CN109254883B CN 109254883 B CN109254883 B CN 109254883B CN 201710575820 A CN201710575820 A CN 201710575820A CN 109254883 B CN109254883 B CN 109254883B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
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- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
Abstract
The invention discloses a debugging device and a debugging method of an on-chip memory, which comprise an input control unit, a register unit, a control unit and a decoding unit, wherein the input control unit is used for receiving and analyzing externally input debugging control information and storing the analyzed debugging control information to the register unit; the control unit is used for acquiring the analyzed debugging control information from the register unit, generating a corresponding debugging read-write signal and outputting the corresponding debugging read-write signal to the decoding unit; the decoding unit is used for receiving the debugging read-write signal from the control unit and the read-write signal input from the outside and carrying out corresponding read-write operation. The invention generates the debugging read-write signal according to the debugging control information, and carries out corresponding read-write operation according to the debugging read-write signal and the read-write signal input from the outside, thereby realizing flexible access to the on-chip memory, meeting the requirements of application on data analysis and correction of data according to the analysis result, and better supporting flexible debugging of the system.
Description
Technical Field
The invention relates to the technical field of System On a Chip (SOC) design of integrated circuits, in particular to a debugging device and method of an On-Chip memory.
Background
In recent years, with the continuous development of large-scale and ultra-large-scale integrated circuits, embedded systems are widely used due to the characteristics of high integration level, high operation speed, low power consumption, good reliability and the like. The advantages of using on-chip memory are apparent for embedded applications to achieve optimal performance, due to the greater data access capability and lower access power consumption of on-chip memory over off-chip memory.
However, this is accompanied by the problem of debugging (Debug) of on-chip memory. Applications often need to read data from a specific area or all areas of on-chip memory for debugging and to implement corrections for error scenarios. The traditional debugging method tends to set breakpoints and save pointer information of the breakpoints, and the method can only locate the error position and cannot read and write. Some improved debugging methods can read data of an on-chip memory, but cannot meet the requirements of applications on data analysis and operation, cannot correct data according to an obtained result, and therefore cannot better support flexible debugging of a system.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides an on-chip memory debugging apparatus and method, which can flexibly access an on-chip memory.
In order to achieve the purpose of the invention, the technical scheme of the embodiment of the invention is realized as follows:
the embodiment of the invention provides a debugging device of an on-chip memory, which comprises an input control unit, a register unit, a control unit and a decoding unit, wherein:
the input control unit is used for receiving and analyzing externally input debugging control information and storing the analyzed debugging control information to the register unit;
the register unit is used for storing the analyzed debugging control information;
the control unit is used for acquiring the analyzed debugging control information from the register unit, generating a corresponding debugging read-write signal and outputting the corresponding debugging read-write signal to the decoding unit;
and the decoding unit is used for receiving the debugging read-write signal from the control unit and the read-write signal input from the outside and carrying out corresponding read-write operation according to the debugging read-write signal and the read-write signal input from the outside.
Further, the debugging control information includes a debugging enable state, a read-write mode, an on-chip memory, and a read-write address.
Further, the control unit includes: a state control unit, a read control unit and a write control unit, wherein:
the state control unit is used for acquiring the debugging enabling state and the read-write mode, enabling or closing the read control unit or the write control unit, and outputting the on-chip memory and the read-write address to the read control unit when the read control unit is enabled; when the write control unit is enabled, outputting the on-chip memory and the read-write address to the write control unit;
the read control unit is used for generating a corresponding debugging read signal according to the on-chip memory and the read-write address and outputting the debugging read signal to the decoding unit;
and the write control unit is used for generating a corresponding debugging write signal according to the on-chip memory and the read-write address and outputting the debugging write signal to the decoding unit.
Further, still include time statistics unit, wherein:
the decoding unit is also used for generating a read-write completion identifier and outputting the read-write completion identifier to the control unit;
the time counting unit is used for recording the time of the control unit for performing the read-write operation or the time of the input control unit for analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write errors or analysis error information to the register unit;
the register unit is also used for storing the read-write error or the analysis error information.
Further, the externally input debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
Further, when the on-chip memory is located inside the CPU, the control unit is further configured to:
detecting the storage state of an internal register of the CPU, and generating the corresponding debugging read-write signal when the storage state of the internal register of the CPU is empty;
when the on-chip memory is located inside a second level cache, the control unit is further to:
and detecting the storage state of the internal register of the second-level cache, and generating the corresponding debugging read-write signal when the storage state of the internal register of the second-level cache is empty.
The embodiment of the invention also provides a debugging method of the on-chip memory, which comprises the following steps:
receiving and analyzing externally input debugging control information, and storing the analyzed debugging control information to a register;
acquiring the analyzed debugging control information from a register to generate a corresponding debugging read-write signal;
and performing corresponding read-write operation according to the debugging read-write signal and an externally input read-write signal.
Further, the debugging control information includes a debugging enable state, a read-write mode, an on-chip memory, and a read-write address.
Further, the method further comprises:
and recording the time of the read-write operation or the time of analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write error or analysis error information into a register.
Further, the externally input debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
The technical scheme of the invention has the following beneficial effects:
the debugging device and the debugging method of the on-chip memory provided by the invention generate the debugging read-write signal according to the debugging control information and carry out corresponding read-write operation according to the debugging read-write signal and the read-write signal input from the outside, thereby realizing flexible access to the on-chip memory, meeting the requirements of application on data analysis and correction of data according to the analysis result, and better supporting flexible debugging of the system.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a diagram illustrating a debugging apparatus of an on-chip memory according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating a debugging apparatus of an on-chip memory according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for debugging an on-chip memory according to an embodiment of the invention;
FIG. 4 is a diagram of the overall architecture of the debugging scheme of the on-chip memory in the system according to the preferred embodiment of the present invention;
FIG. 5 is an overall block diagram of the first-level debug circuit of the present invention in a Central Processing Unit (CPU);
FIG. 6 is a schematic diagram of the implementation unit division of the first-level debug circuit of the present invention;
FIG. 7 is a flow chart illustrating the execution of the first level debug circuitry of the present invention;
FIG. 8 is an overall block diagram of the second level debug circuitry of the present invention in a second level Cache (L2 Cache);
FIG. 9 is a schematic diagram of the implementation unit division of the two-level debug circuitry of the present invention;
FIG. 10 is a flow chart illustrating the execution of the two-stage debug circuitry of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
As shown in fig. 1, a debugging apparatus of an on-chip memory according to the present invention includes an input control unit, a register unit, a control unit, and a decoding unit, wherein:
the input control unit is used for receiving and analyzing externally input debugging control information and storing the analyzed debugging control information to the register unit;
the register unit is used for storing the analyzed debugging control information;
the control unit is used for acquiring the analyzed debugging control information from the register unit, generating a corresponding debugging read-write signal and outputting the corresponding debugging read-write signal to the decoding unit;
and the decoding unit is used for receiving the debugging read-write signal from the control unit and the read-write signal input from the outside and carrying out corresponding read-write operation according to the debugging read-write signal and the read-write signal input from the outside.
It should be noted that, when the debugging read-write signal is true (that is, when the input control unit receives the debugging control information and the control unit generates the debugging read-write signal and outputs the debugging read-write signal to the decoding unit), the decoding unit of the present invention performs corresponding read-write operation according to the debugging read-write signal; when the debugging read-write signal is false (that is, when the input control unit does not receive the debugging control information and the control unit does not generate the debugging read-write signal), the decoding unit of the invention performs corresponding read-write operation according to the read-write signal input from the outside.
Furthermore, the debugging device of the on-chip memory further comprises a clock unit, and the clock unit is used for providing clock signals for all units of the debugging device of the on-chip memory.
Further, the debugging control information includes a debugging enable state, a read-write mode, an on-chip memory, and a read-write address.
Further, the debugging control information further comprises a reset instruction;
the control unit is further configured to obtain the reset instruction from the register unit, and perform a reset operation on the debugging apparatus.
In an embodiment of the present invention, the on-chip Memory includes, but is not limited to, Tightly Coupled Memory (TCM), Random Access Memory (RAM) for a first level instruction cache, data RAM for a first level instruction cache, index address RAM for a first level data cache, data RAM for a first level data cache, index address RAM for a second level cache, and data RAM for a second level cache.
In an embodiment of the present invention, the read/write modes include a read mode, a write mode, an address area mode and an address self-increment mode, where the address area mode is used to read a part of data of the on-chip memory, and the address self-increment mode is used to read all data of the on-chip memory.
In an embodiment of the present invention, the read/write address includes a read/write start address and a read/write access area size.
Further, the control unit specifically includes a state control unit, a read control unit, and a write control unit, wherein:
the state control unit is used for acquiring the debugging enabling state and the read-write mode, enabling or closing a clock signal of the read control unit or the write control unit, and outputting the on-chip memory and the read-write address to the read control unit when the clock signal of the read control unit is enabled; when a clock signal of a write control unit is enabled, outputting the on-chip memory and the read-write address to the write control unit;
the read control unit is used for generating a corresponding debugging read signal according to the on-chip memory and the read-write address and outputting the debugging read signal to the decoding unit;
and the write control unit is used for generating a corresponding debugging write signal according to the on-chip memory and the read-write address and outputting the debugging write signal to the decoding unit.
Furthermore, the write control unit is further configured to generate a consistency feedback identifier and store the consistency feedback identifier in the register unit;
the register unit is further configured to store the consistency feedback identification.
Further, as shown in fig. 2, the debugging apparatus further includes a time counting unit, wherein:
the decoding unit is also used for generating a read-write completion identifier and outputting the read-write completion identifier to the control unit;
the time counting unit is used for recording the time of the control unit for performing the read-write operation or the time of the input control unit for analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write errors or analysis error information to the register unit;
the register unit is also used for storing the read-write error or the analysis error information.
Further, the externally input debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
Further, the Bus is an Advanced eXtensible Interface (AXI) Bus or an Advanced Peripheral Bus (APB).
Further, when the on-chip memory is located inside the CPU, the control unit is further configured to:
detecting the storage state of an internal register of the CPU, and generating the corresponding debugging read-write signal when the storage state of the internal register of the CPU is empty;
when the on-chip memory is located inside a second level cache, the control unit is further to:
and detecting the storage state of the internal register of the second-level cache, and generating the corresponding debugging read-write signal when the storage state of the internal register of the second-level cache is empty.
As shown in fig. 3, a method for debugging an on-chip memory according to the present invention includes:
step 301: receiving and analyzing externally input debugging control information, and storing the analyzed debugging control information to a register;
further, the debugging control information includes a debugging enable state, a read-write mode, an on-chip memory, and a read-write address.
Further, the debugging control information further comprises a reset instruction;
the method further comprises the step of obtaining the reset instruction from the register and carrying out reset operation on a debugging device of the on-chip memory.
In an embodiment of the present invention, the on-chip memory includes, but is not limited to, a tightly coupled memory TCM, an index address RAM of a first-level instruction cache, a data RAM of a first-level instruction cache, an index address RAM of a first-level data cache, a data RAM of a first-level data cache, an index address RAM of a second-level cache, and a data RAM of a second-level cache.
In an embodiment of the present invention, the read/write modes include a read mode, a write mode, an address area mode and an address self-increment mode, where the address area mode is used to read a part of data of the on-chip memory, and the address self-increment mode is used to read all data of the on-chip memory.
In an embodiment of the present invention, the read/write address includes a read/write start address and a read/write access area size.
Further, the externally input debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
Further, the bus is an AXI bus or an APB bus.
Step 302: acquiring the analyzed debugging control information from a register to generate a corresponding debugging read-write signal;
step 303: and performing corresponding read-write operation according to the debugging read-write signal and an externally input read-write signal.
It should be noted that, when the debug read-write signal is true (i.e., when the debug control information is received and a corresponding debug read-write signal is generated), corresponding read-write operation is performed according to the debug read-write signal; and when the debugging read-write signal is false (namely, when the debugging control information is not received and the debugging read-write signal is not generated), performing corresponding read-write operation according to the read-write signal input from the outside.
Further, after the step 303, the method further comprises:
and recording the time of the read-write operation or the time of analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write error or analysis error information into a register.
Further, after the step 303, the method further comprises: when writing operation is carried out, a consistency feedback identification is generated and stored in a register.
Further, after the step of obtaining the debug control information from the register in step 303 and before the step of generating the corresponding debug read-write signal, the method further includes:
when the on-chip memory is positioned in the CPU, detecting the storage state of an internal register of the CPU, and generating the corresponding debugging read-write signal when the storage state of the internal register of the CPU is empty;
and when the on-chip memory is positioned in the second-level cache, detecting the storage state of the internal register of the second-level cache, and generating the corresponding debugging read-write signal when the storage state of the internal register of the second-level cache is empty.
The present invention is further explained by providing several preferred embodiments, but it should be noted that the preferred embodiments are only for better describing the present invention and should not be construed as unduly limiting the present invention. The following embodiments may exist independently, and technical features in different embodiments may be combined and used in one embodiment.
As shown in fig. 4, the system on-chip storage is divided into a first level cache and a second level cache according to the CPU subsystem requirements and architecture, and the first level cache includes a first level instruction cache (L1 ICache), a first level data cache (L1 DCache), and Tightly Coupled storage (TCM) storage. According to the division mode of system storage, the debugging scheme of on-chip storage is also divided into two parts: first level Debug circuitry (L1_ TCM Debug) and second level Debug circuitry (L2 Debug). The first level of debugging circuitry is implemented inside the CPU, including debugging L1 ICache, L1DCache and TCM as well as other CPU internal storage. The second-level debugging circuit debugs a second-level Cache (L2Cache) and is implemented in the L2 Cache.
As shown in fig. 5, the first-level Debug circuit implemented by the present invention implements a Debug function stored on a chip inside a CPU, and can implement two modes, namely, an instruction Debug and a bus Debug, so that in a CPU system, an L1_ TCM Debug needs to receive a Debug instruction sent by a CPU Core (Core) and an AXI bus Slave (Slave) interface, and complete the analysis of the Debug instruction; accessing an L1 ICache, an L1D Cache and a TCM (trusted cryptography module) which are stored in a CPU (central processing unit) according to Debug instruction information, selecting an access storage interface of a Program Memory system (PMSS) and a primary debugging circuit through a selector, and connecting a primary instruction Cache; after a Data Memory system (DMSS) and an access Memory interface of a first-level debugging circuit are selected by a selector, a first-level Data cache and a tightly-coupled Memory TCM are connected; the output data of the first-level debugging circuit and the data output by an AXI Master (Master) interface of the CPU are selected by the selector and then output by the AXI Master interface, the read data are output to the AXI Master interface for being analyzed by a user, and the write data are stored in an internal memory.
As shown in fig. 6, the first-level Debug circuit of the present invention is divided into a first-level state control unit, a first-level read control unit, a first-level write control unit, a first-level master control unit, a first-level slave control unit, a first-level register unit, a first-level decoding unit, a first-level clock unit, a first-level time counting unit, a first-level error recording unit, and an instruction parsing unit according to the Debug requirement and function of the CPU portion, wherein:
the first-stage state control unit completes a control path of the first-stage debugging circuit, jumps to a corresponding state according to a debugging configuration mode and a debugging enabling state, and drives each unit to execute according to a flow. Specifically, the first-level state control unit acquires a debugging enabling state and a read-write mode stored in the first-level register unit, enables or closes a clock signal of the first-level read control unit or the first-level write control unit, and outputs the on-chip memory and the read-write address to the first-level read control unit when the clock signal of the first-level read control unit is enabled; when a clock signal of a primary write control unit is enabled, the on-chip memory and the read-write address are output to the primary write control unit;
the primary read control unit generates corresponding debugging read signals for accessing the L1 ICache TAG/Data RAM, the L1DCache TAG/Data RAM and the TCM according to the on-chip memory and the read-write address and outputs the debugging read signals to the primary decoding unit;
the primary write control unit generates corresponding debugging write signals for accessing L1 ICache TAG/Data RAM, L1DCache TAG/Data RAM and TCM according to the on-chip memory and the read-write address and outputs the debugging write signals to the primary decoding unit; receiving write data from a primary slave control unit and outputting the write data to a primary decoding unit;
the first-level main control unit outputs the read data from a debugging main interface according to an AXI protocol or an APB protocol (or other protocols such as Joint Test Action Group (JTAG)) and the like;
the primary Slave control unit analyzes information sent by an AXI Slave interface of the CPU, sends register configuration information to a primary register unit and sends write data to a primary write control unit;
the first-level register unit stores register configuration information and analysis information received from the instruction analysis unit and the first-level slave control unit, and stores error marks, error information and consistency problem feedback information;
the primary decoding unit completes read-write selection of an L1 ICache TAG RAM, read-write selection of an L1 ICache Data RAM, read-write selection of an L1DCache TAG RAM, read-write selection of an L1DCache Data RAM, read-write selection of a TCM, selection of a Slave interface and selection of a Master interface;
the primary clock unit finishes gating a clock, and determines whether the clock is turned off or not according to the working state of each unit;
the time counting unit completes the time counting of each state of the primary state control unit, including the read-write operation time, the slave interface analysis time and the data sending time of the master interface, and compares the time counting with a preset read-write time threshold, an analysis time threshold and a sending time threshold, if the time counting is larger than one of the thresholds, the time counting unit sends a time error to the primary error recording unit;
the primary error recording unit records error marks and error information under each state and outputs results to the primary register unit;
the instruction analysis unit completes the analysis of the debugging control information and sends the register configuration information in the debugging control information to the first-level register unit.
The register configuration information and the parsing information stored in the primary register unit are as shown in table one:
As shown in fig. 7, the basic implementation method of the first-level debug circuit of the present invention includes the following steps:
the first step is as follows: a1: a user configures a Debug mode instruction through an application program; alternatively, the first and second electrodes may be,
b1: a user configures a Debug mode through an AXI Slave interface;
the second step is that: a2: configuring a Debug enabling instruction by a user through an application program; alternatively, the first and second electrodes may be,
b2: a user configures Debug enabling through an AXI Slave interface;
the third step: resolving a Debug mode instruction and a Debug enabling instruction, storing a Debug mode and Debug enabling information to corresponding registers, and enabling a state machine of a primary state control unit to enter a Debug state; if the analysis is wrong, jumping to the ninth step; otherwise, continuing;
the fourth step: emptying the internal Cache, determining that data sent to the first-level Cache TCM/L1Cache is finished, and jumping to the ninth step if an error occurs in execution; otherwise, continuing;
the fifth step: determining read control access or write control access according to the configuration information of the primary register, and jumping to the ninth step if an error occurs; otherwise, continuing;
and a sixth step: accessing storage according to configuration information of a primary register:
c6: reading L1 ICache TAG RAM/L1 ICache Data RAM/L1 DCache TAG RAM/L1 DCache Data RAM/TCM Data, and jumping to the seventh step if the reading is successful; if an error occurs, jumping to the ninth step; alternatively, the first and second electrodes may be,
d6: writing Data to L1 ICache TAG RAM/L1 ICache Data RAM/L1 DCache TAG RAM/L1 DCache Data RAM/TCM; if the data writing is successful, jumping to the eighth step; if an error occurs, jumping to the ninth step;
the seventh step: the read data is returned to the primary control unit and finally output through the main interface, and a read operation completion identifier is generated and stored in the primary register unit; if an error occurs, jumping to the ninth step;
eighth step: after data access is completed, generating a write operation completion identifier and storing the write operation completion identifier in a primary register unit, generating a consistency feedback identifier and storing the consistency feedback identifier in the primary register unit, and turning off a clock until a normal Debug access flow is finished;
the ninth step: extracting error information, and writing the error type into a primary register unit;
the tenth step: the user determines whether to reset according to the error information, and executes the Debug scheme again;
the eleventh step: and the user performs software processing flow according to the consistency problem brought by the write operation.
The second-level debugging circuit (L2 Debug) realizes the Debug function of the internal storage of the L2Cache, is realized in the L2Cache, is completed by cooperating with the internal unit of the L2Cache, and needs to complete the Cache clearing of the internal unit; the L2Cache path and the Debug path select an L2 TAG, an L2 Data RAM, and AXI Slave to be connected to the L2 Debug unit, and the Master interfaces of the AXI Master and the Debug are selected by the selector and then output.
As shown in fig. 8, the second-level Debug circuit of the present invention implements a bus Debug mode, so that the L2 Debug in the L2Cache needs to receive control information and data sent by an AXI Slave interface and a second-level Cache control unit, where the control information includes an empty signal of a memory Cache unit and empty signals of Master0 and Master 1Cache control units; accessing the L2cache TAG RAM and Data RAM according to the configuration information of the second register unit, selecting the access storage interface of the second-level cache control unit and the access storage interface of the second-level debugging circuit through a selector, and then connecting each memory, wherein each memory comprises each block (Bank) of each Way (Way) of the TAG RAM and each block (Bank) of each Way (Way) of the Data RAM; the data output by the debugging main interface and the data output by the second-level cache main interface are selected by the selector and then output to a double-rate synchronous dynamic random access memory/third-level cache/AXI 2AXI bridge (DDR/L3/AXI2AXI) through an AXI Master interface for analysis by a user, and the write data is stored in an internal memory. Besides a second-level cache control unit, the second-level cache also comprises a clock unit, a configuration register unit, a Slave0 control analysis unit, a Slave1 control analysis unit, a TCM Slave control analysis unit, a TCM request generation and transmission unit (TCM REQ), a TCM storage control unit, a replacement control and cache unit (Evictin Buffer), a storage cache (Store Buffer) unit, a conflict detection unit (Harzard), an Event (Event) analysis unit and a Master0& Master 1cache control unit.
As shown in fig. 9, the second-level Debug circuit (L2 Debug) according to the present invention implements a Debug function stored on an L2Cache chip, and is divided into a second-level state control unit, a second-level read control unit, a second-level write control unit, a second-level master control unit, a second-level slave control unit, a second-level register unit, a second-level decoding unit, a second-level clock unit, a second-level time counting unit, and a second-level error recording unit according to the Debug requirement and function of the L2Cache part, wherein:
and the secondary state control unit completes a control path of the secondary debugging circuit, jumps to a corresponding state according to a debugging configuration mode and a debugging enabling state, and drives each unit to execute according to a flow. Specifically, the secondary state control unit acquires a debugging enabling state and a read-write mode stored in the secondary register unit, enables or closes a clock signal of the secondary read control unit or the secondary write control unit, and outputs the on-chip memory and the read-write address to the secondary read control unit when the clock signal of the secondary read control unit is enabled; when a clock signal of the secondary write control unit is enabled, the on-chip memory and the read-write address are output to the secondary write control unit;
the secondary read control unit generates a corresponding debugging read signal for accessing the L2Cache TAG/Data RAM according to the on-chip memory and the read-write address and outputs the debugging read signal to the secondary decoding unit;
the secondary write control unit generates a corresponding debugging write signal for accessing the L2Cache TAG/Data RAM according to the on-chip memory and the read-write address and outputs the debugging write signal to the secondary decoding unit; receiving write data from the secondary slave control unit and outputting the write data to the secondary decoding unit;
the secondary main control unit outputs the read data from the debugging main interface according to an AXI protocol or an APB protocol (or other protocols such as JTAG);
the secondary Slave control unit analyzes information sent by an AXI Slave interface of the CPU, sends register configuration information to a secondary register unit and sends write data to a secondary write control unit;
the secondary register unit stores register configuration information and analysis information received from the secondary slave control unit, and stores error flags and error information and consistency problem feedback information;
the secondary decoding unit completes read-write selection of an L2Cache TAG RAM, read-write selection of an L2Cache TAG RAM, selection of a Slave interface and selection of a Master interface;
the secondary clock unit finishes gating a clock, and determines whether the clock is turned off or not according to whether the clock works or not and the working state;
the time counting unit completes the time counting of each state of the secondary state control unit, including the read-write operation time, the slave interface analysis time and the data sending time of the master interface, and compares the time counting with a preset read-write time threshold, an analysis time threshold and a sending time threshold, if the time counting is larger than one of the thresholds, a time error is sent to the secondary error recording unit;
and the secondary error recording unit records error marks and error information in each state and outputs results to the secondary register unit.
The register configuration information and the parsing information stored in the secondary register unit are as shown in table two:
watch two
As shown in fig. 10, the basic implementation method of the second-level debug circuit of the present invention includes the following steps:
the first step is as follows: configuring a Debug mode by a user through AXI Slave;
the second step is that: configuring Debug enabling by a user through AXI Slave;
the third step: saving the Debug mode and Debug enabling information to corresponding registers, and enabling a state machine of the secondary state control unit to enter a Debug state; if an error occurs, jumping to the ninth step; otherwise, continuing;
the fourth step: emptying the Slot Cache and the Cache in the storage Cache unit (Store Buffer) in the Master0 and the Master1, determining that the data sent to the L2Cache is finished, and jumping to the ninth step if the execution is wrong; otherwise, continuing;
the fifth step: determining read control access or write control access according to the configuration information of the secondary register, and jumping to the ninth step if an error occurs; otherwise, continuing;
and a sixth step: accessing storage according to configuration information (including configuration information such as Way, Bank, and Multiport) of a secondary register:
c6: reading Way and Bank Data corresponding to the L2Cache TAG RAM/L2 Cache Data RAM, and jumping to the seventh step if the reading is successful; if an error occurs, jumping to the ninth step; alternatively, the first and second electrodes may be,
d6: writing Data into an L2Cache TAG RAM/L2 Cache Data RAM, and jumping to the eighth step if the Data writing is successful; if an error occurs, jumping to the ninth step;
the seventh step: the read data is returned to the secondary main control unit and finally output through the main interface, and a read operation completion identifier is generated and stored in the secondary register unit; if an error occurs, jumping to the ninth step;
eighth step: after data access is completed, generating a writing operation completion identifier and storing the writing operation completion identifier in a secondary register unit, generating a consistency feedback identifier and storing the consistency feedback identifier in the secondary register unit, and turning off a clock until a normal Debug access flow is finished;
the ninth step: extracting error information, and writing the error type into a secondary register unit;
the tenth step: the user determines whether to reset according to the error information, and executes the Debug scheme again;
the eleventh step: and the user performs software processing flow according to the consistency problem brought by the write operation.
The consistency support of the Debug scheme stored on the chip of the invention needs software and hardware cooperative processing and is divided into the following three conditions:
when a user writes the TAG RAMs of L1I/DCache and L2Cache, the operation in the normal mode is to store related Data in the Data RAM, and the inconsistency of the TAG RAM and the Data RAM is caused by the writing of the TAG RAM in the Debug mode. At this time, the user needs to fetch the instruction cache Data in the DDR through a software instruction and write the instruction cache Data into the Data RAM, so as to solve the consistency problem caused by writing Data.
When a user writes Data RAMs of L1I/DCache and L2 caches, WT (write through) type Data in a normal mode is written into the Cache RAMs and an external Memory (Memory), and Data in a Debug mode is written into the Cache RAMs. At this time, the user needs to write any data written into the Cache RAM into the external storage through a software instruction, so as to solve the consistency problem caused by writing data.
When the internal Cache of the CPU and the Store Buffer of the L2 have data, the data is written into the Cache or the Memory in the normal mode, and the data of the Cache and the Memory in the Debug mode are not updated, so that the hardware Debug unit performs Debug operation when the internal Cache of the CPU or the Store Buffer of the L2 is empty, completes reading and writing the data, and ensures that the data of the Cache RAM is up to date.
The invention can realize the following three Debug register configuration and data change and collection methods:
the first scheme is as follows: support AXI protocol configuration and collection data as described above;
scheme II: the APB protocol support can be realized, and data can be configured and collected through an APB interface;
the third scheme is as follows: JTAG debug may be supported.
The first scheme has the advantages of multiple supportable transmission types and more flexible Debug, and the second scheme has the advantages of simple protocol and simplified scheme. The first scheme and the second scheme can flexibly select to realize the first scheme, and the selected scheme depends on the practical application. And the third scheme can be selectively supported and is determined by the actual application requirements.
The three schemes only need to modify the Master control and the Slave control of the Debug unit, or add selection in the control unit, because the system of the present invention has an AXI bus, in order to utilize the existing resources, the preferred embodiment of the present invention is implemented by using the AXI protocol configuration and data collection of scheme one.
The invention can realize the following three Debug mode triggering modes:
scheme A: the direct debugging of the breakpoint of the CPU is supported, and when the breakpoint occurs, all stored data are read;
scheme B: the direct debugging of the breakpoint of the CPU is supported, and when the breakpoint occurs, the stored data is read according to the configuration;
scheme C: the breakpoint direct debugging method of the CPU can be configured.
The scheme A has the advantages that when the CPU is broken, the data of the Debug is directly returned to the user, the Debug can be carried out in real time, and the defect that whether the Debug is needed or not can not be determined according to actual requirements is overcome; the scheme B has the advantage that when the CPU releases the breakpoint, the Debug is performed according to the requirements of the user, but the real-time performance is not high. The scheme C combines the advantages and the disadvantages of the scheme A and the scheme B, whether the real-time performance is selected or not is selected according to the requirements of users, however, the optimization of the scheme increases the logic, and the selection of the three schemes can be flexibly selected by practical application.
The three schemes only need to modify the data control part, if breakpoint debugging in the scheme A is triggered to directly read all data once, and the scheme B reads the data according to configuration.
The debugging device and the debugging method of the on-chip memory provided by the invention generate the debugging read-write signal according to the debugging control information and carry out corresponding read-write operation according to the debugging read-write signal and the read-write signal input from the outside, thereby realizing flexible access to the on-chip memory, meeting the requirements of application on data analysis and correction of data according to the analysis result, and better supporting flexible debugging of the system.
The invention adopts a hardware special circuit to realize debugging of an on-chip memory, wherein the on-chip memory comprises but is not limited to a tightly coupled memory TCM, a first-level Cache L1I/DCache TAG RAM L1I/DCache Data RAM, a second-level Cache L2Cache TAG RAM and an L2Cache Data RAM, and provides low power consumption and consistency access support of software and hardware cooperation.
The Debug scheme stored on all chips is independent of the original structure, and can be reset independently, so that Debug and normal operation of the original structure are facilitated;
the read/write control unit realized by the invention can flexibly support read-write access to all the RAMs in the system;
the consistency software and hardware cooperative protection method and the hardware consistency architecture support provided by the invention ensure the consistency of read-write data and support Cache consistency access;
the invention can realize the gated clock, support the module structured access and low power consumption mode;
the invention realizes independent Slave access control and Master access control longitudinally through AXI, supports non-aligned data access and various data transmission modes;
the register unit and the read/write control unit are realized, so that the access RAM mode supports address self-increment and specified area access;
the realization of the instruction analysis unit and the input control unit ensures that the L1_ TCM Debug can support two trigger modes of instruction Debug triggering and external bus Debug access;
the invention can configure macro definition (Define) and distinguish according to different realization Way number (Way), block number (Bank) and multiple port (Multiport) of the macro definition, and support the access to flexible configuration of L1_ TCM Debug multiple Way; the method supports the access to the flexible configuration of different banks, Multiports and Way of the L2 Debug;
the L1_ TCM external bus Debug and the L2 Debug of the invention adopt AXI protocol configuration and access;
the realization of the error recording unit of the invention supports Debug error feedback.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (10)
1. An apparatus for debugging an on-chip memory, comprising an input control unit, a register unit, a control unit, and a decoding unit, wherein:
the input control unit is used for receiving and analyzing externally input debugging control information and storing the analyzed debugging control information to the register unit;
the register unit is used for storing the analyzed debugging control information;
the control unit is used for acquiring the analyzed debugging control information from the register unit, generating a corresponding debugging read-write signal and outputting the corresponding debugging read-write signal to the decoding unit;
the decoding unit is used for receiving a debugging read-write signal from the control unit and an externally input read-write signal, and when the debugging read-write signal is true, corresponding read-write operation is carried out according to the debugging read-write signal; and when the debugging read-write signal is false, performing corresponding read-write operation according to the read-write signal input from the outside.
2. The debugging apparatus according to claim 1, wherein the debugging control information comprises a debugging enable state, a read/write mode, and a read/write address of an on-chip memory.
3. The debugging apparatus according to claim 2, wherein said control unit comprises: a state control unit, a read control unit and a write control unit, wherein:
the state control unit is used for acquiring the debugging enabling state and the read-write mode, enabling or closing the read control unit or the write control unit, and outputting the read-write address of the on-chip memory to the read control unit when the read control unit is enabled; when the write control unit is enabled, outputting the read-write address of the on-chip memory to the write control unit;
the read control unit is used for generating a corresponding debugging read signal according to the read-write address of the on-chip memory and outputting the debugging read signal to the decoding unit;
and the write control unit is used for generating a corresponding debugging write signal according to the read-write address of the on-chip memory and outputting the debugging write signal to the decoding unit.
4. The debugging apparatus according to claim 1, further comprising a time statistic unit, wherein:
the decoding unit is also used for generating a read-write completion identifier and outputting the read-write completion identifier to the control unit;
the time counting unit is used for recording the time of the control unit for performing the read-write operation or the time of the input control unit for analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write errors or analysis error information to the register unit;
the register unit is also used for storing the read-write error or the analysis error information.
5. The debugging apparatus according to claim 1, wherein the externally inputted debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
6. The debugging apparatus according to claim 1, wherein when the on-chip memory is located inside a CPU, the control unit is further configured to:
detecting the storage state of an internal register of the CPU, and generating the corresponding debugging read-write signal when the storage state of the internal register of the CPU is empty;
when the on-chip memory is located inside a second level cache, the control unit is further to:
and detecting the storage state of the internal register of the second-level cache, and generating the corresponding debugging read-write signal when the storage state of the internal register of the second-level cache is empty.
7. A method for debugging an on-chip memory, comprising:
receiving and analyzing externally input debugging control information, and storing the analyzed debugging control information to a register;
acquiring the analyzed debugging control information from a register to generate a corresponding debugging read-write signal;
when the debugging read-write signal is true, performing corresponding read-write operation according to the debugging read-write signal; and when the debugging read-write signal is false, performing corresponding read-write operation according to the read-write signal input from the outside.
8. The debugging method of claim 7, wherein the debugging control information comprises a debugging enable state, a read-write mode, and a read-write address of an on-chip memory.
9. The debugging method of claim 7, further comprising:
and recording the time of the read-write operation or the time of analyzing the debugging control information, comparing the time with a preset read-write time threshold or an analysis time threshold, and if the time exceeds the read-write time threshold or the analysis time threshold, storing corresponding read-write error or analysis error information into a register.
10. The debugging method of claim 7, wherein the externally input debugging control information is: debugging control instructions input by a user program or debugging control information input by a bus.
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| CN112015611A (en) * | 2020-09-09 | 2020-12-01 | 厦门紫光展锐科技有限公司 | Chip debugging device, system and chip |
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