CN100371907C - Tracing debugging method and system for processor - Google Patents
Tracing debugging method and system for processor Download PDFInfo
- Publication number
- CN100371907C CN100371907C CNB200410086641XA CN200410086641A CN100371907C CN 100371907 C CN100371907 C CN 100371907C CN B200410086641X A CNB200410086641X A CN B200410086641XA CN 200410086641 A CN200410086641 A CN 200410086641A CN 100371907 C CN100371907 C CN 100371907C
- Authority
- CN
- China
- Prior art keywords
- processor core
- debugging
- tracing
- programmable counter
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a tracing debugging method and a system for a processor. The method comprises the steps: (A), a program counter is monitored; (B), whether a processing core executes a non-continuous command or not is judged according to address date of the program counter; (C), if the processing core executes the non-continuous command, a tracing breakpoint event is generated to set the processing core to enter to be under a debugging mode; (D), a value of the program counter of the processing core and the state of the processing core are obtained; (E), the value of the program counter and the state of the processing core are transmitted to a host machine in order to generate tracing debugging information of the processing core.
Description
Technical field
The present invention relates to a kind of method and system of tracing and debugging, particularly relate to a kind of tracing debugging method cheaply and system that is used for processor.
Background technology
Because the fast development of electronic technology, the framework of various types of processors becomes increasingly complex, so the normal built-in hardware debug module of processor uses this processor to develop new system to make things convenient for the developer.Fig. 1 is the block scheme of the built-in hardware debug module of an existing processor, wherein, the data of being transmitted on this tracing and monitoring device monitor address bus and the data bus, and the data on address bus and the data bus are deposited in this tracking apparatus for temporary storage, analyze for the developer.Yet this framework only is fit to not have the processor core of high-speed cache (cache) function.
At the problems referred to above, the MIPS processor utilizes programmable counter (the program counter of built-in circuit with processor, PC) changing condition, by extra extension EJTAG (EnhancedJoint Test Action Group, EJTAG) pin sends an Integrated Development Environment (integrated development environment to, IDE) software is with the inside of processor of recombinating in this Integrated Development Environment (IDE) software.When extending EJTAG pin position deficiency, the information of output will be seldom, and Integrated Development Environment (IDE) software will be very complicated.If when simplifying the complexity of this Integrated Development Environment (IDE) software, complete with regard to suspending processor etc. output information, allow processor move again, so reach the real-time program counter and follow the trail of with regard to difficulty, the MIPS processor also can't be accomplished data tracing in addition.
Fig. 2 is the block scheme of the built-in hardware debug module of an existing arm processor, and it utilizes built-in follow-up mechanism to export tracked information to an Integrated Development Environment software through debugging pin position.Though the method can reach real-time tracing, built-in follow-up mechanism accounts for the door and extra output pin of 17-55K, and this can increase the hardware cost of processor.Work as in addition under the limited situation of the very fast or extra output pin of processor travelling speed, just must can realize that just programmable counter is followed the trail of or the function of data tracing by built-in again tracking apparatus for temporary storage.
A built-in debugging link and the jtag interface of existing SH5 processor, the information storage of being followed the trail of simultaneously is in a debugging module first-in first-out buffer (debug module first in firstout, DM FIFO).This debugging module first-in first-out buffer (DM FIFO) is the first-in first-out buffer (FIFO) of a 3*64bit, though it can use less storer, but, need elder generation the processor time-out is given up new trace data simultaneously when this first-in first-out buffer (FIFO) when filling up data.This first-in first-out buffer (FIFO) also can be set at a ring-type first-in first-out buffer (circular FIFO), when this ring-type first-in first-out buffer (FIFO) when filling up data, though need not earlier processor to be suspended, but new trace data can cover old trace data.So the built-in track of hardware debugging of existing processor still has the space of improvement.
Summary of the invention
One object of the present invention is to provide a kind of tracing debugging method cheaply, avoiding the required built-in tracking apparatus for temporary storage of prior art, thereby saves hardware cost.
Another object of the present invention is to provide a kind of tracing debugging method cheaply, avoiding the required extra output pin of prior art, thereby saves hardware cost.
According to one aspect of the present invention, a kind of tracing debugging method that is used for processor is proposed, this processor has a processor core, one high-speed cache and a time set, this processor core has a normal execution pattern and a debugging mode, and has a programmable counter, address in order to the record next instruction, this high-speed cache is connected to this processor core by an address bus and data bus, this time set is connected to this processor core, to provide operating system to carry out the clocking capability that context switches (context switch), the method comprising the steps of: (A) monitor this programmable counter; (B), judge whether this processing core carries out discrete instruction according to the address date of this programmable counter; (C) if judge when this processor core is carried out discrete instruction, produce a tracking breakpoint event (trace break event), enter debugging mode to set this processor core; (D) obtain the value of programmable counter of this processor core and the state of this processor core; (E) transmit the value of this programmable counter and state to a main frame of this processor core, to produce the tracing and debugging information of this processor core at this main frame.
According to another aspect of the present invention, a kind of tracing and debugging system that is used for processor is proposed, this processor has a processor core, one high-speed cache, one Bus Interface Unit (BIU) and a time set, this processor core has a normal execution pattern and a debugging mode, and has a programmable counter, address in order to the record next instruction, this high-speed cache is connected to this processor core by an address bus and data bus, this Bus Interface Unit (BIU) is connected to this high-speed cache and a primary memory, this time set is connected to this processor core, to provide operating system to carry out the clocking capability that context switches (context switch), this system mainly comprises a tracing and monitoring device, one Hardware Breakpoint device, an one debugging control device and a debugging communication link.This tracing and monitoring device is connected to this programmable counter, to monitor the address date of this programmable counter; This Hardware Breakpoint device is connected to this address bus and data bus, with according to default Hardware Breakpoint, produces a Hardware Breakpoint incident, to allow this processor core suspend; This debugging control device is connected to this tracing and monitoring device, to control the action of this tracing and monitoring device; This debugs communication link, is connected to this a Hardware Breakpoint device and a main frame, and the value of this programmable counter and the state of this processor core are sent to this main frame, to produce the tracing and debugging information of this processor core at this main frame; Wherein, this tracing and monitoring device is according to the address date of this programmable counter, judge whether this processing core carries out continuous instruction, if judge when this processor core is carried out discrete instruction, this tracing and monitoring device produces one and follows the trail of breakpoint event (tracebreak event), enter debugging mode to set this processor core, this Hardware Breakpoint device obtains the value of programmable counter of this processor core and the state of this processor core.
Description of drawings
Fig. 1 is the block scheme of an existing built-in hardware debug module of processor.
Fig. 2 is the block scheme of an existing built-in hardware debug module of arm processor.
Fig. 3 is the use synoptic diagram of tracing and debugging cheaply of the present invention system.
Fig. 4 is the block scheme of Hardware Breakpoint device of the present invention.
Fig. 5 is used for the process flow diagram of the tracing debugging method of processor for the present invention.
Fig. 6 is the synoptic diagram of an example of tracing debugging method of the present invention.
Embodiment
Fig. 3 is the use synoptic diagram of tracing and debugging cheaply of the present invention system 300.In Fig. 3, a processor core 305 is in order to carry out the instruction of a program, and it has a programmable counter 309, in order to the address of record next instruction.This processor core 305 has a normal execution pattern and a debugging mode.One high-speed cache, 310 save commands and data, this high-speed cache 310 is connected to this processor core 305 by an address bus 306, data-out bus (DataOut bus) 307 and data input bus (DIB) (DataIn bus) 308, required instruction and data when providing this processor core 305 to carry out, and the data write out of temporary this processor core 305.One Bus Interface Unit (bus interface unit, BIU) 315 is connected to this high-speed cache 310, when not these processor core 305 desired datas or when instruction in this high-speed cache 310, by reading in these Bus Interface Unit 315 to one primary memorys (figure does not show), or when this high-speed cache 310 has filled up data or instruction, partial data is written in this primary memory (figure does not show) by this Bus Interface Unit (BIU) 315.One time set 320 is connected to this processor core 305, carries out the clocking capability that context switches so that an operating system to be provided.
This tracing and debugging system 300 mainly comprises a tracing and monitoring device 330, a Hardware Breakpoint device 340, a debugging control device 350 and a debugging communication link 360.This debugging communication link 360 is connected to this a Hardware Breakpoint device 340 and a main frame.When processor core 305 is in debugging mode, this is sent to this main frame with the value of this programmable counter and the state of this processor core 305, with on this main frame by an Integrated Development Environment (IDE) software this processor core 305 internal states of recombinating, produce the tracing and debugging information of this processor core 305.
This debugging communication link 360 comprises an internal memory control device 361 and an interface arrangement 362.This interface arrangement 362 can be a jtag interface so that and existing jtag circuit shared pins, save the pin of integrated circuit (IC).This interface arrangement 362 connects this main frame through a sniffer 370, and this sniffer 370 mainly is to be the receivable signal of this main frame with the jtag interface conversion of signals, and for example RS232 signal, usb signal are so that be sent to this main frame.These interface arrangement 362 other ends are connected to this internal memory control device 361, are sent to this internal memory control device 361 with the data with this main frame, or the data of internal memory control device 361 are sent to this main frame.
This internal memory control device 361 maps to the memory mapping (memory map) of this main frame with Hardware Breakpoint device 340 and debugging control device 350 internal registers, carries out related setting to make things convenient for this main frame.This internal memory control device 361 is connected to this Bus Interface Unit (BIU) 315 simultaneously, this main frame can pass through this internal memory control device 361 and this Bus Interface Unit (BIU) 315, and access is connected to primary memory (figure do not show) data of this Bus Interface Unit (BIU) 315 or be connected to the data of the peripherals (figure does not show) of this Bus Interface Unit (BIU) 315.
This Hardware Breakpoint device 340 is connected to this address bus 306, data-out bus 307 and data input bus (DIB) 308, with according to default Hardware Breakpoint, produces a Hardware Breakpoint incident, to allow this processor core 305 enter debugging mode.
Fig. 4 is the block scheme of this Hardware Breakpoint device 340, and it comprises one first register 341, one second register 342, one the 3rd register 343, one first comparer 344, one second comparer 345, one the 3rd comparer 346 and one or door 347.This main frame with desire set breakpoint address value, write out the data of this processor core 305 and read in the data of this processor core 305, be written to respectively in first register 341, second register 342 and the 3rd register 343 by this debugging communication link 360.The first input end of this first comparer 344 is connected to the output terminal of this first register 341, its second input end is connected to this address bus 306, when the address value that is occurred on the stored address value of this first register 341 and this address bus 306 is identical, this first comparer 344 produces a signal (Hardware Breakpoint incident), and be sent to this processor core 305 by this or door 347, to allow this processor core 305 enter debugging mode.In like manner, when these processor core 305 data are write out in the desire tracking, then utilize data-out bus 307, second register 342 and second comparer 345 to reach.
This debugging control device 350 is connected to this Hardware Breakpoint device 340, and the register that this main frame is set in this debugging control device 350 by this debugging communication link 360 is to enable (enable) or to cut out (disable) this tracing and monitoring device 330.
This tracing and monitoring device 330 is connected to this programmable counter 309, this address bus 306, data-out bus 307 and data input bus (DIB) 308, to monitor this programmable counter 309, this address bus and data bus activity.This tracing and monitoring device 330 is according to the address date of this programmable counter (PC) 309, judge whether this processing core 305 carries out discrete instruction, if judge when this processor core 305 is carried out discrete instruction, this tracing and monitoring device 330 produces one and follows the trail of breakpoint event (trace break event), and sets this processor core 305 and enter debugging mode.At this moment, this Hardware Breakpoint device 340 obtains the value of programmable counter of this processor core 305 and the state of this processor core.When this processor core 305 enters debugging mode, simultaneously this time set 320 cuts out (disable), under debugging mode, continue timing to avoid this time set 320, reach virtual real-time debug function.This Hardware Breakpoint device 340 is sent to this main frame with the value of this programmable counter and the state of this processor core 305, with on this main frame by an Integrated Development Environment (IDE) software this processor core 305 internal states of recombinating, produce the tracing and debugging information of this processor core 305.When this processor core 305 enters debugging mode, this main frame can pass through this internal memory control device 361 and this Bus Interface Unit 315, and access is connected to primary memory (figure do not show) data of this Bus Interface Unit 315 or be connected to the data of the peripherals (figure does not show) of this Bus Interface Unit 315.
This Hardware Breakpoint device 340 is set this processor core 305 and is returned normal execution pattern after the state of the value of this programmable counter and this processor core 305 is sent to this main frame.After this processor core 305 returns normal execution pattern, simultaneously this time set is enabled, to allow the program of carrying out at this processor core 305 re-execute.
Fig. 5 is used for the process flow diagram of the tracing debugging method of processor for the present invention, this processor has a processor core 305, a high-speed cache 310 and a time set 320, this processor core 305 has a normal execution pattern and a debugging mode, and have a programmable counter 309, in order to the address of record next instruction.This high-speed cache 310 is connected to this processor core 305 by an address bus and data bus.At first in step S510, monitor the address date of this programmable counter 309, this moment, this processor core 305 was under the normal execution pattern.In step S520,, judge whether this processing core 305 carries out discrete instruction according to the address date of this programmable counter 309.If judging this processor core 305 is that then execution in step S530 if not, then returns step S510 when carrying out discrete instruction.
In step S530, produce one and follow the trail of breakpoint event, enter debugging mode, simultaneously this time set 320 cuts out (disable) to set this processor core 305, to avoid this time set 320 under debugging mode, to continue timing, reach virtual real-time debug function.Because this time set 320 provides an operating system to carry out the clocking capability that context switches, when this time set 320 is closed (disable), operating system promptly can't be carried out context and be switched, and allows the program halt of carrying out on this processor core 305, to reach real-time effect.
In step S540, obtain the value of a programmable counter 309 of this processor core and the state of this processor core 305.In step S550, the value of this programmable counter 309 and the state of this processor core 305 are sent to this main frame, with on this main frame by an Integrated Development Environment (IDE) software this processor core 305 internal states of recombinating, produce the tracing and debugging information of this processor core 305, for the developer with reference to use.
In step S560, set this processor core 305 and return normal execution pattern.After this processor core returns normal execution pattern, simultaneously this time set 320 is enabled, switch to allow operating system can carry out context.At this moment, this processor core 305 is carried out the instruction that enters the preceding programmable counter indication of debugging mode, and returns step S510.
Fig. 6 shows of the present invention one actual example, and it is the synoptic diagram of assembly routine and annotations and comments, and wherein, figure the right is the value record of programmable counter 309, and it writes down the address of these processor core 305 next execution commands.As shown in the figure, the instruction at address 0x0,0x4,0x8,0xc and 0x10 place is all carried out continuously, so the value of programmable counter 309 is 0x0,0x4,0x8,0xc and 0x10 in regular turn.Instruction Bne r7, r4, Lab_b are the value of comparand register r7 and register r4, if when unequal, then redirect (branch) is to the Lab_b place.Because register r7 is 143, register r4 is 53, so instruction Bne sets up, programmable counter 309 can store the address value at this Lab_b place, i.e. 0x24.Be that this processor core 305 of decidable will be carried out discrete instruction this moment, follows the trail of breakpoint event so produce one, enters debugging mode to set this processor core 305.Simultaneously this time set 320 cuts out (disable), under debugging mode, continue timing, reach virtual real-time debug function to avoid this time set 320.And obtain the value of a programmable counter 309 of this processor core 305 and the state of this processor core 305.Again the value of this programmable counter 309 and the state of this processor core 305 are sent to this main frame, with on this main frame by an Integrated Development Environment (IDE) software this processor core 305 internal states of recombinating, produce the tracing and debugging information of this processor core 305, for the developer with reference to use.
In sum, the present invention utilizes this tracing and monitoring device 330 to observe the varying circuit of the programmable counter 309 of processor core 305, follows the trail of breakpoint event to produce one, and it utilizes the function of debugging originally can reach tracking function.In addition, employ processor core 305 enters debugging mode and controls time set 320 counting and reach the function that similar real-time program counter is followed the trail of.The present invention need not to use built-in tracking apparatus for temporary storage, can avoid the multiple tracking apparatus for temporary storage of the required use of prior art, thereby reduces hardware cost.Utilize existing JTAG pin can reach quick tracking effect simultaneously, more can avoid prior art to need the extra problem that output pin produced.
The foregoing description is only given an example for convenience of description, and the interest field that the present invention advocated should be as the criterion with appended claims, but not only limits to the foregoing description.
Claims (9)
1. tracing debugging method that is used for processor, this processor has a processor core, a high-speed cache and a time set, this processor core has a normal execution pattern and a debugging mode, and has a programmable counter, address in order to the record next instruction, this high-speed cache is connected to this processor core by an address bus and data bus, this time set is connected to this processor core, to provide an operating system to carry out the clocking capability that context switches, the method comprising the steps of:
(A) monitor this programmable counter;
(B), judge whether this processing core carries out discrete instruction according to the address date of this programmable counter;
(C) if judging this processor core is when carrying out discrete instruction, to produce a tracking breakpoint event, enter debugging mode to set this processor core;
(D) obtain the value of programmable counter of this processor core and the state of this processor core; And
(E) transmit the value of this programmable counter and state to a main frame of this processor core, to produce the tracing and debugging information of this processor core at this main frame.
2. tracing debugging method as claimed in claim 1, it further comprises the following step:
(F) set this processor core and return normal execution pattern, and return this programmable counter of step (A) persistent surveillance.
3. tracing debugging method as claimed in claim 1 wherein, is when carrying out continuous instruction, then to return step (A) if step (B) is judged this processor core.
4. tracing debugging method as claimed in claim 1, wherein, step (C) further comprises the following step:
(C1) when this processor core enters debugging mode, simultaneously this time set cuts out, to allow the program halt of carrying out at this processor core.
5. tracing debugging method as claimed in claim 2, wherein, step (F) further comprises the following step:
(F1) after this processor core returns normal execution pattern, carry out the instruction that this processor core enters the preceding programmable counter indication of debugging mode.
6. tracing debugging method as claimed in claim 5, wherein, step (F) further comprises the following step:
(F2) after this processor core returns normal execution pattern, simultaneously this time set is enabled, to allow the program of carrying out at this processor core re-execute.
7. tracing and debugging system that is used for processor, this processor has a processor core, one high-speed cache, one Bus Interface Unit and a time set, this processor core has a normal execution pattern and a debugging mode, and has a programmable counter, address in order to the record next instruction, this high-speed cache is connected to this processor core by an address bus and data bus, this Bus Interface Unit is connected to this high-speed cache and a primary memory, this time set is connected to this processor core, to provide an operating system to carry out the clocking capability that context switches, this system mainly comprises:
One tracing and monitoring device is connected to this programmable counter, to monitor the address date of this programmable counter;
One Hardware Breakpoint device is connected to this address bus and data bus, with according to default Hardware Breakpoint, produces a Hardware Breakpoint incident, to allow this processor core suspend;
One debugging control device is connected to this tracing and monitoring device, to control the action of this tracing and monitoring device; And
One debugging communication link is connected to this a Hardware Breakpoint device and a main frame, the value of this programmable counter and the state of this processor core is sent to this main frame, to produce the tracing and debugging information of this processor core at this main frame;
Wherein, this tracing and monitoring device is according to the address date of this this programmable counter, judge whether this processing core carries out continuous instruction, if judging this processor core is when carrying out discrete instruction, this tracing and monitoring device produces one and follows the trail of breakpoint event, enter debugging mode to set this processor core, this Hardware Breakpoint device obtains the value of a programmable counter of this processor core and the state of this processor core.
8. tracing and debugging as claimed in claim 7 system, wherein, this debugging communication link further comprises:
One interface arrangement is connected to this main frame, with transceive data to this main frame;
One internal memory control device, be connected to this interface arrangement, this Bus Interface Unit and this Hardware Breakpoint device, Hardware Breakpoint device and debugging control device internal register are mapped to a memory mapping of this main frame, so that this main frame carries out related setting, this main frame can pass through this internal memory control device and this Bus Interface Unit, and access is connected to the main memory data of this Bus Interface Unit or be connected to the peripheral data of this Bus Interface Unit.
9. tracing and debugging as claimed in claim 8 system, wherein, this interface arrangement can be a TTAG interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410086641XA CN100371907C (en) | 2004-11-19 | 2004-11-19 | Tracing debugging method and system for processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200410086641XA CN100371907C (en) | 2004-11-19 | 2004-11-19 | Tracing debugging method and system for processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1779654A CN1779654A (en) | 2006-05-31 |
| CN100371907C true CN100371907C (en) | 2008-02-27 |
Family
ID=36769990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200410086641XA Expired - Fee Related CN100371907C (en) | 2004-11-19 | 2004-11-19 | Tracing debugging method and system for processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100371907C (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100401267C (en) * | 2006-09-01 | 2008-07-09 | 上海大学 | Chip dynamic tracing method of microprocessor |
| CN101237350B (en) * | 2008-02-27 | 2010-12-01 | 中兴通讯股份有限公司 | Global variant exception alteration and positioning method for multi-task environment single board machine |
| CN104461796B (en) * | 2013-09-17 | 2017-12-22 | 上海华虹集成电路有限责任公司 | JTAG debugging modules and adjustment method for embedded 8051CPU |
| CN112579169B (en) * | 2019-09-27 | 2024-04-09 | 阿里巴巴集团控股有限公司 | Method and device for generating processor trace stream |
| CN112685278A (en) * | 2021-01-05 | 2021-04-20 | 上海擎昆信息科技有限公司 | Chip drive tracing debugging method and device |
| CN112685212B (en) * | 2021-01-05 | 2024-03-19 | 上海擎昆信息科技有限公司 | Processor exception debugging and tracking method, device and system |
| CN116108091B (en) * | 2022-12-26 | 2024-01-23 | 小米汽车科技有限公司 | Data processing method, event tracking analysis method, device, equipment and medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1133455A (en) * | 1994-12-28 | 1996-10-16 | 株式会社东芝 | Microprocessor and testing system |
| US6075941A (en) * | 1997-01-29 | 2000-06-13 | International Business Machines Corporation | Microcomputer |
| CN1444144A (en) * | 2002-03-08 | 2003-09-24 | 精工爱普生株式会社 | Debugging function built-in micro-computer |
-
2004
- 2004-11-19 CN CNB200410086641XA patent/CN100371907C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1133455A (en) * | 1994-12-28 | 1996-10-16 | 株式会社东芝 | Microprocessor and testing system |
| US6075941A (en) * | 1997-01-29 | 2000-06-13 | International Business Machines Corporation | Microcomputer |
| CN1444144A (en) * | 2002-03-08 | 2003-09-24 | 精工爱普生株式会社 | Debugging function built-in micro-computer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1779654A (en) | 2006-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20220252665A1 (en) | On-chip Debugging Device and Method | |
| CN102360329B (en) | Bus monitoring and debugging control device and methods for monitoring and debugging bus | |
| US7533302B2 (en) | Trace and debug method and system for a processor | |
| US7636870B2 (en) | Semiconductor integrated circuit device, and debugging system and method for the semiconductor integrated circuit device | |
| US6145099A (en) | Debugging system | |
| KR100856336B1 (en) | Real-time processor debug system | |
| CN100401267C (en) | Chip dynamic tracing method of microprocessor | |
| KR20010006188A (en) | Trace cache for a microprocessor-based device | |
| CN101154184A (en) | JTAG debugging method for microcontroller | |
| CN101458725B (en) | Microcontroller chip and debug method thereof | |
| CN102662835A (en) | Program debugging method of embedded system and embedded system | |
| US20060161818A1 (en) | On-chip hardware debug support units utilizing multiple asynchronous clocks | |
| CN101493847A (en) | Communication chip system chip tracing and debugging method and apparatus | |
| CN103593271A (en) | Method and device for chip tracking debugging of system on chip | |
| CN101751327B (en) | Method for tracing embedded processor debugging | |
| US20030233601A1 (en) | Non-intrusive signal observation techniques usable for real-time internal signal capture for an electronic module or integrated circuit | |
| JP2006507586A (en) | Apparatus and method for analyzing embedded system | |
| CN100371907C (en) | Tracing debugging method and system for processor | |
| CN109254883A (en) | A kind of debugging apparatus and method of on-chip memory | |
| CN112685278A (en) | Chip drive tracing debugging method and device | |
| CN202267954U (en) | Bus monitoring and debugging control device | |
| CN112685212A (en) | Debugging and tracking method, device and system for processor exception | |
| CN101998135A (en) | System for collecting and playing mobile television signal and control method | |
| CN100403275C (en) | Micro processor and method using in firmware program debug | |
| CN101963936A (en) | Method for storing working parameter state by DSP (Digital Signal Processor) equipment through CF (Compact Flash) memory card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080227 Termination date: 20161119 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |