CN202267954U - Bus monitoring and debugging control device - Google Patents
Bus monitoring and debugging control device Download PDFInfo
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- CN202267954U CN202267954U CN2011203670990U CN201120367099U CN202267954U CN 202267954 U CN202267954 U CN 202267954U CN 2011203670990 U CN2011203670990 U CN 2011203670990U CN 201120367099 U CN201120367099 U CN 201120367099U CN 202267954 U CN202267954 U CN 202267954U
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Abstract
The utility model discloses a bus monitoring and debugging control device used for solving the technical problem of poor real-time performance of the conventional device over bus monitoring and debugging. The technical scheme is that the bus monitoring and debugging control device comprises a phase-locked loop, a data acquisition module, a clock control module, a working mode control module, a breakpoint and debugging control module, a data transmission module, a memory, a memory controller, a configurable interface and time sequence control module, a serial data receiver and a serial data transmitter, wherein the data acquisition module is used for acquiring data on a bus of a target system and setting data addresses and instruction addresses required to be monitored; the memory module is used for recording access information of a core microprocessor to a specific address unit; the core processor is used for recording reading-writing operations of a pre-set key memory cell or a preset peripheral interface and comparing reading-writing and instruction-fetching address information of a memory data area with preset breakpoint information; and if the reading-writing and instruction-fetching address information of the memory data area is matched with the preset breakpoint information, the bus of the system is taken over, and real-time monitoring and debugging are completed.
Description
Technical field
The utility model relates to a kind of control device, particularly relates to a kind of monitoring bus and debugging control device.
Background technology
Functional part integrated on the universal and chip along with embedded system chip is more and more; Embedded system scale and complexity are increasingly high; This has increased the debugging of hardware system and the difficulty of software developer's debugging software undoubtedly, but system can monitor and debugging problem highlights.Some embedded systems, for example the Control of Automobile engine is perhaps controlled the system of satellite, needs certain fault-tolerant ability, and this just needs debug system speed and convenience in system, to inject mistake flexibly.In addition, different embedded systems is owing to use different processor cores, and the status signal of these processors and data address width maybe be different, for the proving installation that makes design reusable, but need the interface of flexible configuration.
Document " publication number is the United States Patent (USP) of US618914081 " discloses a kind of device that processor and embedded system are debugged.This device is typical application development sequence person a device that processor is debugged comparatively, has the JTAG debugging interface, the TAP controller, and boundary scan register etc.Input information that can be through the jtag interface serial during debugging is loaded into these information on the pin of chip in boundary scan register then, so just can processor controls or the input information of embedded system chip.This device lacks real-time monitoring and debugging capability, in the time will debugging system, need the normal work of processor be stopped, and can't satisfy some special Embedded Application occasions, like the embedded system of debugging control motor car engine.
Document " publication number is the United States Patent (USP) of US676907681 " discloses a kind of real-time processor debugging system.This device has added virtual address bus and virtual data bus between the core processor of embedded system and Cache, through gate logic the address signal of data updated and renewal is delivered to the debugging interface of circuit then; And core processor can provide the status signal of processor to debugging interface.Though this device constitutes simple, and because can be in the running status of opening test core processor under the situation of Cache, it is more accurate to measure.But when the existing embedded system SoC chip of test,, can't between core processor and Cache, increase hardware logic, so this method is also inapplicable because core processor is integrated in the chip piece with respective stored and peripheral hardware usually.In addition, this device only has monitoring function, lacks the ability that processor and embedded system are debugged.
Document " publication number is the Chinese patent of CN95120196.4 " discloses a kind of debugging apparatus of microprocessor.This device is accomplished debugging module and a processor cores in the microprocessor; Processor cores is carried out user program and is carried out the watchdog routine of the goal systems that is used to debug; Debugging module can make processor cores carry out and leave the watchdog routine in the debugging acid in as the interface of a debugging acid.Though this device can be revised the data in the storer through processor cores; Realize the similar wrong function of injecting; But since processor have only can detection system ruuning situation from carrying out that user program switches to when carrying out watchdog routine, lack support to real-time monitoring processor ruuning situation.In addition, though should the design consideration need to reduce chip pin quantity, the debugging interface that increases has still increased a spot of chip pin quantity undoubtedly.
Summary of the invention
In order to overcome conventional device to the deficiency of monitoring bus with debugging real-time difference; The utility model provides a kind of monitoring bus and debugging control device; Through data acquisition module real-time monitoring system bus; Core processor is carried out record to the read-write motion of predefined critical storage unit or Peripheral Interface,, monitor thereby accomplish in real time for analyzing; In real time core processor is made comparisons with preset breakpoint information to the read-write in memory data district and the address information of instruction fetch through end points and debugging control module; If coupling; Then take over system bus; And, system is debugged or injects mistake fast to system through the operation of configurable interface and time-sequence control module emulation bus.
The utility model solves the technical scheme that its technical matters adopted: a kind of monitoring bus and debugging control device; Comprise phase-locked loop pll, Gbps serial receiver and serial data transmitter; Phase-locked loop pll generates monitoring bus and the required system works clock of debugging control module; The data that Gbps serial receiver transmits host computer are gone here and there and are changed; Form by appointment sends to the mode of operation control module, and the serial data transmitter will need loopback to send on the LVDS for the data of host computer, be characterized in also comprising:
Clock control module according to work clock and the multiple between the system works clock CLK and each module work clock of phase relation generation of each module.
The data acquisition module that bus operation is monitored.Under the control of mode of operation control module; In advance check point is write this module, when each bus cycles begins, gather the bus behavior; When the bus operation of A_BUS and C_BUS indication is complementary with the check point that pre-sets; Then the behavior record with this bus operation gets off, and is sent to data transmission module then, in storer, preserves.When what visit is the position that needs monitoring, and the sampling module that reads and writes data so is under the control of data sampling enable signal, in the data value write store in the read/write data module.
A command signal of sending according to host computer is provided with the mode of operation of monitoring and debugging control module, disposes the interface that is connected with goal systems, and the mode of operation control module of control point, breakpoint is set.Send when makeing mistakes repeat requests at host computer simultaneously, notice serial data transmitter is uploaded error data again.
A breakpoint and a debugging control module that realizes breakpoint function and debug function.When bus operation indicates the breakpoint coupling that the instruction carried out and mode of operation control module be provided with in advance, then make the goal systems operation suspension through sending the STOP signal.Host computer can be checked the operation information that the goal systems processor core is current, and the operation of processor controls core.When host computer needed the debug processor core, through sending the processor core requests bus control right of HOLD signal to goal systems, when processor core when it has abandoned bus with the HOLDA signalisation, debug controller notice host computer can be debugged.After receiving the Debugging message that host computer sends, the waveform that Debugging message is converted into the goal systems bus sends to the goal systems bus.When receiving debugging the finish command that host computer sends, abandon bus control right thereby drive the HOLD invalidating signal.
One will need the data recorded write store, and the data transmission module of when host computer need be analyzed, data being uploaded.
A storer that is used under monitoring mode, preserving the bus data that samples.
A Memory Controller that is used for the control store read-write.
Also has a configurable interface and a sequential control module that is applicable to the multiple different goal systems of test.
Above-mentioned configurable interface and sequential control module comprise interface configuration register, interface RAM, interface sequence control state machine and select logic.The interface configuration register comprises data address bus width configuration register, control bus configuration register and sequential control state machine groups of configuration registers.Each row storage emulation bus of interface RAM during the cycle one clap the data that will produce.
The beneficial effect of the utility model is: because data acquisition module is used to gather the data on the goal systems bus; Monitoring can be provided with data address and the instruction address that needs monitoring with debug controller, and memory module is used to write down the details of core microprocessors to the particular address unit access.Its method for supervising is through the control point is set in advance data address and the program address that need monitor to be set, and when processor moved, if visit the address that these are provided with in advance, then the details with this memory access were recorded in the storage of debug system.Host computer reads the Visitor Logs of storing in the host computer through the mode of sending order to the utility model device and analyzes.Data acquisition module also is used to gather the data on the goal systems bus; Breakpoint is provided with instruction breakpoint and the data breakpoint that module is used to be provided with the needs monitoring; Also be provided at core processor and be in and wait for that the bus cycles carry out specific read-write operation to particular storage after accomplishing, the address of particular storage or peripherals and the specific value of reading and writing data are provided through the utility model device by host computer.So just can revise the value of particular variables or check particular variables.Its method of carrying out breakpoint is sampling address bus and a control bus when each bus cycles begins; The address that samples is compared according to memory access type (instruction/data) and the breakpoint that is provided with in advance; If coupling is arranged then transmit control signal, make processor be in the state of waiting for that the bus cycles finish to processor core.Write address and the specific value of reading and writing data of particular storage or peripherals then to this device by host computer.After finishing to wait for the bus cycles, this device is taken over system bus at last, in analog module emulation bus cycle bus cycles, accomplishes specific read-write is carried out in the address of particular storage or peripherals.So not only can check the state of each parts of goal systems and the content in the storer, and can through directly in storer or peripherals write error information come in system to inject fast mistake.For the configurable interface of the utility model design, increased the reusability of adaptability and device, make the utility model can be used for monitoring and debugging goal systems with distinct interface processor.
Below in conjunction with accompanying drawing and embodiment the utility model is elaborated.
Description of drawings
Fig. 1 is that the utility model monitoring bus is connected block diagram with the debugging control device with goal systems and host computer.
Fig. 2 is the utility model monitoring bus and a debugging control structure drawing of device among Fig. 1.
Fig. 3 is a data acquisition module detail drawing among Fig. 2.
Fig. 4 is an initial identification module detail drawing of bus cycles among Fig. 3.
Fig. 5 is that the sequential of bus cycles starting module work among Fig. 4 is given an example.
Fig. 6 is the generation circuit diagram of data sampling enable signal among Fig. 3.
Fig. 7 is that the sequential of data acquisition enable signal generation circuit working among Fig. 6 is given an example.
Fig. 8 is a write data sampling module detail drawing among Fig. 3.
Fig. 9 is that the sequential of data sampling module work among Fig. 8 is given an example.
Figure 10 produces STOP signal detail drawing when being Fig. 2 point of interruption and debugging control module realization breakpoint function.
Figure 11 produces the sequential of STOP signal and gives an example when being Figure 10 point of interruption and debugging control module realization breakpoint function.
Bus read cycle simulated timing diagrams for example when Figure 12 was debug function.
The bus write cycle simulated timing diagrams for example when Figure 13 was debug function.
Figure 14 is configurable interface and a sequential module detail drawing among Fig. 2.
But Figure 15 is a sequential control state machine groups of configuration registers structure among Figure 10.
Figure 16 is configuration interface and a sequential module sequential control state machine among Figure 10.
Embodiment
The interface signal title and the effect of the utility model monitoring bus and debugging control device and host computer and goal systems:
CLKIN: input clock on the plate, after PLL (Phase Locking Loop, phaselocked loop) frequency multiplication, as the system clock of monitoring bus and debugging control module.
SerialData/Command: with the LVDS input signal of host computer interface.Host computer transmits serial data through this signal wire toward monitoring bus and debugging control module at high speed, is used to be provided with duty, check point and breakpoint are set, and under the goal systems debugging mode, carry Debugging message toward monitoring bus and debugging control module.
SerialData to Master: with the LVDS output signal of host computer interface.Preserve ground during with controlling bus detects data upload and gives host computer through this signal wire.
A_BUS: the goal systems address bus, under monitoring mode, as input.Under debugging mode, as output, monitoring bus and debugging control module are write Debugging message to this bus.
D_BUS: the goal systems data bus, under monitoring mode, as input.Under debugging mode, as output, monitoring bus and debugging control module are write Debugging message to this bus.
C_BUS: the goal systems control bus, under monitoring mode, as input.Under debugging mode, as output, monitoring bus and debugging control module are write Debugging message to this bus.
STOP: break point signal, as output.When the data on the bus and breakpoint are complementary, send this signal.Indicating target system halt operation.READY signal that can processor controls.
HOLD: the output signal is connected on the HOLD signal of goal systems.When host computer has the HOLD order, send the HOLD request, the request processor core is abandoned bus control right.
HOLDA: input signal, goal systems is to the answer signal of HOLD request.Processor is abandoned bus control right through this signalisation monitoring bus and debugging control module handler.
With reference to Fig. 1～16, the utility model monitoring bus is connected through known LVDS (Low Voltage Differential Signal low-voltage differential signal) high speed serialization line with host computer with the debugging control device; The utility model monitoring bus and debugging control device are directly connected on the bus of goal systems.
The utility model monitoring bus and debugging control device comprise phaselocked loop, data acquisition module, clock control module, mode of operation control module, breakpoint and debugging control module, data transmission module, storer and Memory Controller, configurable interface and sequential control module, Gbps serial receiver and serial data transmitter.
PLL (Phase Locking Loop, phaselocked loop): the clock that crystal oscillator produces on the dash receiver generates monitoring bus and the required system works clock of debugging control module.
Clock control module Clock Controller: according to the work clock of each module and the work clock of the multiple between the system works clock CLK and each module of phase relation generation.
Data acquisition module Data Sample Module: bus operation is monitored.Under the control of mode of operation control module; In advance check point is write this module, when each bus cycles begins, gather the bus behavior; When the bus operation of A_BUS and C_BUS indication is complementary with the check point that pre-sets; Then the behavior record with this bus operation gets off, and is sent to data transmission module then, in storer Memory, preserves.Initial identification module of bus cycles is used to judge on the current bus whether initiated the bus address cycle; Because goal systems is normally operated on the different dominant frequency with the utility model device; In order to solve the metastable state problem of striding clock signal, the utility model has designed the circuit structure of a plurality of register continuous samplings.What Sample_Pointer0 write down in the Sample_Pointer9 is the address information that needs monitoring.Through will be under the bus cycles all addresses in the data on the address bus and ten the Sample_Pointer registers compare simultaneously, just can judge the position that whether current accessed visits needs monitoring, this part logical constitution the control point address comparison logic.When what visit is the position that needs monitoring, and the sampling module that reads and writes data so is under the control of data sampling enable signal, in the data value write store in the read/write data module.
Breakpoint and debugging control module: this module has realized breakpoint function and debug function.When bus operation indicates the breakpoint coupling that the instruction carried out and mode of operation control module be provided with in advance, then make the goal systems operation suspension through sending the STOP signal.Host computer can be checked the operation information that the goal systems processor core is current, and the operation of processor controls core.When host computer needed the debug processor core, through sending the processor core requests bus control right of HOLD signal to goal systems, when processor core when it has abandoned bus with the HOLDA signalisation, debug controller notice host computer can be debugged.After receiving the Debugging message that host computer sends, the waveform that Debugging message is converted into the goal systems bus sends to the goal systems bus.When receiving debugging the finish command that host computer sends, abandon bus control right thereby drive the HOLD invalidating signal.
The effect of breakpoint function is when finding that processor implements specific program address and data address, stops the operation of processor, can revise the value of variable etc. like this.The operation that stops processor realizing through sending the STOP signal to goal systems.The STOP signal is used to make processor to be in the state of waiting for that the bus cycles finish, execution that so just can interrupt handler.The circuit that produces the STOP signal comprises initial identification module of bus cycles, program breakpoint and data breakpoint storer, breakpoint match logic module.Initial identification module of bus cycles is identical with initial identification module 26S Proteasome Structure and Function of the bus cycles in the monitoring module.The address Break_PointerP0 of the program breakpoint that the program breakpoint memory stores is provided with is to Break_PointerP9; The address Break_PointerD0 of the instruction breakpoint that the data breakpoint memory stores is provided with is to Break_PointerD9.The function of breakpoint match logic module is exactly that request address and the address of program and instruction breakpoint of current bus address during the cycle compared; If exist coupling then what current accessed was described is a position that needs breakpoint, needs to produce the STOP signal this moment and make processor be in the state of waiting for the bus end; Otherwise, let processor normally accomplish request.The more parallel of these addresses carried out.
Debug function is mainly accomplished the simulation to the processor core bus cycles.When processor operates in debugging mode following time, according to simulated data and address that host computer sends, the sequential of debug function parts analog processor is sent read-write and address and data.When read operation, the data of the appropriate address that reads back; When write operation, write the simulated data that host computer is sent here at appropriate address.So not only can be when system's actual motion the visible status register of readout memory and peripheral hardware and the value of data register, and the value that can revise storer in this way realizes the similar wrong function of injecting.The simulation of concrete sequential is accomplished through configurable interface and sequential module.For a kind of method of verifying the bus reliability is provided, the debug function of the utility model provides the ability of revising standard time sequence in emulation bus during the cycle, and some signals can prolong under the control of configuration field or a period of time finishes in advance.When prolonging or finishing in advance, the signal of all generations all prolongs or finishes in advance.
Debug function comprises the simulation of bus read cycle and write cycle time.
1) read cycle simulation.When debugging module receive the simulation command of bus read cycle and receive corresponding address and the data of memory access type after; At first detect the rising edge of CLKOUT1; Can detect at the 15ns place the latest; Just can send address signal and R/W# signal at the moment, signals such as STRB#, RD#, PS#, DS# send according to time relationship, and the time interval is confirmed with the clock count of 200MHz.Confirming that Ready_Detected is ordered is identical with definite logic of the following Ready_Detected of monitoring mode, and the sampling of readback data is identical with monitoring mode.After data sampling is returned, the data of reading back are added PB, send to host computer through the LVDS serial then and handle.Finish these bus cycles then.
2) write cycle time simulation.After receiving the bus write cycle simulation command and corresponding data that host computer sends, at first detect the rising edge of CLKOUT1, detect at 15ns place the latest, send the real write cycle time PAD cycle before then, send write cycle time afterwards.After data write completion (Ready_Detected), accomplish write cycle time, then send again a PAD cycle.Relative time wherein uses the clock of 200MHz to carry out counting and timing and produces.Write operation is accomplished need not notify host computer.Because with respect to manually-operated, it is very fast that write operation is accomplished, and write operation need not feed back to the host computer data.
Configurable interface and sequential control module: for applicability and the reusability that improves the utility model; Configurable interface and sequential control module have been increased; Through using this module can test multiple different goal systems, its structure mainly comprises interface configuration register, interface RAM, interface sequence control state machine and selects logic.The interface configuration register comprises data address bus width configuration register, control bus configuration register and sequential control state machine groups of configuration registers.The data-bus width of hardware system support has 32,64 and 128 three kinds.Other data-bus width needs the upper computer software support, is come to packing data and unpack to realize other width by software.For example data-bus width is 16, and then software need replenish 16 bit data and gathers into 32 bit data and come transceive data.As long as when being connected, connect correct 16 with goal systems.The address-bus width of hardware system support has 32 and 64.Other forms need the software support.The width of control bus configuration register configuration control model, promptly total how many control signals.This registers group can be provided with 11 conditions altogether, and these 11 conditions are the state transitions between five Read_Cycle and six Write_Cycle in control timing control state machine respectively.The form of each condition is following, supposes to have now five control signals to come control data bus and address bus, and each condition has ten significance bits so; Wherein five are used for setting under the current state transfer case; Those control signals are to need to consider, need to consider to put 1, need not consider to put 0.When a condition need be considered, back closely follow was provided with the condition that this condition is set up, and was 1 or was 0.Like this when satisfying whole condition, state machine is to next state exchange, otherwise under current state, circulates.
Each row storage emulation bus of interface RAM one is clapped the data that institute will produce during the cycle, when simulation, need only so whenever send the data line that send among the interface RAM according to certain condition just can the emulation bus cycle.Data among the interface RAM are write by host computer.The interface sequence control state machine is used for the agreement that analogy is shaken hands.Which line data when its main thought is the current beat of control among the fetch interface RAM sends on the bus of goal systems.Which reads determine, select logic to realize through control by state machine.The interface sequence control state machine is responsible for time sequence control, and its method is to select the capable data of special interface RAM to send on the bus to realize, can simulate handshake in this way.
Figure 16 seen in the state exchange of sequential control state machine.Under system's normal operating conditions, this state machine is in the IDLE attitude, and when host computer sent HOLD and orders to monitoring with the debugging control module, this state machine got into the HOLD_REQ state, sends the HOLD request to the processor core of goal systems.If goal systems is returned the HOLDA signal, and abandon bus, then state machine gets into the WAIT state, waits for that host computer sends the order and the data of the memory access of simulated target system bus.If host computer has sent simulation command and data, then get into the bus timing of Read_Cycle1 and Write_Cycle1 state simulation processor respectively according to the operation that will simulate.Get into the WAIT state after a timing simulation is accomplished again and wait for that host computer sends new simulation command.As previously mentioned, Read_Cycle1 and Write_Cycle1 need accomplish under the control of the sequential control state machine groups of configuration registers in the interface configuration register to the conversion of succeeding state.
Storer Memory: be used to be kept at the bus data that monitoring mode is down sampled to.
Memory Controller Memory Controller: be used for the read-write of control store.
Mode of operation control module: also be the command processing module.The command signal of sending according to host computer is provided with the mode of operation of monitoring with the debugging control module, and the interface that configuration is connected with goal systems is provided with control point, breakpoint etc.Send when makeing mistakes repeat requests at host computer simultaneously, notice serial data transmitter is uploaded error data again.
Data transmission module Data Transmit Module: will need the data recorded write store, and when host computer need be analyzed, data uploaded.Because the frequency of operation of data acquisition module, storer and LVDS is different, in the process of carrying out data transmission, need buffering FIFO.When data acquisition module needed record data, this module was with the writing data into memory controller; When working in the uploading detection data, the data conversion that this module will be kept among the storer Memory uploads to host computer for the LVDS signal.
Gbps serial receiver: string and modular converter, the data that host computer is transmitted are gone here and there and are changed, and form by appointment sends to the mode of operation control module.
The serial data transmitter: parallel serial conversion module, with needing loopback to send on the LVDS for the data of host computer.Need carry out buffer memory to the data that transmit, wrong if the host computer checking data transmits, need to retransmit.
The method of using the utility model device to carry out monitoring bus and debugging is described below.
It is specific as follows to utilize the device of the utility model to carry out method for monitoring bus:
(1) host computer is through sending a plurality of control points information to the serial of SerialData/Command pin; Be converted into parallel data through Gbps serial receiver and give the mode of operation control module, a plurality of control points (comprising data address and program address) are write the Sample_Pointer register in the data acquisition module.
(2) employing writes control command with the identical method of step (1) by host computer, the utility model device is set is in monitoring mode.
(3) when the goal systems operate as normal, when the utility model device utilizes the bus cycles initial not with bus cycles of A-Latch recognition objective system, and in the sample content of address bus, data bus and control bus of each bus cycles.The address that samples compared with predefined control point Sample_Pointer0～Sample_Pointer9 according to memory access type (instruction/data) (adopt ten parallel comparator C MP0～CMP9).If coupling is arranged, execution in step (4); The execution in step that do not match (5).
(4) if CMP0～CMP9 comparative result has coupling, what this visit then was described is the position of a needs monitoring.In this case; With information such as the addresses of this bus cycles, data, instruction/data, read/write operations through module records such as write data sampling, read data sampling, Data_to_Mem, Addr_to_Mem to Memory WriteFIFO, and then leave in the storer.Execution in step (6).
(5) if CMP0～CMP9 comparative result has coupling, what this visit then was described is the position that need not monitor.Latched data is removed, not write store.
(6) from step (3) begin to carry out up to the program that will monitor carry out and finish or host computer withdraws from monitoring mode.
(7) at host computer when sending teletype command with the identical method of step (1), the bus data that this device will record storer sends to host computer analyze through Serial Data pin with the LVDS signal through data transmission module, serial data transmitter.
Utilize the device of the utility model to realize that the method for break point debugging function is specific as follows:
(1) host computer is through sending a plurality of breakpoints (ten instruction breakpoints and ten data breakpoints) information to the serial of SerialData/Command pin; Be converted into parallel data through Gbps serial receiver and give the mode of operation control module, with the Break_PointerP0～Break_PointerP9 or the Break_PointerD0～Break_PointerD9 register of a plurality of breakpoints (comprising program breakpoint address and data breakpoint address) write break point and debug controller.
(2) employing writes control command with the identical method of step (1) by host computer, the utility model device is set is in the debugging breakpoints pattern.
(3) when the goal systems operate as normal, when the utility model device utilizes the bus cycles initial not with bus cycles of A-Latch recognition objective system, and in the sample content of address bus, data bus and control bus of each bus cycles.The address that samples compared with predefined breakpoint B reak_PointerP0～Break_PointerP9 and Break_PointerD0～Break_PointerD9 according to memory access type (instruction/data) (adopt 20 parallel comparator C MPP0～CMPP9 and CMPD0～CMPD9).If there is not coupling, this device is not done any action, and the goal systems program continues to carry out.
(4) if the comparer comparative result in the step (3) has coupling; Then read-me implements a breakpoint; The signal STOP that the bus cycles are freezed in generation sends to goal systems through control bus C_BUS, and all signals that goal systems will be freezed on the bus remain unchanged; This device sends to host computer through Serial Data pin with the LVDS signal through data transmission module, serial data transmitter with this information simultaneously and notifies the user.
(5) user has two kinds of selections after the information of receiving program arrival breakpoint; A kind of selection is the state that adopts address bus, data bus and the control bus of the direct measurement target of surveying instrument systems such as oscillograph or logic analyser; Measure the order breakpoint and the debug controller that use the mode identical to write removing STOP signal by host computer after accomplishing with step (1); And then produce End_Stop signal removal STOP signal, thus the bus cycles that goal systems is thawed and freezed, program continues to carry out; Second kind of selection is in system, to inject mistake, and its method is: (a) host computer is taken over the HOLD order of bus to the request of sending of this device through the mode identical with step (1); (b) take over the HOLD signal of bus through control bus C_BUS to the target request of sending; (c) this device is removed the bus cycles that the STOP signal freezes goal systems and is thawed; (d) goal systems is abandoned bus control right, and notifies this device through control bus C_BUS; (e) this device notice host computer has obtained bus control right; (f) error message that will inject of host computer converts the bus read-write cycle that needs simulation into, adopts and imports breakpoint and debug controller into the identical mode of step (1); (g) this device adopts the finite states machine control configurable interface in emulation bus cycle and the bus read-write cycle that the sequential control module produces goal systems; (h) if what produce is the bus read cycle, the data of reading back are returned to host computer; If the total line write transactions that produces then shows by host computer whether write operation is successful; (i) this device is cancelled the HOLD signal, surrenders bus control right, and goal systems continues operation.
(6) begin execution from step (2) and withdraw from debugging mode to the utility model device transmission instruction up to host computer.
Claims (3)
1. monitoring bus and debugging control device; Comprise phase-locked loop pll, Gbps serial receiver and serial data transmitter; Phase-locked loop pll generates monitoring bus and the required system works clock of debugging control module, and the data that Gbps serial receiver transmits host computer are gone here and there and changed, and form by appointment sends to the mode of operation control module; The serial data transmitter will need loopback to send on the LVDS for the data of host computer, it is characterized in that also comprising:
Clock control module according to work clock and the multiple between the system works clock CLK and each module work clock of phase relation generation of each module;
The data acquisition module that bus operation is monitored; Under the control of mode of operation control module; In advance check point is write this module, when each bus cycles begins, gather the bus behavior; When the bus operation of A_BUS and C_BUS indication is complementary with the check point that pre-sets; Then the behavior record with this bus operation gets off, and is sent to data transmission module then, in storer, preserves; When what visit is the position that needs monitoring, and the sampling module that reads and writes data so is under the control of data sampling enable signal, in the data value write store in the read/write data module;
A command signal of sending according to host computer is provided with the mode of operation of monitoring and debugging control module, disposes the interface that is connected with goal systems, and the mode of operation control module of control point, breakpoint is set; Send when makeing mistakes repeat requests at host computer simultaneously, notice serial data transmitter is uploaded error data again;
A breakpoint and a debugging control module that realizes breakpoint function and debug function; When bus operation indicates the breakpoint coupling that the instruction carried out and mode of operation control module be provided with in advance, then make the goal systems operation suspension through sending the STOP signal; Host computer can be checked the operation information that the goal systems processor core is current, and the operation of processor controls core; When host computer needed the debug processor core, through sending the processor core requests bus control right of HOLD signal to goal systems, when processor core when it has abandoned bus with the HOLDA signalisation, debug controller notice host computer can be debugged; After receiving the Debugging message that host computer sends, the waveform that Debugging message is converted into the goal systems bus sends to the goal systems bus; When receiving debugging the finish command that host computer sends, abandon bus control right thereby drive the HOLD invalidating signal;
One will need the data recorded write store, and the data transmission module of when host computer need be analyzed, data being uploaded;
A storer that is used under monitoring mode, preserving the bus data that samples;
A Memory Controller that is used for the control store read-write.
2. monitoring bus according to claim 1 and debugging control device are characterized in also comprising a configurable interface and a sequential control module that is applicable to the multiple different goal systems of test.
3. monitoring bus according to claim 2 and debugging control device are characterized in that said configurable interface and sequential control module comprise interface configuration register, interface RAM, interface sequence control state machine and select logic; The interface configuration register comprises data address bus width configuration register, control bus configuration register and sequential control state machine groups of configuration registers; Each row storage emulation bus of interface RAM during the cycle one clap the data that will produce.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203670990U CN202267954U (en) | 2011-09-29 | 2011-09-29 | Bus monitoring and debugging control device |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885421A (en) * | 2014-03-26 | 2014-06-25 | 上海航天电子通讯设备研究所 | Standard bus controller |
| CN105700999A (en) * | 2016-02-19 | 2016-06-22 | 珠海格力电器股份有限公司 | method and system for recording processor operation |
| CN112165499A (en) * | 2020-12-01 | 2021-01-01 | 南京芯驰半导体科技有限公司 | Control flow monitoring method and device and storage medium |
| CN114050987A (en) * | 2021-11-03 | 2022-02-15 | 猫岐智能科技（上海）有限公司 | Contactless debugging system and method for Internet of things equipment |
| CN114884766A (en) * | 2022-03-29 | 2022-08-09 | 机械工业仪器仪表综合技术经济研究所 | Device for realizing integration of various industrial buses and 5G communication |
-
2011
- 2011-09-29 CN CN2011203670990U patent/CN202267954U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885421A (en) * | 2014-03-26 | 2014-06-25 | 上海航天电子通讯设备研究所 | Standard bus controller |
| CN103885421B (en) * | 2014-03-26 | 2017-04-05 | 上海航天电子通讯设备研究所 | A kind of STD bus controller |
| CN105700999A (en) * | 2016-02-19 | 2016-06-22 | 珠海格力电器股份有限公司 | method and system for recording processor operation |
| CN112165499A (en) * | 2020-12-01 | 2021-01-01 | 南京芯驰半导体科技有限公司 | Control flow monitoring method and device and storage medium |
| CN112165499B (en) * | 2020-12-01 | 2021-02-12 | 南京芯驰半导体科技有限公司 | Control flow monitoring method and device and storage medium |
| CN114050987A (en) * | 2021-11-03 | 2022-02-15 | 猫岐智能科技（上海）有限公司 | Contactless debugging system and method for Internet of things equipment |
| CN114050987B (en) * | 2021-11-03 | 2023-08-22 | 猫岐智能科技（上海）有限公司 | Non-contact debugging system and method for Internet of things equipment |
| CN114884766A (en) * | 2022-03-29 | 2022-08-09 | 机械工业仪器仪表综合技术经济研究所 | Device for realizing integration of various industrial buses and 5G communication |
| CN114884766B (en) * | 2022-03-29 | 2024-04-26 | 机械工业仪器仪表综合技术经济研究所 | Device for realizing integration of various industrial buses and 5G communication |
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