CN208655247U - Memory chip built-in self-test circuit device - Google Patents
Memory chip built-in self-test circuit device Download PDFInfo
- Publication number
- CN208655247U CN208655247U CN201821416120.XU CN201821416120U CN208655247U CN 208655247 U CN208655247 U CN 208655247U CN 201821416120 U CN201821416120 U CN 201821416120U CN 208655247 U CN208655247 U CN 208655247U
- Authority
- CN
- China
- Prior art keywords
- test
- under test
- signal
- vector
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The utility model provides a kind of memory chip built-in self-test circuit device, including circuit under test, register, comparison circuit and test result output module.Circuit under test is used for according to original test vector generation data signal under test.Comparison circuit is connected to circuit under test and register, for generating for indicating the whether effective test result indication signal of circuit under test to the original test vector and data signal under test progress logic XOR operation after register delay.Test result output module is used to select an output for indicating one of the effective validity test result of circuit under test and Logic state instruction value according to test result indication signal.It whether effective can not only judge circuit under test, and further obtain the Inactivation shape of circuit under test, the logic state of data signal under test and the logic state of original test vector can be immediately arrived at from test result.Testing efficiency is not only improved, but also is convenient for the subsequent maintenance to circuit under test.
Description
Technical field
The utility model relates to semiconductor integrated circuit technology fields, and in particular to a kind of memory chip built-in self-test
Circuit device.
Background technique
As the unit number for including in ultra-large semiconductor integrated circuit is more and more, thus bring shared by testing cost
The ratio of entire chip cost is increasing.Currently, generally believe can effectively solve the problem that chip-scale testing cost scheme be
Chip interior assigns " built-in self-test (BIST, Build-in Self-test) " structure that can increase core by this scheme
The controllability and observability of built-in testing, so that test vector generation and validation test be made to become easy.
Common test method be to chip under test load test vector, by collect response results and with expected results pair
Than coming whether detection chip can work normally.In current BIST Structure, memory chip comparison circuit be by
The data signal under test i.e. response results and test vector i.e. expected results exported after being tested circuit under test do exclusive or
Logical operation judges whether circuit under test can work normally by the result that operation obtains.Specific test process is: working as survey
When trying data-signal and test vector difference, output result is " 1 ", and judging result is circuit under test failure, cisco unity malfunction；
When data signal under test is identical as test vector, output result is " 0 ", and judging result is that circuit under test is effective, can be normal
Work.
However, can not accurately obtain the state of data signal under test according to judging result in current test method.Reason
It is that when circuit under test fails, it is possible that there are the following two kinds: when the state of data signal under test is " 1 ", the state of test vector is
When " 0 ", judging result is that circuit under test is invalid；When the state of data signal under test is " 0 ", and the state of test vector is " 1 ",
Judging result is also that circuit under test is invalid.At this point, the state of data signal under test is in the case where circuit under test is invalid, including two
Kind state " 0 " and " 1 ".Therefore, using existing test method, the shape of data signal under test can not be learnt according to judging result
State.
Utility model content
The utility model provides a kind of memory chip built-in self-test circuit device, to overcome or alleviated by background technique
Existing one or more problem at least provides a kind of beneficial selection.
As the one aspect of the utility model, a kind of memory chip built-in self-test circuit device is provided, including
Circuit under test, register, comparison circuit and test result output module；
The circuit under test is used to generate data signal under test according to original test vector；
The register is used to postpone the transmission time of the original test vector, so that the original test after delay
Vector and the data signal under test synchronism output；
The comparison circuit is connected to the circuit under test and the register, and the comparison circuit includes XOR gate, anti-
Phase device and NAND gate；
The XOR gate includes first input end, the second input terminal and the first signal output end, the first input end
For the original test vector after input delay, second input terminal is described for receiving the data signal under test
First signal output end is for the indication signal that outputs test result, and the test result indication signal is for indicating the electricity to be measured
Whether road is effective；
The phase inverter includes inverter input and inverter output, and the inverter input is for receiving delay
The original test vector afterwards, the inverter output are used to export the phase to the original test vector after delay
Invert the reverse phase test vector that 180 degree generates；
The NAND gate includes third input terminal, the 4th input terminal and second signal output end, the third input terminal
For receiving the data signal under test, the 4th input terminal is connected to the inverter output, the 4th input terminal
For receiving the reverse phase test vector, the second signal output end is for exporting Logic state instruction value, the logic shape
When state indicated value is for indicating circuit under test failure, the logic state of the data signal under test；
The test result output module is connected to the XOR gate and the NAND gate, for according to the test result
Indication signal selects an output for indicating in the effective validity test result of the circuit under test and the Logic state instruction value
One kind.
Preferably, in above-mentioned memory chip built-in self-test circuit device, the circuit device further include test to
Generation module is measured, the test vector generation module includes:
Built-in self-test controller, for generating test control signal；
Test vector generator, for generating the original test vector, the measurement according to the test control signal
The input terminal of vector generator is connected to the built-in self-test controller, multiple output ends difference of the measurement vector generator
It is connected to the circuit under test and the register.
Preferably, in above-mentioned memory chip built-in self-test circuit device, the test result output module is more
Path multiplexer and including selection control terminal, the first signal input part, second signal input terminal and test result output end；
The selection control terminal is connected to first signal output end of the XOR gate, for receiving the test knot
Fruit indication signal；
First signal input part is connected to the second signal output end of the NAND gate, for receiving described patrol
Collect state index value；
The second signal input terminal is for inputting for indicating the effective validity test result of the circuit under test；
The test result output end is used for when the test result indication signal is low level, and connection second signal is defeated
Enter end, and exports the validity test as a result, when the test result indication signal is high level, the first signal described in connection
Input terminal, and export the Logic state instruction value.
The utility model by adopting the above technical scheme, has the advantages that this programme carries out the function of comparison circuit
It improves.Specifically, by original test vector and data signal under test input comparison circuit, in comparison circuit, original test
Vector sum data signal under test passes through logic XOR operation, generates test result indication signal.In addition, the phase of original test vector
Bit reversal 180 degree generates reverse phase test vector, and reverse phase test vector and data signal under test are carried out logic NAND operation, defeated
Logic state instruction value out.Output Logic state instruction value is finally selected according to test result indication signal by multiplexer
Or validity test result, wherein when Logic state instruction value indicates circuit under test failure, the logic state of data signal under test.
Whether this programme can not only judge circuit under test effective, and further obtain the Inactivation shape of circuit under test, can
The logic state of data signal under test and the logic state of original test vector are immediately arrived at from test result.Not only mention
High testing efficiency, and it is convenient for the subsequent maintenance to circuit under test.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the utility model is into one
Aspect, embodiment and the feature of step, which will be, to be readily apparent that.
Detailed description of the invention
In the accompanying drawings, unless specified otherwise herein, otherwise indicate the same or similar through the identical appended drawing reference of multiple attached drawings
Component or element.What these attached drawings were not necessarily to scale.It should be understood that these attached drawings are depicted only according to originally practical
Novel disclosed some embodiments, and should not be taken as the limitation to the scope of the utility model.
Fig. 1 is painted the flow chart of storage chip build-in self-test method provided by the embodiment of the utility model.
Fig. 2 is painted storage chip built-in self-test circuit structure drawing of device provided by the embodiment of the utility model.
Fig. 3 is painted comparison circuit structure in storage chip built-in self-test circuit device provided by the embodiment of the utility model
Figure.
Fig. 4 is painted the signal schematic representation during storage chip built-in self-test provided by the embodiment of the utility model.
Detailed description of the invention:
100- test vector generation module；
101- built-in self-test controller；
102- test vector generator；
The input terminal of 111- test vector generator；
The output end of 110- test vector generator；
200- circuit under test；
300- register；
400- comparison circuit；
401- XOR gate；
The first input end of 411- XOR gate；
Second input terminal of 421- XOR gate；
First signal output end of 431- XOR gate；
402- phase inverter；
412- inverter input；
422- inverter output；
403- NAND gate；
The third input terminal of 433- NAND gate；
4th input terminal of 443- NAND gate；
The second signal output end of 413- NAND gate；
500- test result output module；
The first signal input part of 501-；
502- second signal input terminal；
503- test result output end；
504- selects control terminal.
Specific embodiment
Hereinafter, certain exemplary embodiments are simply just described.As one skilled in the art will recognize that
Like that, without departing from the spirit or scope of the present utility model, it can be modified by various different modes described real
Apply example.Therefore, attached drawing and description are considered essentially illustrative rather than restrictive.
In the description of the present invention, it should be understood that term " center ", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside",
The orientation or positional relationship of the instructions such as " clockwise ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " is based on the figure
Orientation or positional relationship is merely for convenience of describing the present invention and simplifying the description, rather than the dress of indication or suggestion meaning
It sets or element must have a particular orientation, be constructed and operated in a specific orientation, therefore should not be understood as to the utility model
Limitation.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.The meaning of " plurality " is two or two in the description of the present invention,
More than, unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " Gu
It is fixed " etc. terms shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be
Mechanical connection, is also possible to be electrically connected, can also be communication；It can be directly connected, the indirect phase of intermediary can also be passed through
Even, the connection inside two elements or the interaction relationship of two elements be can be.For those of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or it
"lower" may include that the first and second features directly contact, and also may include that the first and second features are not direct contacts but lead to
Cross the other characterisation contact between them.Moreover, fisrt feature includes above the second feature " above ", " above " and " above "
One feature is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign includes fisrt feature right above second feature and oblique upper under the second feature " below ", " below " and " below ", or only
Indicate that first feature horizontal height is less than second feature.
Following disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter the component of specific examples and setting are described.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, the utility model can in different examples repeat reference numerals
And/or reference letter, this repetition are for purposes of simplicity and clarity, itself not indicate discussed various embodiments
And/or the relationship between setting.In addition, the example of various specific techniques and material that the utility model provides, but this
Field those of ordinary skill can be appreciated that the application of other techniques and/or the use of other materials.
Embodiment one
In a kind of specific embodiment, a kind of memory chip build-in self-test method is provided, as shown in Figure 1, Figure 2,
Shown in Fig. 3 and Fig. 4, comprising:
Step S100: original test vector is input to circuit under test 200, generates data signal under test.
Functional test is carried out to circuit under test 200, whether the function to judge circuit under test 200 is effective.For example, to
Slowdown monitoring circuit 200 reads original test vector, and output test data signal, by judging data signal under test and original test vector
Whether unanimously learn whether circuit under test 200 can correctly read original test vector, if unanimously, illustrating circuit under test
200 read functions are effective, if inconsistent, illustrate the read functions failure of circuit under test 200.
Step S200: original test vector is input in register 300, when transmission to postpone original test vector
Between, so that original test vector is synchronous with data signal under test.
Since circuit under test 200 needs the time from the original test vector of reading to the signal that outputs test data, pass through
Original test vector is input in register 300 and caches a period of time, guarantees that original test vector and data signal under test are same
Step output.
Step S300: it to the original test vector and data signal under test progress logic XOR operation after delay, generates and surveys
Test result indication signal, effectively whether test result indication signal for indicating circuit under test 200.
Logic exclusive or can be carried out to the original test vector and data signal under test that receive simultaneously by XOR gate 401
Operation generates test result indication signal.For example, test result refers to as shown in figure 4, test result indication signal is exported from the road a
Show that signal is logic state 1 or 0.When test result indication signal is 1, indicate that circuit under test 200 fails.When test result refers to
When showing that signal is 0, indicate that circuit under test 200 is effective.Certainly, test result indication signal can also with the signals of other types into
Row indicates, in the protection scope of the present embodiment.
Step S400: the phasing back 180 degree of the original test vector after delay is generated into reverse phase test vector, and will be anti-
Phase test vector and data signal under test carry out logic NAND operation, export Logic state instruction value, and Logic state instruction value is used
When indicating that circuit under test 200 fails, the logic state of data signal under test.
As shown in figure 4, original test vector and data signal under test are passed through after above-mentioned logical operation, obtained logic shape
State indicated value may include logic state 1 or 0.
Step S500: according to test result indication signal, an output is selected for indicating the validity test knot of circuit under test 200
One of fruit and Logic state instruction value.
As shown in figure 4, exporting validity test signal when test result indication signal is 0, validity test signal can be used
The high-impedance state Hi-Z inputted in advance is indicated.When test result indication signal is 1, Logic state instruction value is exported.If final
Selection output Logic state instruction value is believed then illustrating that circuit under test 200 fails by the Logic state instruction of detection output
Number, obtain the logic state of data signal under test.For example, original test vector is 0 when Logic state instruction value is 0, number is tested
It is believed that number logic state be exactly 1；When Logic state instruction value is 1, original test vector is 1, the logic of data signal under test
State is exactly 0.
In one embodiment, original test vector is input to circuit under test 200 to test, generates test data
Before signal, further includes:
Original test vector is generated according to the test control signal that built-in self-test controller 101 generates.
Wherein, built-in self-test controller 101 generates test control signal, and test vector generator 102 receives testing and control
Signal, and original test vector is generated according to test control signal.Certainly, in the generation of original test vector including but not limited to
Mode is stated, can also be other generating modes, in the protection scope of the present embodiment.
In one embodiment, data signal under test and the logic state of the original test vector after delay include height
Level and low level generate test knot to the original test vector and data signal under test progress logic XOR operation after delay
The step of fruit indication signal includes:
When the logic state of data signal under test and the logic state difference of the original test vector after delay, patrolled
Collecting the test result indication signal generated after XOR operation is high level.
For example, the logic state of data signal under test is 0, the logic state of the original test vector after delay is 1, or
The logic state of data signal under test is 1, and the logic state of the original test vector after delay is 0, generates and surveys after XOR operation
Test result indication signal is 1, indicates that circuit under test 200 fails.
In one embodiment, when test result indication signal is high level, the step of Logic state instruction value is exported
Suddenly include:
When test result indication signal is high level and output Logic state instruction value is high level, then it represents that test number
It is believed that number logic state be low level；
When test result indication signal is high level and output Logic state instruction value is low level, then it represents that test number
It is believed that number logic state be high level.
For example, the logic state of data signal under test is 0, the logic state of original test vector is 1, test result instruction
Signal is 1, indicates that circuit under test 200 fails, and can indicate test data according to the output of the test result indication signal of high level
The Logic state instruction value of the logic state of signal, the process for generating Logic state instruction value is: logic state is 1 original test
The phasing back 180 degree of vector generates reverse phase test vector, and the logic state of reverse phase test vector is 0, and is 0 by logic state
Reverse phase test vector and logic state are that 0 data signal under test carries out logic NAND operation, and output Logic state instruction value is patrolled
The state of collecting is 1.Therefore, it is known that when the Logic state instruction value detected is 1, then it represents that the logic state of data signal under test
It is 0, the logic state of original test vector is 1.Similarly, when detecting that Logic state instruction value is 0, then it represents that test data letter
Number logic state be 1, the logic state of original test vector is 0.Circuit under test 200 can be directly obtained using aforesaid way
When failure, the logic state of the logic state of data signal under test and original test vector is made efficiently convenient for failure state
The judgement of rate.
In one embodiment, data signal under test and the logic state of the original test vector after delay include height
Level and low level generate test knot to the original test vector and data signal under test progress logic XOR operation after delay
The step of fruit indication signal includes:
When the logic state of data signal under test is identical with the logic state of the original test vector after delay, patrolled
It collects the test result indication signal generated after XOR operation and is expressed as low level.
For example, the logic state of data signal under test is 0, the logic state of the original test vector after delay is 0, or
The logic state of data signal under test is 1, and the logic state of the original test vector after delay is 1, generates and surveys after XOR operation
Test result indication signal is 0, indicates circuit under test 200 effectively, i.e., circuit under test 200 can correctly read original test vector.
In one embodiment, when test result indication signal is low level, the validity test result of output is indicated
For high-impedance state.
For example, high-impedance state pre-enters, when convenient for being 0 according to test result indication signal, having for high-impedance state is directly exported
Test result is imitated, indicates that circuit under test 200 can correctly read original test vector.Certainly, test result indication signal is 0
When, the signal of other types can also be exported, in the protection scope of present embodiment.
Embodiment two
In another embodiment specific implementation mode, provide a kind of memory chip built-in self-test circuit device, such as Fig. 2 and
Shown in Fig. 3, including test vector generation module 100, circuit under test 200, register 300, comparison circuit 400 and test result
Output module 500, test vector generation module 100 include built-in self-test (built-in self-test, BIST) controller 101
With test vector (Test Pattern Generator, TPG) generator 102.
Wherein, built-in self-test controller 101 is used for basis for generating test control signal, test vector generator 102
Test control signal generates original test vector, and the input terminal 111 for measuring vector generator is connected to built-in self-test controller
101, the output end 110 for measuring vector generator is respectively connected to circuit under test 200 and register 300.
Circuit under test 200 is used to generate data signal under test according to original test vector.Register 300 is for postponing original
The transmission time of beginning test vector, so that original test vector and data signal under test synchronism output after delay.
Comparison circuit 400 is connected to circuit under test 200 and register 300.Comparison circuit 400 includes XOR gate 401, reverse phase
Device 402 and NAND gate 403.XOR gate 401 includes first input end 411, the second input terminal 421 and the first signal output end
431, first input end 411 is for inputting original test vector, and the second input terminal 421 is for receiving data signal under test, and first
Signal output end 411 is for the indication signal that outputs test result, and whether test result indication signal is for indicating circuit under test 200
Effectively；Phase inverter 402 includes inverter input 412 and inverter output 422, and inverter input 412 prolongs for receiving
The original test vector to lag, inverter output 422 are used to export the phasing back 180 to the original test vector after delay
Spend the reverse phase test vector generated；NAND gate 403 includes third input terminal 433, the 4th input terminal 443 and second signal output
End 413, for third input terminal 433 for receiving data signal under test, the 4th input terminal 443 is connected to inverter output 422, the
Four input terminals 443 are for receiving reverse phase test vector, and second signal output end 413 is for exporting Logic state instruction value, logic
When state index value is for indicating that circuit under test 200 fails, the logic state of data signal under test；Test result output module
500, it is connected to XOR gate 401 and NAND gate 403, for selecting an output for indicating to be measured according to test result indication signal
One of the effective validity test result of circuit 200 and Logic state instruction value.
In one embodiment, test result output module 500 is multiplexer, and multiplexer includes selection control
End 504, the first signal input part 501, second signal input terminal 502 and test result output end 503 processed；Select control terminal
504 are connected to the first signal output end 431 of XOR gate 401, for receiving test result indication signal；First signal input part
501 are connected to the second signal output end 413 of NAND gate 403, for receiving Logic state instruction value；Second signal input terminal
502 for inputting for indicating the effective validity test result of circuit under test 200；Test result output end 503 is used for when test
When result indicative signal is low level, connection second signal input terminal 502, output validity test is as a result, when test result indicates
When signal is high level, the first signal input part of connection 501 exports Logic state instruction value.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, it is each can to readily occur in it
Kind change or replacement, these should be covered within the scope of the utility model.Therefore, the protection scope of the utility model
It should be based on the protection scope of the described claims.
Claims (3)
1. a kind of memory chip built-in self-test circuit device, which is characterized in that electric including circuit under test, register, comparison
Road and test result output module；
The circuit under test is used for according to original test vector generation data signal under test；
The register is used to postpone the transmission time of the original test vector, so that the original test vector after delay
With the data signal under test synchronism output；
The comparison circuit is connected to the circuit under test and the register, and the comparison circuit includes XOR gate, phase inverter
And NAND gate；
The XOR gate includes first input end, the second input terminal and the first signal output end, and the first input end is used for
The original test vector after input delay, second input terminal is for receiving the data signal under test, and described first
Signal output end is for the indication signal that outputs test result, and the test result indication signal is for indicating that the circuit under test is
It is no effective；
The phase inverter includes inverter input and inverter output, after the inverter input is for receiving delay
The original test vector, the inverter output are used to export the phasing back to the original test vector after delay
The reverse phase test vector that 180 degree generates；
The NAND gate includes third input terminal, the 4th input terminal and second signal output end, and the third input terminal is used for
The data signal under test is received, the 4th input terminal is connected to the inverter output for receiving the reverse phase test
Vector, the second signal output end is for exporting Logic state instruction value, and the Logic state instruction value is for indicating described
When circuit under test fails, the logic state of the data signal under test；
The test result output module is connected to the XOR gate and the NAND gate, for being indicated according to the test result
Signal selects an output for indicating one in the effective validity test result of the circuit under test and the Logic state instruction value
Kind.
2. memory chip built-in self-test circuit device as described in claim 1, which is characterized in that further include test vector
Generation module, the test vector generation module include:
Built-in self-test controller, for generating test control signal；
Test vector generator, for generating the original test vector, the test vector according to the test control signal
The input terminal of generator is connected to the built-in self-test controller, and multiple output ends of the test vector generator are separately connected
To the circuit under test and the register.
3. memory chip built-in self-test circuit device as described in claim 1, which is characterized in that the test result is defeated
Module is for multiplexer and including selection control terminal, the first signal input part, second signal input terminal and test result out
Output end；
The selection control terminal is connected to first signal output end of the XOR gate, refers to for receiving the test result
Show signal；
First signal input part is connected to the second signal output end of the NAND gate, for receiving the logic shape
State indicated value；
The second signal input terminal is for inputting for indicating the effective validity test result of the circuit under test；
The test result output end is used for when the test result indication signal is low level, and second signal described in connection is defeated
Enter end, and exports the validity test as a result, when the test result indication signal is high level, the first signal described in connection
Input terminal, and export the Logic state instruction value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821416120.XU CN208655247U (en) | 2018-08-29 | 2018-08-29 | Memory chip built-in self-test circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821416120.XU CN208655247U (en) | 2018-08-29 | 2018-08-29 | Memory chip built-in self-test circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208655247U true CN208655247U (en) | 2019-03-26 |
Family
ID=65792235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821416120.XU Active CN208655247U (en) | 2018-08-29 | 2018-08-29 | Memory chip built-in self-test circuit device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208655247U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111736062A (en) * | 2020-07-27 | 2020-10-02 | 上海兆芯集成电路有限公司 | Test system and test method |
| CN116008791A (en) * | 2023-03-27 | 2023-04-25 | 上海韬润半导体有限公司 | FPGA-based chip DFT test circuit, method and test machine |
-
2018
- 2018-08-29 CN CN201821416120.XU patent/CN208655247U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111736062A (en) * | 2020-07-27 | 2020-10-02 | 上海兆芯集成电路有限公司 | Test system and test method |
| CN116008791A (en) * | 2023-03-27 | 2023-04-25 | 上海韬润半导体有限公司 | FPGA-based chip DFT test circuit, method and test machine |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100367045C (en) | Circuit connecting line conducting test method based on dichotomy | |
| CN101173972B (en) | Method and apparatus for testing to determine minimum operating voltages in electronic devices | |
| CN1326147C (en) | Non-volatile memory, microcontroller and method for using same | |
| CN208655247U (en) | Memory chip built-in self-test circuit device | |
| US7571367B2 (en) | Built-in self diagnosis device for a random access memory and method of diagnosing a random access | |
| CN103698689B (en) | The ageing method and ageing device of integrated circuit | |
| CN101515479B (en) | Method for increasing test coverage of scan chain and device thereof | |
| CN102655101A (en) | Built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of 3D chip | |
| CN102332306A (en) | Embedded static random access memory (SRAM) test structure and test method based on institute of electrical and electronics engineers (IEEE) 1500 | |
| CN101996687A (en) | Built-in system test method of multiple static random access memory (SRAM) based on scanning test | |
| CN102608518A (en) | Chip testing method and device | |
| CN110120242A (en) | Method for testing memory, device, computer equipment and storage medium | |
| CN106546907B (en) | A kind of low power scan self testing circuit and self-test method | |
| CN108062267A (en) | Configurable register file self-testing method and generating device | |
| CN106685479B (en) | Fault excitation method and system in RS485 communication of electric energy meter | |
| CN110082672A (en) | The test method and device of logical model in a kind of chip | |
| CN105140152B (en) | Wafer level packaging single chip microcomputer pin welding detection method | |
| CN105334452A (en) | Testing system for boundary scan | |
| CN109801666A (en) | The test device of memory chip in a kind of hybrid circuit | |
| CN106610462A (en) | Electronic system, system diagnostic circuit and operation method thereof | |
| CN106291313A (en) | For the method and apparatus testing integrated circuit | |
| CN202120623U (en) | Embedded static random access memory (SRAM) testing structure based on institute of electrical and electronic engineers (IEEE) 1500 | |
| US8977513B2 (en) | Reliability test with monitoring of the results | |
| CN109164378A (en) | A kind of design and test method on boundary scan test chain road | |
| CN110415751A (en) | A kind of memory built in self test of sram circuit of parameterisable configuration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |