CN102655101A - Built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of 3D chip - Google Patents
Built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of 3D chip Download PDFInfo
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Abstract
The invention relates to a built-in self test and built-in self-repairing technology of TSV (Through Silicon Via) interconnection of a 3D chip. The technology comprises the following steps: at the chip-designing stage, corresponding built-in self test and built-in self-repairing circuits are inserted, and a redundant TSV channel is designed; after power-on reset of the 3D chip, the built-in self test circuit starts to work, carries out grouped test on TSVs, generates corresponding TSV configuration information according to a test result, and then calls the built-in self-repairing circuit for configuration of a TSV mapping circuit, and simultaneously, the test of next group of TSVs is started; after the test and the configuration on all the TSVs, the circuits can enter normal working. The technology has the advantages that the difficulty of the TSV interconnection in the traditional 3D chip can be solved, the strategy can be replaced by redundancy, and the finished-product rate of the 3D chip is increased; the dependency of the 3D chip test on ATE (Automatic Test Equipment) is reduced, so that the test cost of the 3D chip is reduced; and due to independency from the specific chip function, the technology can be widely applied to the 3D chip based on the TSVs and has stronger practicability.
Description
Technical field
The invention discloses a kind of 3D chip TSV (silicon perforation) interconnection built-in self-test and in build self-repair technology.Specifically be meant after the 3D chip power resets (Power-on Reset); The built-in self-test circuit is started working; TSV is divided into groups to test, and generate corresponding TSV configuration information, build self-repair circuit in calling then TSV is configured according to test result; After the test of accomplishing all TSV and configuration, circuit both can get into operate as normal.
Background technology
Along with dwindling and the increase of circuit scale of device size, delay and power problems that interconnection line brought are more and more serious, and in fact, this has become the main bottleneck of restriction circuit performance.The 3D chip has increased the design space through the perpendicular interconnection of silicon puncturing technique realization multilayer silicon chip, has improved the flexibility of design, also can reduce chip area simultaneously, improves circuit working speed, reduces the power consumption of circuit.In recent years, TSV technology has obtained major progress, has had the 3D chip to come out abroad, and product comprises 3D cmos sensor, 3D FPGA, 3D RAM etc.But, in order to realize commercially producing of 3D chip, also have many difficult problems to need to solve, for example the control of the test of 3D chip, rate of finished products etc.
TSV is the key technology that realizes the chip perpendicular interconnection; Under the existing processes condition; The manufacturing of TSV (fabrication), aligning (alignment), bonding (bonding) process all might be introduced the fault relevant with TSV, and therefore, the test of TSV is just particularly important.To the test of TSV, more feasible at present scheme is behind bonding, to test (post-bond test) stage, implements through the TSV interconnecting test.Erik Jan Marinissen etc. has proposed a kind of solution based on boundary scan, and each TSV is connected a scanning element, carries out the TSV interconnecting test through the boundary scan mode, but the hardware spending of this scheme is bigger.Yu-Jen Huang etc. has proposed a kind of scheme of built-in self-test; This scheme has only been considered the test of TSV interconnection; Therefore all connect a scanning element without each TSV, but, the TSV array is tested line by line through BIST with the array that TSV is configured to be similar to memory; Thereby can hardware spending be reduced greatly, also can save testing cost simultaneously.In addition, to the TSV that has fault,, will cause the inefficacy of entire chip if do not take measures.And along with the increase (increase of the increase of TSV density and chip superposed number of layers) of TSV quantity, the TSV fault to the influence of chip yield and chip cost with corresponding increase.To the chip yield loss that the TSV fault is caused, Ang-Chih Hsieh etc. has proposed redundant (redundancy) technology, through increasing redundant TSV, out of order TSV passage is replaced as subsequent use signalling channel, thus the reparation of realization TSV.Hung-Yen Huang etc. proposed a kind of to TSV interconnection built-in self-test and in build the selfreparing scheme, through the TSV equivalence is carried out charge-discharge test for the RC model, be a kind of simulation test technology, but the accuracy of the RC model of TSV is still waiting to prove.Therefore, the present invention proposes a kind of to TSV interconnection built-in self-test and in build self-repair technology, this technology can overcome the defective of current TS V interconnecting test technology, and can improve the rate of finished products of chip.
Summary of the invention
The purpose of this invention is to provide a kind of to 3D chip TSV interconnection built-in self-test and in build the method for selfreparing, solving the difficult problem of current 3D chip TSV test, and, improve the rate of finished products of chip through the redundancy replacement strategy.
In order to achieve the above object, the invention discloses the DFT technology of building selfreparing in a kind of TSV of collection built-in self-test and the TSV, mainly comprise the two large divisions, build self-repair circuit (BISR) in TSV built-in self-test circuit (BIST) and the TSV.Wherein BIST partly comprises following a few part: BIST controller, test vector generation and transmitting element, address counting and decoding unit, test response analytic unit; BISR comprises following a few part: BISR controller, TSV map unit, TSV redundancy analysis unit.The BIST controller is used for controlling the work of other module of BIST circuit; Test vector generates and transmitting element is used to generate test vector and output TSV is applied the test and excitation signal; Address counting and decoding unit are used to select TSV to be tested capable, and the test response analytic unit links to each other with input TSV to catch from the test signal of another layer and to generate corresponding failure diagnosis information; The BISR controller is used for controlling the work of other module of BISR circuit; The TSV map unit is used to realize the mapping between signal and the TSV passage, and TSV redundancy analysis unit generates corresponding configuration information to realize the correct configuration to the TSV map unit according to failure diagnosis information.Need at each layer all to need above-mentioned corresponding circuit on the chip of stack.
It is as shown in Figure 1 to have used 3D chip of the present invention.With two-layer is example, and chip layer 101 and 102 realizes perpendicular interconnection through TSV, and 111 and 112 are respectively TSV signalling channel and TSV redundant channel, and 121 and 122 for the special-purpose TSV passage of test, is used for the transmission of configuration information at the adjacent core lamella.The BIST of single layer of chips and the plan view of BISR are as shown in Figure 2.201 are output TSV, and 202 are input TSV (only be used for explaining this scheme, have more TSV).Each output TSV connects a MUX (211), and each input TSV connects a tristate buffer (212), and MUX selects control signal and tristate buffer output enable signal to be generated through decoding by address counter.Test vector generates and transmitting element is connected to output TSV through MUX, and input TSV is connected to the test response analytic unit through tristate buffer.The a certain position of address decoder is output as at 1 o'clock; To select an input TSV of delegation and a line output TSV simultaneously; It is capable that test vector is applied to selected output TSV; Transfer to the test response analytic unit of another layer chip through this row TSV, in like manner, the test response analytic unit is through the capable test vector that receives from another layer of selected input TSV.Accomplish after the test of selected line TSV, will generate configuration information by TSV redundancy analysis unit, be written to then in the mapping control register of tested TSV, address counter begins to descend test and the repair of two row TSV from increasing simultaneously.
Basic testing process is as shown in Figure 3: at first TSV is categorized as input TSV (Inward TSV) and output TSV (Outward TSV); According to N one group TSV is divided into the M group then; Can TSV be arranged as the memory array that is similar to the capable N row of M like this, each group comprises N-1 signal TSV passage and a redundant TSV passage.Receiving POR (Power-On Reset; Electrification reset) after the signal; BIST on all chip layer and BISR begin collaborative work simultaneously; With one deck wherein is that example is done explanation corresponding work flow process: 1) through address counting and decoding unit, select one group of input TSV and one group of output TSV simultaneously, as the object of test next time; 2) test vector generation and transmitting element begin to generate test vector and output TSV are applied test and excitation, and through shifting function test vector (i.e. the test response of expectation) are sent into the test response analytic unit; 3) the test response analytic unit is caught the test signal from another layer, and compares with the test response of expecting, and generates corresponding TSV fault message; 4) if all test vectors are all tested, get into 5), otherwise get into 2); 5) if the number of defects of one group of TSV≤2; The redundancy analysis unit generates corresponding configuration information according to the TSV fault message so; And be configured through the TSV map unit of shifting function to transmitting terminal and receiving terminal; Get into 6 simultaneously), otherwise generative circuit fault-signal and termination test and repair; 6) if all TSV have all tested and repaired to finish, circuit revert to normal operating conditions, otherwise gets into 1) choose down two groups of TSV and test and repair.With respect to traditional T SV testing scheme, the present invention has the following advantages:
1. reduced dependence to ATE equipment.Traditional T SV testing scheme is mostly based on IEEE 1149.1 or IEEE 1500 standards; Promptly each TSV is connected a boundary scan cell; Apply test vector through ATE equipment, when TSV quantity was very big, this testing scheme will significantly increase the cost of chip.This invention utilizes the built-in self-test circuit that TSV is interconnected and tests, and therefore can reduce the dependence to ATE equipment greatly.
2. improve the rate of finished products of chip.The present invention adopts soft reparation (soft repair) strategy; Promptly at every turn after chip power resets; BIST on the chip (built-in self-test circuit) promptly starts working, and according to test result, calls BISR (in build self-repair circuit) out of order TSV is carried out redundancy replacement.This soft reparation strategy has stronger flexibility, according to the analysis of document [5], for medium scale 3D circuit (TSV quantity≤10000), only needs per 50 TSV to distribute the TSV of a redundancy, just can the chip yield be increased to more than 99.4.
Description of drawings
Fig. 1 TSV built-in self-test is built the self-repairing system tomograph in reaching
Fig. 2 TSV built-in self-test is built self-repairing system individual layer plane structure chart in reaching
The workflow that Fig. 3 built-in self-test circuit is built self-repair circuit in reaching
Fig. 4 BIST master controller state transition diagram
Fig. 5 BISR master controller state transition diagram
Fig. 6 TSV mapping circuit structure chart
Fig. 7 test response is analyzed and the redundancy analysis circuit structure diagram
Embodiment
Below in conjunction with accompanying drawing describe in detail 3D chip TSV provided by the present invention interconnection built-in self-test and in build self-repair technology.
This technology mainly comprises the two large divisions, builds self-repair circuit (BISR) in TSV built-in self-test circuit (BIST) and the TSV.Wherein BIST partly comprises following a few part: BIST controller, test vector generation and transmitting element, address counting and decoding unit, test response analytic unit; BISR comprises following a few part: BISR controller, TSV map unit, TSV redundancy analysis unit.Design and realization below in conjunction with the description of drawings main modular:
1.BIST master controller is used for controlling the work of other module of BIST circuit, its state transition diagram is as shown in Figure 4.Receiving power-on reset signal (Power on Reset) afterwards, controller gets into the INITIALIZE state, accomplishes relevant initial work.Get into the FETCH_PAT state then, select a test vector (test vector can be built among the ROM, also can be generated by finite state machine).Get into the SHIFT_PAT state thereupon; Test vector is write test vector transmitting element (TPT) and test response analytic unit (TRA), after whole test vector is write (number of the TSV of delegation has determined the length of test vector, thereby has determined the cycle-index of SHIFT_PAT); Controller gets into the UPDATE_PAT state (when needs cover the relevant fault of sequential; Need to increase this state), get into the CAPTURE_PAT state then, in order to the acceptance test pumping signal.If accomplished the test of all test vectors, then controller gets into the ADDR_INC state, and the address selects following two groups of TSV to test from increasing, otherwise controller gets into the FETCH_PAT state, chooses next test vector and tests.After the test job of accomplishing all TSV, controller gets into the END state, but the circuit operate as normal (need to prove; Under any state; When finding the fault that can not repair, controller will get into the TERMINATE state, stop test process; Here for state diagram for simplicity, omitted this part).
2.BISR master controller is used for controlling the work of other module of BISR circuit, its state transition diagram is as shown in Figure 5.Receiving power-on reset signal (Power on Reset) afterwards, controller gets into the INITIALIZE state, accomplishes relevant initial work.Get into the WAIT cycle of states then, wait for scanning, transmission, the acquisition procedure of a test vector of BIST circuit completion, get into the CONFIG_GEN state thereupon, generate corresponding configuration information according to test result.Get into the CONFIG_SHIFT state subsequently, the configuration information that generates is written to the TSV configuration register of tested row through scan mode.If accomplished the repair of all TSV, then controller gets into the END state, otherwise controller gets into the WAIT state, begins the configuration effort that next organizes TSV to be measured.(identical with the BIST master controller, under any state, when the fault finding to repair, controller will get into the TERMINATE state, the termination repair process, here for state diagram for simplicity, omitted this part).
3. test response analytic unit and redundancy analysis unit generate TSV redundant configuration information in order to the analytical test result and according to test result, and its implementation is as shown in Figure 6.When the test of each row TSV of beginning; Because be interconnecting test, the test vector of transmitting terminal also is the desired test response of receiving terminal simultaneously, therefore when applying each test vector; Need test vector be write test vector transmitting element and test response analytic unit (through controlling MUX (602) so that d type flip flop (603) is operated in scan pattern) simultaneously; The test response analytic unit carries out " step-by-step XOR " operation (realizing through XOR door 601) with the desired value of test response that receives and storage, generates corresponding fault message, if there is not fault; Then all faults indicate the position and are 0; If there is fault in some TSV, the test signal and the desired value that cause receiving are inequality, the fault marker location 1 that xor operation will be corresponding with this TSV.TSV redundancy analysis device is used for the fault message according to the generation of test response analyzer, generates corresponding mapping control information, is used for correctly disposing tested TSV is capable, to realize that out of order TSV is carried out redundancy replacement.The redundancy analysis device directly is connected on the test response analyzer; When the test of each row TSV of beginning; D type flip flop (613) is resetted, whenever apply a test vector, the test response analyzer will obtain one group of fault message; With this fault message with applied before the corresponding fault message of vector carry out " step-by-step or " operation (through " or " gate 611 realizations), with the fault message that obtains accumulating.After having applied all test vectors, with obtaining the capable complete fault message of tested TSV.Make TSV redundancy analysis device be operated in scan pattern (realizing) then, the mapping control information be written to the capable mapping control register of tested TSV through control MUX (612), entire arrangement information in shifting process, generates (through " or " gate 621 realizations).If the number of defects >=2, then " with " gate 631 output will be 1, show the fault that existence can not be repaired.Because the mapping control information both need be written to the configuration register of transmitting terminal, also need be written to the configuration register of receiving terminal, so need between the adjacent core lamella to increase by two extra TSV passages, be used for the transmission of configuration information between the layers of chips.
4.TSV mapping circuit is in order to the mapping between realization function signal and the TSV passage, thereby realization redundancy replacement.The mapping control information generation multiple mode can be arranged, with wherein a kind of be example, like Fig. 7; Each MUX connects a d type flip flop and (wherein 701 represents transmitting terminal MUX; 702 represent receiving terminal MUX, and 711 represent the transmitting terminal configuration register, and 712 represent the receiving terminal configuration register); Through scan mode control information is write d type flip flop, thereby realize correct configuration TSV.The configuration register that low level TSV is corresponding places the front end (right-hand member of figure) of scan chain, and the configuration register that high-order TSV is corresponding places the rear end (left end of figure) of scan chain.
Above-mentioned each embodiment only is used to explain the present invention, and wherein the concrete realization of each module all can change to some extent, and every equivalents of on the basis of technical scheme of the present invention, carrying out and improvement all should not got rid of outside protection scope of the present invention.
Claims (6)
1. build the technology of selfreparing in the built-in self-test to 3D chip TSV interconnection reaches; Including the built-in self-test module is used for TSV is tested and generate corresponding failure diagnosis information; And in build self-repair module and be used for the TSV that has fault is carried out redundancy replacement, it is characterized in that:
After chip power resetted, the built-in self-test circuit was promptly started working, and TSV is divided into groups to test; And build self-repair circuit in calling; According to fault message the TSV mapping circuit is correctly disposed, after the test of accomplishing all TSV and configuration, circuit both can get into normal operating conditions.
2. a kind of built-in self-test system and method thereof to 3D chip TSV interconnection according to claim 1 is characterized in that:
To the TSV test of dividing into groups,, apply a plurality of test vectors, and generate corresponding failure diagnosis information during a certain group of TSV in test according to test result, accomplish the test of one group of TSV after, both can begin the test of next group TSV, finish until all TSV tests.
3. according to claim 1 a kind of to building self-repairing system and method thereof in the 3D chip TSV interconnection, it is characterized in that:
Adopt soft reparation strategy, promptly behind the each electrification reset of chip, with the configuration effort of accomplishing TSV automatically, to realize that the TSV that has fault is carried out redundancy replacement.After the test of accomplishing one group of TSV, correctly dispose according to the d type flip flop of failure diagnosis information control MUX, after the configuration of accomplishing all TSV, circuit can get into normal operating conditions.
4. test response analytical system according to claim 2 and method thereof is characterized in that:
The test response analytic unit is connected with input TSV array; The desired value of test response that receives and storage is carried out " step-by-step XOR " operation, generate corresponding fault message, if there is not fault; Then all faults indicate the position and are 0; If there is fault in some TSV, the test signal and the desired value that cause receiving are inequality, the fault marker location 1 that xor operation will be corresponding with this TSV.
5. redundancy analysis system according to claim 3 and method thereof is characterized in that:
TSV redundancy analysis device is connected with the test response analytic unit, is used for the fault message according to the generation of test response analyzer, generates corresponding configuration information, thereby the TSV map unit is correctly disposed, to realize that out of order TSV is carried out redundancy replacement.When the test of each row TSV of beginning; D type flip flop is resetted, whenever apply a test vector, the test response analyzer will obtain one group of fault message; With this fault message with applied the corresponding fault message of vector before and carry out " step-by-step or " and operate, with the fault message that obtains accumulating.After having applied all test vectors, with obtaining the capable complete fault message of tested TSV, i.e. configuration information needed.Make TSV redundancy analysis device be operated in scan pattern then, configuration information is written to the capable mapping control register of tested TSV.
6. TSV mapped system according to claim 3 and method thereof is characterized in that:
The TSV mapping circuit is used to realize redundancy replacement.Because the present invention adopts soft reparation (soft repair) strategy, configuration information is stored in the d type flip flop, and each MUX connects a d type flip flop, through scan mode configuration information is write d type flip flop, thereby realizes the correct configuration to TSV.The configuration register that low level TSV is corresponding places the front end of scan chain, and the configuration register that high-order TSV is corresponding places the rear end of scan chain.
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| CN113466668B (en) * | 2021-07-09 | 2024-05-17 | 哈尔滨工业大学 | Interlayer dielectric cavity fault test structure and test method based on switch capacitor |
| TWI763570B (en) * | 2021-07-28 | 2022-05-01 | 瑞昱半導體股份有限公司 | Memory device, memory test circuit and memory test method thereof having repair information maintaining mechanism |
| CN115373926A (en) * | 2022-08-31 | 2022-11-22 | 西安微电子技术研究所 | Self-testing and self-repairing method, system, equipment and medium based on physical layer IP |
| CN115684896A (en) * | 2022-12-29 | 2023-02-03 | 摩尔线程智能科技(北京)有限责任公司 | Chip testability design test method, test platform, and generation method and device thereof |
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