CN112114998A

CN112114998A - Method, device, storage medium and terminal for repairing redundant information in static random access memory

Info

Publication number: CN112114998A
Application number: CN202010780186.2A
Authority: CN
Inventors: 罗海燕; 王文武; 杨涛
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-08-05
Filing date: 2020-08-05
Publication date: 2020-12-22

Abstract

The invention discloses a method, a device, a storage medium and a terminal for repairing redundant information in a static random access memory, wherein the method comprises the following steps: when the built-in self-test is realized for a storage array in a chip, information data of each static random access memory in the storage array is shared; performing redundancy analysis according to the information data of each static random access memory to generate redundancy information required to be added by each static random access memory; and distributing redundancy information to each static random access memory based on the redundancy information needing to be added. Therefore, the method and the device can be used for rapidly evaluating the redundant logic information of the static random access memory in the initial stage of chip development and repairing the redundant logic information, so that the yield of the chip is improved.

Description

Method, device, storage medium and terminal for repairing redundant information in static random access memory

Technical Field

The invention relates to the technical field of chips, in particular to a method and a device for repairing redundant information in a static random access memory, a storage medium and a terminal.

Background

In the chip manufacturing, with the continuous reduction of process nodes, the logic scale of the chip is larger and larger, and the density of Static Random Access Memories (SRAMs) with the same storage capacity is also greatly improved, so that the number of the Static Random Access Memories (SRAMs) integrated on a single chip is rapidly increased, and the scale of the static random access memories is also continuously improved while the scale of the existing chip is continuously increased, so that the static random access memories in most chips can occupy more than half of the area of the single chip. Such large-scale applications make Static Random Access Memories (SRAMs) highly susceptible to defects that may scrap an entire chip. Therefore, how to plan the test and implementation scheme of the Static Random Access Memory (SRAM) is of great significance to the yield (yield) and yield of the whole chip.

In the prior art, one is based on macroscopic recommendations given by the manufacturing plant (Foundry), which is a relatively large granularity. As the area of the memory cell increases, the yield difference between the memory cell and the logic cell under the same condition becomes larger and larger. Therefore, the (manufacturer) Foundry gives a macroscopic repair scheme, and when the size of the memory cell exceeds a certain range, the memory cell needs to be repaired, so that the stability of the overall yield (yield) is ensured, but the real condition of the chip is not considered, and the given value is difficult to obtain the optimal result. The other is that each Design House (Design House) generally determines redundancy logic according to the recommendations of the manufacturer (foundation) based on the existing experience, and compared with the solution recommended by the manufacturer (foundation), the operation granularity is more accurate, but the situation of one-time cutting cannot be avoided, and the better effect is difficult to achieve. The existing mechanism provides that the redundancy logic is calculated according to the real chip area, but the input data needs to model the static random access memory unit according to the detailed information of a manufacturer (Foundry), complex global iteration and repeated operation are adopted, the division of the row and the column of the memory unit is not considered, the influence of repair logic, the grouping of the static memory unit and the repair logic is not considered, and the requirement of complexity is too high to be applied to the actual project.

Therefore, how to quickly detect and repair redundant information of a memory cell in a chip, thereby improving the yield of the chip, is a difficult problem to be urgently broken through in the academic world.

Disclosure of Invention

The embodiment of the application provides a method and a device for repairing redundant information in a static random access memory, a storage medium and a terminal. The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

In a first aspect, an embodiment of the present application provides a method for repairing redundant information in a static random access memory, where the method includes:

when the built-in self-test is realized for a storage array in a chip, information data of each static random access memory in the storage array is shared;

performing redundancy analysis according to the information data of each static random access memory to generate redundancy information required to be added by each static random access memory;

distributing redundancy information to each static random access memory based on the redundancy information to be added

Optionally, before the implementation of the built-in self-test for the memory array in the chip, the method further includes:

receiving a preset redundancy evaluation algorithm;

the redundancy evaluation algorithm is embedded into built-in self-test logic for a memory array in a chip.

Optionally, performing redundancy analysis according to the information data of each static random access memory to generate redundancy information that needs to be added to each static random access memory includes:

performing descending order arrangement according to the capacity of each static random access memory to generate each arranged static random access memory;

reading parameter information shared by the static random access memories according to the arranged static random access memories;

performing row and column repair calculation based on the shared parameter information to generate a row and column redundancy weight in each static random access memory;

iteratively comparing the row-column redundancy weight values in each static random access memory to obtain the optimal row-column redundancy weight values in each static random access memory;

performing ascending arrangement on the optimal row-column redundancy weights in each static random access memory to generate an arranged weight set;

and calculating the redundancy distribution of each static random access memory based on the arranged weight set to generate the redundancy information of each static random access memory.

Optionally, the performing row-column repair calculation based on the shared parameter information to generate a weight of row-column redundancy in each sram includes:

acquiring grouping information, repair information and an area estimation value of the chip in the parameter information shared by the static random access memories;

and inputting the grouping information, the repairing information and the area estimation value of the chip into a preset row-column weight calculation formula to generate a row-column redundancy weight in each static random access memory.

Optionally, the calculating the redundancy distribution of each static random access memory based on the arranged weight set to generate redundancy information of each static random access memory includes:

performing refined weight calculation on the rows and the columns of the static random access memories according to the arranged weight set and the corrected area in the parameter information to obtain an optimal redundant solution;

and taking the optimal redundancy solution as redundancy information of each static random access memory.

Optionally, after the allocating the redundancy information to each static random access memory based on the redundancy information to be added, the method further includes:

when register sharing is started in the chip, a shared repair unit is obtained;

reducing, by the shared repair unit, additional area overhead introduced by self-test logic of the static random access memory;

calculating whether the SRAM can pass the shared redundancy and whether the redundancy information needs to be adjusted according to the row weight and the column weight;

if so, optimizing the area of the chip.

In a second aspect, an embodiment of the present application provides an apparatus for repairing redundant information in a static random access memory, where the apparatus includes:

the data sharing module is used for sharing the information data of each static random access memory in the storage array when the built-in self test is realized for the storage array in the chip;

the redundancy information generation module is used for performing redundancy analysis according to the information data of each static random access memory and generating redundancy information which needs to be added to each static random access memory;

and the redundant information repair module is used for distributing the redundant information to each static random access memory based on the redundant information needing to be added.

Optionally, the apparatus further comprises:

the algorithm receiving module is used for receiving a preset redundancy evaluation algorithm;

and the algorithm embedding module is used for embedding the redundancy evaluation algorithm into built-in self-test logic for the storage array in the chip.

In a third aspect, embodiments of the present application provide a computer storage medium storing a plurality of instructions adapted to be loaded by a processor and to perform the above-mentioned method steps.

In a fourth aspect, an embodiment of the present application provides a terminal, which may include: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the above-mentioned method steps.

The technical scheme provided by the embodiment of the application can have the following beneficial effects:

in the embodiment of the application, when the device for repairing redundant information in the static random access memory performs built-in self-test on the memory array in the chip, information data of each static random access memory in the memory array is shared firstly, then redundancy analysis is performed according to the information data of each static random access memory to generate redundant information required to be added to each static random access memory, and finally redundant information distribution is performed on each static random access memory based on the redundant information required to be added. According to the method and the device, the preset evaluation algorithm is embedded into the implementation process of the built-in self test (MABIST) logic of the storage array, the redundancy analysis of the static random access memory in the storage array is carried out through the shared data information, the redundancy result is generated, and finally the redundancy logic information is subjected to redundancy distribution and further optimization through the redundancy result, so that the yield of the chip is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic flowchart illustrating a method for repairing redundant information in an sram according to an embodiment of the present application;

FIG. 2 is a schematic process diagram of a process of analyzing redundant information in an SRAM according to an embodiment of the present application;

fig. 3 is a schematic flowchart of weight calculation during analyzing redundant information in an sram according to an embodiment of the present disclosure;

FIG. 4 is a schematic flow chart illustrating further optimization of redundant information in an SRAM according to an embodiment of the present disclosure;

FIG. 5 is a flow chart illustrating a logic for repairing redundant information in an SRAM according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an apparatus for repairing redundant information in an SRAM according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of an apparatus for repairing redundant information in an SRAM according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a terminal according to an embodiment of the present application.

Detailed Description

The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

To date, one of the methods for redundant logic detection and repair in a chip is based on macro recommendations given by the manufacturing plant (Foundry), which has a relatively large granularity. As the area of the memory cell increases, the yield difference between the memory cell and the logic cell under the same condition becomes larger and larger. Therefore, the (manufacturer) Foundry gives a macroscopic repair scheme, and when the size of the memory cell exceeds a certain range, the memory cell needs to be repaired, so that the stability of the overall yield (yield) is ensured, but the real condition of the chip is not considered, and the given value is difficult to obtain the optimal result. The other is that each Design House (Design House) generally determines redundancy logic according to the recommendations of the manufacturer (foundation) based on the existing experience, and compared with the solution recommended by the manufacturer (foundation), the operation granularity is more accurate, but the situation of one-time cutting cannot be avoided, and the better effect is difficult to achieve. The existing mechanism provides that the redundancy logic is calculated according to the real chip area, but the input data needs to model the static random access memory unit according to the detailed information of a manufacturer (Foundry), complex global iteration and repeated operation are adopted, the division of the row and the column of the memory unit is not considered, the influence of repair logic, the grouping of the static memory unit and the repair logic is not considered, and the requirement of complexity is too high to be applied to the actual project. Therefore, the present application provides a method, an apparatus, a storage medium, and a terminal for repairing redundant information in a static random access memory, so as to solve the above-mentioned problems in the related art. In the technical scheme provided by the application, a preset evaluation algorithm is embedded into a realization process of a self-test built-in (MABIST) logic of a storage array, redundancy analysis of a static random access memory in the storage array is performed through shared data information to generate a redundancy result, and finally, the redundancy logic information is distributed and further optimized through the redundancy result, so that the yield of chips is improved.

The following describes in detail a method for repairing redundant information in a static random access memory according to an embodiment of the present application with reference to fig. 1 to 5. The method may be implemented by means of a computer program, and may be run on a redundant information repair device in a static random access memory based on the von neumann architecture. The computer program may be integrated into the application or may run as a separate tool-like application.

Referring to fig. 1, a flow chart of a method for repairing redundant information in a static random access memory according to an embodiment of the present application is shown. As shown in fig. 1, the method of the embodiment of the present application may include the steps of:

s101, when built-in self-test is carried out on a storage array in a chip, information data of each static random access memory in the storage array are shared;

the built-in self test is an implementation technology of testability design, and aims to detect redundant information of a static random access memory in a chip through an implementation process of a memory array built-in self test (MABIST) logic.

In a possible implementation manner, when detecting redundancy information of a static random access memory in a chip and performing logic repair, a pre-designed evaluation algorithm needs to be embedded into a storage array built-in self-test logic in the chip, the selection of the size and the type of the storage logic of a designer is based on an empirical value and a selection made by the designer according to performance requirements, and when the evaluation algorithm is implemented in a storage array built-in self-test (mabbist) implementation process, all information read in the storage array built-in self-test (mabbist) implementation process, including a storage unit type, rank information and a current redundancy scheme, are shared.

The method comprises the steps of obtaining a grouping scheme of Static Random Access Memory (SRAM) in the design in the implementation process of the built-in self test (MABIST) of the storage array in real time, and obtaining a test repair scheme of the built-in self test (MABIST) of the storage array. It is also necessary to supplement process information provided by the lowest manufacturer (foundry) required for calculating redundancy when performing a built-in self test (mabbist) implementation process, including but not limited to yield (yield) of different types of memory cells, yield (logic yield) of logic cells, physical information (memory level) of memory cells, physical information (register level) of logic cells and related defect information (defect level) and manufacturing complexity.

Further, in the design of evaluation algorithm, it can be concluded that the ratio of yield (yield) increase and area increase of Static Random Access Memory (SRAM) is much larger than the original one by calculating the simplified formula of the die (good die) passing the testThe chip can gain much more benefit from the ratio of the yield (yield) to the area of the memory. The number of dies that pass the test is formulated as:

where G represents the good die number, i.e. the number of dies that pass the test, Ychip: representing the yield of the chip, Awafer: representing the area of the wafer, Adie: representing the area of the die. The formula for calculating the number of the repaired good die is

Wherein, Gr: representing the number of good die after repair, Ylogic is the yield of logic units in the chip, Ym is the yield of storage units in the chip, dYm is the yield increased by increasing the repair of redundant units, AWafer is the area of a wafer, Adie is the area of a bare chip, and dA is the extra area introduced by increasing the redundant units and the repair logic.

From the above two equations, if: gr>G is the number of the first group,

(where A is Adie: the area of the die). The formula is further optimized in view of realism: suppose that:

(pi is the circumferential ratio, Rw is the radius of the wafer, and A is the area of the die), so that the following equation can be derived:

if the formula is further updated, an updated evaluation mode is provided:

(R is Rw represents the radius of the wafer).

S102, performing redundancy analysis according to the information data of each static random access memory to generate redundancy information required to be added by each static random access memory;

in the embodiment of the application, firstly, descending order arrangement is carried out according to the capacity of each static random access memory to generate each static random access memory after arrangement, then, parameter information shared by each static random access memory is read according to each static random access memory after arrangement, then, row and column repair calculation is carried out based on the shared parameter information to generate the weight of row and column redundancy in each static random access memory, then, iterative comparison is carried out on the weight of row and column redundancy in each static random access memory to obtain the optimal row and column redundancy weight in each static random access memory, then, ascending order arrangement is carried out on the optimal row and column redundancy weight in each static random access memory to generate a weight set after arrangement, and finally, the redundancy distribution of each static random access memory is calculated based on the weight set after arrangement to generate the redundancy information of each static random access memory.

In one possible implementation, for example, as shown in fig. 2, if a redundancy analysis algorithm is used in the implementation process of the built-in self test (mabbist) of the memory array, the tool first reads in information data of the shared Static Random Access Memory (SRAM), then performs permutation according to the size of the SRAM, performs row-column repair by default, and calculates a weight of the row-column redundancy according to the grouping, repair information, and estimated chip area information Ae of the SRAM:

wherein (Mm is a weight for calculating the row-column redundancy, Ym is a yield of the memory, dAm is an increased area of the memory cell, dAl is an increased area of the logic cell, dYm is an increased yield of the memory cell, dYl is a decreased yield of the logic cell), the row-column weight is compared, and the row-column value and the estimated chip area are compared, so that the optimal row-column redundancy allocation is found through iterative calculation.

When the weight value M_m>A_eThe current information is accessed as a backup, the next SRAM is calculated (the weight of the SRAM and the calculation of the weight are shown in FIG. 3. if the row repair or the column repair is limited, the FIG. 3 can be further simplified, the redundant information of the row and the column is not required to be calculated at the same time, and only the current information is calculatedThe information of the rows or columns is redundantly allocated. After all Static Random Access Memory (SRAM) weights are calculated, the second part of fig. 2 is entered, and sorting is performed according to the calculated weights and according to the size of the weights, using the corrected area: a. the_e＝A+ΔA_m-1Performing more refined weight calculation on determinant in safety range

To calculate M_m>A_eAnd (3) performing time redundancy distribution, namely traversing all information, then additionally calculating redundant lines and columns additionally introduced in the redundant calculation process, and acquiring the current optimal redundant solution after the processing is finished, wherein the redundant solution is redundant information required to be added by each static random access memory.

S103, distributing the redundant information to each static random access memory based on the redundant information needing to be added.

In a possible implementation manner, when the current optimal redundancy solution is obtained after the processing is completed, redundancy information allocation is performed on each static random access memory based on the redundancy information to be added, so that each repaired static random access memory is obtained.

Further, when the static random access memories are further repaired after register sharing is started, grouping information of the Static Random Access Memories (SRAM) in different modules is obtained, meanwhile, embedded self-repair analysis and self-repair logic under the current grouping is obtained, and the embedded self-test and self-repair logic under the same grouping can reduce extra area overhead introduced by the self-test logic of the Static Random Access Memories (SRAM) through sharing a repair unit. Whether the Static Random Access Memory (SRAM) between each group can pass the shared redundancy is calculated by using the weight calculated in step S102, and the area of the chip can be further optimized, thereby obtaining further optimization information. The following formula is used in optimization:

if so: gr > G is

Thus, the Static Random Access Memory (SRAM) is further optimized by using a formula close to reality:

evaluation mode for area reduction:

the specific calculation method is as shown in fig. 4, according to the obtained Static Random Access Memory (SRAM) grouping information, n (n >1) Static Random Access Memories (SRAMs) meeting the sharing requirement are found from the group, whether to continue to increase the number of the shared Static Random Access Memories (SRAMs) next step is calculated according to the currently calculated Static Random Access Memory (SRAM) weight, when the current sharing weight is less than the last sharing weight, the calculation is stopped, the last shared Static Random Access Memory (SRAM) is removed, and the sharing analysis is continued in the set until all the Static Random Access Memories (SRAMs) are analyzed completely. And under the condition that the current sharing weight value does not meet the requirement, removing the current sharing, calculating the next group of sharing strategies, and sequentially and circularly optimizing the storage units in the chip.

For example, as shown in fig. 5, fig. 5 is a logic block diagram for repairing redundant information in a static random access memory provided in the present application, and designing and storing library files, designing logic analysis, testing logic insertion, and testing logic detection are prior art, and when performing redundancy analysis by using built-in self-test in the prior art, first, manufacturing process data is obtained, and then, redundancy analysis is performed, and redundant information is obtained by calculation according to a weight in the redundancy analysis and is repaired. When the repair is complete and register sharing is turned on, further optimization is performed, making the repair more granular.

The following are embodiments of the apparatus of the present invention that may be used to perform embodiments of the method of the present invention. For details which are not disclosed in the embodiments of the apparatus of the present invention, reference is made to the embodiments of the method of the present invention.

Fig. 6 is a schematic structural diagram illustrating a device for repairing redundant information in a static random access memory according to an exemplary embodiment of the present invention. The device for restoring redundant information in the static random access memory can be realized by software, hardware or a combination of the software and the hardware to form all or part of the intelligent robot. The device 1 comprises a data sharing module 10, a redundant information generating module 20 and a redundant information repairing module 30.

The data sharing module 10 is configured to share information data of each sram in a memory array when implementing a built-in self-test for the memory array in a chip;

a redundant information generating module 20, configured to perform redundant analysis according to the information data of each static random access memory, and generate redundant information that needs to be added to each static random access memory;

and the redundant information repair module 30 is configured to allocate redundant information to each static random access memory based on the redundant information that needs to be added.

Optionally, for example, as shown in fig. 7, the apparatus 1 further includes:

an algorithm receiving module 40, configured to receive a preset redundancy evaluation algorithm;

an algorithm embedding module 50 for embedding the redundancy evaluation algorithm into built-in self-test logic for the memory array in the chip.

It should be noted that, when the apparatus for repairing redundant information in a static random access memory provided in the foregoing embodiment executes the method for repairing redundant information in a static random access memory, only the division of each functional module is taken as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the apparatus may be divided into different functional modules, so as to complete all or part of the above described functions. In addition, the device for repairing redundant information in a static random access memory provided in the above embodiments and the method for repairing redundant information in a static random access memory belong to the same concept, and details of implementation processes thereof are referred to in the method embodiments and are not described herein again.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The present invention also provides a computer readable medium, on which program instructions are stored, and when the program instructions are executed by a processor, the method for repairing redundant information in a static random access memory provided by the above-mentioned method embodiments is implemented.

The present invention also provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the method for repairing redundant information in a static random access memory according to the above-mentioned method embodiments.

Please refer to fig. 8, which provides a schematic structural diagram of a terminal according to an embodiment of the present application. As shown in fig. 8, the terminal 1000 can include: at least one processor 1001, at least one network interface 1004, a user interface 1003, memory 1005, at least one communication bus 1002.

Wherein a communication bus 1002 is used to enable connective communication between these components.

The user interface 1003 may include a Display screen (Display) and a Camera (Camera), and the optional user interface 1003 may also include a standard wired interface and a wireless interface.

The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others.

Processor 1001 may include one or more processing cores, among other things. The processor 1001 interfaces various components throughout the electronic device 1000 using various interfaces and lines to perform various functions of the electronic device 1000 and to process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 1005 and invoking data stored in the memory 1005. Alternatively, the processor 1001 may be implemented in at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 1001 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 1001, but may be implemented by a single chip.

The Memory 1005 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). Optionally, the memory 1005 includes a non-transitory computer-readable medium. The memory 1005 may be used to store an instruction, a program, code, a set of codes, or a set of instructions. The memory 1005 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described above, and the like; the storage data area may store data and the like referred to in the above respective method embodiments. The memory 1005 may optionally be at least one memory device located remotely from the processor 1001. As shown in fig. 8, the memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a redundant information repair application in a static random access memory.

In the terminal 1000 shown in fig. 8, the user interface 1003 is mainly used as an interface for providing input for a user, and acquiring data input by the user; the processor 1001 may be configured to call the application program for repairing redundant information in the sram stored in the memory 1005, and specifically perform the following operations:

and distributing redundancy information to each static random access memory based on the redundancy information needing to be added.

In one embodiment, the processor 1001, when prior to executing the when built-in self-test for a memory array in a chip, further performs the following:

receiving a preset redundancy evaluation algorithm;

In an embodiment, when the processor 1001 performs the redundancy analysis according to the information data of each static random access memory to generate the redundancy information that needs to be added to each static random access memory, the following operations are specifically performed:

In an embodiment, when the processor 1001 performs the row-column repair calculation based on the shared parameter information to generate the row-column redundancy weight in each sram, the following operations are specifically performed:

In an embodiment, when the processor 1001 calculates the redundancy distribution of the static random access memories based on the arranged weight set and generates the redundancy information of the static random access memories, the following operations are specifically performed:

In one embodiment, when performing the redundancy information allocation for the static random access memories based on the redundancy information required to be added, the processor 1001 further performs the following operations:

when register sharing is started in the chip, a shared repair unit is obtained;

if so, optimizing the area of the chip.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.

Claims

1. A method for repairing redundant information in a Static Random Access Memory (SRAM), the method comprising:

2. The method of claim 1, prior to when implementing the built-in self-test for the memory array in the chip, further comprising:

receiving a preset redundancy evaluation algorithm;

3. The method according to claim 1 or 2, wherein the performing redundancy analysis according to the information data of each sram to generate the redundancy information required to be added to each sram comprises:

4. The method according to claim 3, wherein performing row-column repair calculation based on the shared parameter information to generate a weight of row-column redundancy in each SRAM comprises:

5. The method according to claim 3, wherein the calculating the redundancy distribution of the static random access memories based on the arranged weight sets and generating the redundancy information of the static random access memories comprises:

6. The method according to claim 1, wherein after the allocating redundancy information to each sram based on the redundancy information to be added, further comprises:

when register sharing is started in the chip, a shared repair unit is obtained;

if so, optimizing the area of the chip.

7. An apparatus for repairing redundant information in a static random access memory, the apparatus comprising:

8. The apparatus of claim 7, further comprising:

9. A computer storage medium, characterized in that it stores a plurality of instructions adapted to be loaded by a processor and to perform the method steps according to any of claims 1 to 6.

10. A terminal, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and to perform the method steps of any of claims 1 to 6.