CN102856226A - Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module - Google Patents
Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module Download PDFInfo
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Abstract
The invention discloses a testing device of a 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with a signal rebounding module. A sending end is connected with a receiving end by through a plurality of silicon vias TSVs. The sending end comprises a first tested chip, a decoder, a control unit CU, a latch D and a bidirectional switch DSW. The receiving end comprises a second tested chip and a signal rebounding module. The signal rebounding module comprises a signal generator F, a plurality of delay cells and a plurality of three-state gates. The upper ends of the TSVs are connected with the delay cells M and the signal generator F at the receiving end. The lower ends of the TSVs are connected with the decoder and the DSW at the sending end. The decoder, the latch D and the DSW are connected with the CU. The latch D is further connected with the DSW. The testing device of the 3D-SIC through silicon vias provided with the signal rebounding module can effectively solve the problem that failed TSVs in the 3D chip preparing process are hard to detect effectively, and has the advantages of smaller area and practical expenses and lower power consumption and the like.
Description
Technical field
The present invention relates to the testing apparatus that a kind of 3D-SIC that is provided with signal bounce-back module crosses the silicon through hole.
Background technology
Along with chip manufacturing process ground development, the size of chip constantly reduces, and performance improves constantly, the splendidness that has continued Moore's Law nearly half a century.Yet the semiconductor transistor size is indicating that near nanoscale manufacture of microchips will run into a great bottleneck, and Moore's Law might lose efficacy at this point.In order to continue Moore's Law, continue to promote the performance of chip, the 3D chip arises at the historic moment.In integrated circuit in the past, all elements all are in one plane to distribute, and namely are called the 2D integrated circuit.And the design of 3D integrated circuit is different from the graphic design method of 2D integrated circuit, and it is with a plurality of wafers (Die) vertical stacking, and is by silicon through hole (TSV) interconnection, vertically integrated to realize.Thereby obtain less volume, better power consumption and radio-frequency performance.
The vertical stacking mode of chip can be divided into face-to-face stacking (Face-to-Face Bonding), in the face of the back of the body stacking (Face-to-Back Bonding) and back-to-back stacking (Back-to-Back Bonding) three kinds.Wherein stacking face-to-face is the metal level vertical stacking formation of two integrated circuits, does not need to interconnect by TSV.And the metal level that is not two integrated circuits in the face of the stacking and back-to-back stack manner of the back of the body directly contacts, so must interconnect by TSV.In chip-stacked technology, two-layer above integrated circuit stacking just inevitably will be used in the face of the stacking and back-to-back stack manner of the back of the body.This shows the importance of TSV in the 3D integrated circuit.
TSV technology (Through-Silicon Vias, cross silicon through hole) is by between nude film (Die) and the nude film, between wafer (Wafer) and the wafer, make vertical conducting between wafer and the nude film, realizes the state-of-the-art technology that interconnects between the chip.A TSV just represents a data link on the vertical direction, is used for signal transmission.Encapsulate and use the superimposing technique of salient point different from IC in the past, TSV can make chip minimum in three-dimensional stacking density maximum, overall dimension, and greatly improves the performance of chip speed and low-power consumption.Yet because the restriction of technology, fracture may appear in TSV in manufacture process, injects inhomogeneous with the impurity situation is arranged, cause occurring short circuit and breaking phenomena.Can not guarantee that all TSV that make are intact.The failure problems of TSV has a lot, is injecting the conductive copper stage, exists to inject the insufficient TSV of causing fracture or the very very thin problem of TSV, is easy to break down when causing the signal transmission.The last process that also has a skiving in the making of TSV, the diameter of TSV generally is 4 ~ 8um, the process that thins easily causes the fracture of TSV.In the stacking process of wafer, very difficult but tens thousand of TSV will align because the two-layer TSV that requires aims at up and down, but also be in the so little situation of the diameter of TSV.Because TSV is the highdensity interconnection line of a class, also can be with thermal coupling near the TSV it when TSV self produces, thus heat near it interconnection line.It is reported, every increase by 10 degree, delay will increase by 5%, hydraulic performance decline 30%.Therefore heat dissipation problem also is the problem that TSV needs to be resolved hurrily.Because the inefficacy of single TSV might cause two known wafers that can work or chip at stacking rear cisco unity malfunction, cost can rise rapidly like this.
Three-dimensional stacked integrated circuit (3D-SIC) mainly adopted silicon through hole technology to realize module interconnection in vertical direction, but the silicon through hole all might occur losing efficacy in manufacture process or binding after-stage, causes whole chip to work.In order to improve the rate of finished products of 3D chip, reduce manufacturing cost, need to it be tested the different phase in manufacture process, mainly comprise the test of following three phases: test (post bond test) and final test (final test) after test (pre bond test) before the binding, the binding.
1, test (pre bond test), namely flawless kernel test (Known Good Die, KGD) before the binding.Because crossing the making of silicon through hole needs through the series of process step, wherein each step might go wrong, such as injecting the conductive copper stage, exist the problems such as the insufficient TSV of the causing fracture of injection or TSV are too very thin, need to test binding front chip, removing problematic chip, thereby reduce cost, boost productivity.
2, test (post bond test) after the binding, namely flawless stacking test (Known Good Stack, KGS).In the multilayer chiop binding procedure, may cause TSV short circuit or open circuit conditions to occur because binding pressure is excessive, the phenomenons such as insulation or TSV misalignment appear in the binding interface, so that signal can't normal transmission, so will test binding rear chip.
3, final test (final test) is tested last packaged chip exactly, determines that finally which chip is qualified.
Wherein, the probability that TSV breaks down after binding is higher, and TSV is as a kind of mode of important 3D IC module communication, and therefore test seems particularly important after the binding.In order not affect the chip normal operation, in chip, add test structure, the pattern switching mode of utilization realizes control.
Test after the binding for TSV, mainly contain following several method in the research approach both domestic and external:
1, by using BIST(Built-in Self Test, built-in self-test) method, after binding, add identical test structure in the layers of chips, utilize control signal with test vector maker (TPG, Test-Pattern Generator) comparison before and after the test vector that generates transmits, and then reach the purpose of test, realize higher fault coverage.But this method, area overhead and displacement power consumption are larger;
2, the TSV two ends add identical test structure after binding, utilize the voltage cutting techniques to realize test; But this method is to be based upon on certain theoretical foundation, and precision is not high enough, and control signal is complicated, implements difficulty;
3, pass through to increase at every one deck chip the method on scan chain and scanning island, utilize these scan chains and scanning island to transmit control signal and transmit the comparison of front and back, can effectively reach the purpose of test TSV.But this method area overhead is large;
4, by two kinds of TSV are carried out the RC modeling, realize testing before the TSV binding with voltage division and electric charge technology of sharing, but owing to having noise in the side circuit, cause calculating to reflect actual conditions by theoretical value, accuracy can not be guaranteed; Fault coverage is lower.
Summary of the invention
The present invention is the weak point that exists in the above-mentioned prior art for avoiding, and provides a kind of 3D-SIC that is provided with signal bounce-back module to cross the testing apparatus of silicon through hole, to solve the problem of inefficacy TSV being carried out effective detection difficult in the 3D chip manufacturing proces.
The present invention is the technical solution problem, provides a kind of 3D-SIC that is provided with signal bounce-back module to cross the testing apparatus of silicon through hole.
The 3D-SIC that is provided with signal bounce-back module crosses the testing apparatus of silicon through hole, and its design feature is to comprise transmitting terminal and receiving terminal; Crossing silicon through hole TSV by many between described transmitting terminal and the receiving terminal is connected; Described transmitting terminal comprises the first chip under test, decoder, control unit CU, latch D and bidirectional switch DSW; Described receiving terminal comprises the second chip under test and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, a plurality of delay cell M and a plurality of triple gate;
The described upper end of crossing silicon through hole TSV is connected with signal generator F with the delay cell M of described receiving terminal, and the described delay cell M all triple gate by separately is connected with described signal generator F;
The described lower end of crossing silicon through hole TSV is connected with bidirectional switch DSW with the decoder of described transmitting terminal; Described decoder, latch D and bidirectional switch DSW all are connected with described control unit CU; Described latch D also is connected with described bidirectional switch DSW.
The testing apparatus that the 3D-SIC that is provided with signal bounce-back module of the present invention crosses the silicon through hole also has following technical characterstic.
Described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
Compared with the prior art, beneficial effect of the present invention is embodied in:
The present invention proposes a kind of testing apparatus, test for binding after-stage silicon through hole, the irreversibility of utilizing signal in conductor, to transmit, increase the bounce-back module at signal receiving end, by apply different test and excitation twice at transmitting terminal, utilize trigger and MUX that twice Output rusults carried out XOR, reach test purpose.The present invention is respectively 0 and 1 by single TSV being applied twice different test vectors.The result who compares two secondary responses by the XOR gate logic, if output is 0, expression has fault; If when output 1, the expression fault-free.
3D-SIC of the present invention crosses the testing apparatus of silicon through hole, the irreversibility of utilizing signal in conductor, to transmit, increase the bounce-back module at signal receiving end, by apply different test and excitation twice at transmitting terminal, utilize trigger and MUX that twice Output rusults carried out XOR, reach test purpose, effectively solved a difficult problem that in the 3D chip manufacturing proces, inefficacy TSV is effectively detected.Testing apparatus of the present invention accomplishing under the prerequisite that inefficacy TSV is effectively detected, have area and put into practice expense less, the advantage such as power consumption is lower.
Description of drawings
Fig. 1 is the overall structure stereogram of testing apparatus of the present invention.
Fig. 2 is the TSV piece sending end structure of testing apparatus of the present invention.
Fig. 3 is the enlarged drawing of bus lower end module among Fig. 2.
Fig. 4 is the TSV piece receiving terminal structure of testing apparatus of the present invention.
Label in accompanying drawing 1～accompanying drawing 4: 1 transmitting terminal, 101 first chip under test, 102 decoders, 2 receiving terminals, 201 second chip under test, 202 triple gates.
Below by embodiment, the invention will be further described.
Embodiment
Participate in Fig. 1～Fig. 4, the 3D-SIC that is provided with signal bounce-back module crosses the testing apparatus of silicon through hole, comprises transmitting terminal 1 and receiving terminal 2; Crossing silicon through hole TSV by many between described transmitting terminal and the receiving terminal is connected; Described transmitting terminal comprises the first chip under test 101, decoder 102, control unit CU, latch D and bidirectional switch DSW; Described receiving terminal 2 comprises the second chip under test 201 and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, a plurality of delay cell M and a plurality of triple gate 202;
The described upper end of crossing silicon through hole TSV is connected with signal generator F with the delay cell M of described receiving terminal, and the described delay cell M all triple gate 202 by separately is connected with described signal generator F;
The described lower end of crossing silicon through hole TSV is connected with bidirectional switch DSW with the decoder 102 of described transmitting terminal; Described decoder 102, latch D and bidirectional switch DSW all are connected with described control unit CU; Described latch D also is connected with described bidirectional switch DSW.
Described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
Principle foundation of the present invention: TSV may have three kinds of situations after binding: stuck at 0 fault, stuck at 1 fault and fault-free.In order to improve fault coverage, the present invention is respectively 0 and 1 by single TSV being applied twice different test vectors.The result who compares two secondary responses by the XOR gate logic.
The overall architecture of structure of the present invention: in order describing the problem better, TSV to be carried out the logic function piecemeal, for example to be divided into the 4x4 mode, double-layer structure.Fig. 1 is the overall architecture of test structure.Wherein CU represents unit of testing and controlling in the bottom, and test and excitation mainly is provided, test control signal and test response analysis.D represents XOR, multichannel selection and latch logical network, and main preservation response and response ratio are.DECODER represents decoder, and mainly screening wherein, delegation tests.DSW is bidirectional switch.M is delay cell in the upper strata.F enables the control signal generator.Die1 is the first chip under test, and Die2 is the second chip under test.Delay cell is delay cell M among Fig. 4.
TSV piece sending end structure as shown in Figure 2, wherein FG is the square wave maker, generates 0 and 1 twice test and excitation.SWCM is the bidirectional switch control module.AG is the address signal that generates decoder.TC is test control and testing analysis module.Each the TSV end points that wherein is in transmitting terminal has a bidirectional switch logic.Each column address conductor with provide the bus infall of test and excitation that a bidirectional switch DSW is arranged.As shown in Figure 3 be the enlarged drawing of the module in Fig. 2 bus below, every row of bus below have an XOR, multichannel to select and latching logic, final test signal all is connected on separately the NMOS grid, the drain electrode of rightmost NMOS connects VDD, and the source electrode of leftmost NMOS is connected on the test controller.Among Fig. 2 and Fig. 3, C is the level pulse signal, and C ' is its complementary signal, and Q is the output signal of transparent D lock.
TSV piece receiving terminal structure as shown in Figure 4, F generates the generator enable control signal according to the TSV signal.The public delay unit M of each row TSV.Generate different enable signals by F and control complementary triple gate, realize the signal bounce-back.
Specific implementation process of the present invention is: at first send test massage 0 by transmitting terminal, after receiving terminal receives signal, by the signal rebounding device signal is back to transmitting terminal, transmitting terminal is kept in the register after receiving the signal that returns.Then transmitting terminal receives the signal that receiving terminal rebounds and to sending test massage 1 with comprehending.This signal and the signal that is kept in the register are before carried out XOR, if the result is 1, then expression time TSV is normal; If be 0, represent that then this TSV lost efficacy.
As shown in Figure 2, transmitting terminal produces the test and excitation signal.The address generator AG of the controller inside of the control unit CU in the TSV piece sending end structure generates the decode address of decoder and selects information, acts on the Y3 address wire, and wherein Y2, Y1 and Y0 are invalid.
When testing for the first time, square wave maker FG at first generates on the bus that 0 test vector acts on connection, bidirectional switch control module SWCM sends a high level signal, make the bidirectional switch that is on the bus be in conducting state, X0, X1, X2 and X3 select on the line be 0 signal, still only have Y3 to select the TSV on the line just can obtain this signal at this moment.The bidirectional switch that is on the Y3 holding wire is in conducting state, and test signal is transferred to the receiving terminal module along TSV.
Receiving terminal bounce-back test and excitation signal.In the receiving terminal module, X selects the TSV end points on the line to be connected on the enable signal controller F.When the capable TSV of transmitting terminal has test signal, act on the enable signal controller, produce a high level signal this moment, and complementary triple gate is in conducting state.Test signal is transmitted along delay unit, occurs the situation in loop in delay unit for fear of signal, chooses pulse duration and the delay unit time consistency of enable signal controller F, when returning from delay unit signal one curb TSV out; Triple gate is arrived again on another road, but because this Time Controller produces a high level signal, the triple gate cut-off.The situation of signal with regard to not occurring circling round avoided the interference of signal and reduced power consumption like this.
Then, transmitting terminal is processed corresponding test signal.When signal returns, generate a low level signal by the square wave maker FG of the controller inside of control unit CU, act on the bidirectional switch on the bus, make it be in cut-off state.Y3 selects the situation that each TSV inverse signal on the line just can not occur disturbing like this.Test response selects logic to be saved in the transparent D-latch by multichannel for the first time.
When testing for the second time, square wave maker FG generates 1 test vector and acts on the bus, and process thereafter is with test process is identical for the first time.When the second time, test response signal arrived XOR and multichannel selection logic, control unit CU provided a high level C pulse signal, and this moment, primary test response result just was transferred to an input of XOR.By twice test response result before and after relatively, at the output of XOR individual comparison signal is arranged.These Output rusults all are connected to the grid of NMOS separately.When grid is high level, conducting; Otherwise, cut-off.Utilize twice response results analytical table of the three kinds of situations in front as can be known, if out of order words, the source electrode of Far Left NMOS is individual 0; If trouble-free words are individual 1.Whether analyze Y3 by test controller TC has fault to exist.After the Y3 test finishes, and then carry out respectively the test of Y2, Y1 and Y0.
During implementation, determine that at the design initial stage TSV is divided into several row of several row, the number according to TSV in the position of each TSV piece and the corresponding TSV piece is divided into a TSV chain with a plurality of TSV.
At the transmitting terminal of TSV, connect all TSV chains with a decoder, and the square wave maker is set, generate 0 and 1 twice test and excitation.Each the TSV end points that wherein is in transmitting terminal has a bidirectional switch logic, each column address conductor with provide the bus infall of test and excitation that a bidirectional switch is arranged, every row of bus below have an XOR, multichannel to select and latching logic, final test signal all is connected on separately the NMOS grid, the drain electrode of rightmost NMOS connects VDD, and the source electrode of leftmost NMOS is connected on the test controller.
At the receiving terminal of TSV piece, there is one to generate the generator F enable control signal according to the TSV signal, the public delay unit M of each row TSV generates different enable signals by signal generator and controls complementary triple gate, realizes the signal bounce-back.
The detailed step of test is as follows:
1) address generator in the TSV piece sending end structure generates the decoding address selecting information, acts on the TSV chain, and other TSV chains are invalid.The square wave maker at first generates on the bus that 0 test vector acts on connection, the bidirectional switch control module sends a high level signal, make the bidirectional switch that is on the bus be in conducting state, TSV on the TSV chain of being chosen by decoder this moment obtains this signal, and test signal is transferred to the receiving terminal module along TSV.
2) in the receiving terminal module, when the capable TSV of transmitting terminal has test signal, act on the enable signal controller, produce a high level signal this moment, and complementary triple gate is in conducting state.Test signal is transmitted along delay unit, and the signal bounce-back is postbacked sending end.
3) in initiator block, test response selects logic to be saved in the D-latch by multichannel for the first time, and then 1 test vector of square wave maker FG generation acts on the bus, and the back process is with for the first time identical.When test response signal arrived XOR and multichannel and selected logic the second time, relatively before and after twice test response result, at the output of XOR individual comparison signal is arranged.These Output rusults all are connected to the grid of NMOS separately.When grid is high level, conducting, otherwise, cut-off.Utilize twice response results analytical table of the three kinds of situations in front as can be known, if out of order words, the source electrode of Far Left NMOS is individual 0; If trouble-free words are individual 1; Again other TSV chain is implemented above-mentioned 1 to 4 testing procedure.
At sending module, generate a low level signal by square wave maker FG, act on the bidirectional switch on the bus, make it be in cut-off state, the situation that each TSV inverse signal on such TSV chain just can not occur disturbing.
Claims (2)
1. the 3D-SIC that is provided with signal bounce-back module crosses the testing apparatus of silicon through hole, it is characterized in that, comprises transmitting terminal (1) and receiving terminal (2); Crossing the silicon through hole by many between described transmitting terminal and the receiving terminal is connected; Described transmitting terminal comprises the first chip under test (101), decoder (102), control unit CU, latch D and bidirectional switch DSW; Described receiving terminal comprises the second chip under test (201) and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, a plurality of delay cell M and a plurality of triple gate (202);
The described upper end of crossing the silicon through hole is connected with signal generator F with the delay cell M of described receiving terminal, and the described delay cell M all triple gate (202) by separately is connected with described signal generator F;
The described lower end of crossing the silicon through hole is connected with bidirectional switch DSW with the decoder (102) of described transmitting terminal; Described decoder (102), latch D and bidirectional switch DSW all are connected with described control unit CU; Described latch D also is connected with described bidirectional switch DSW.
2. the 3D-SIC that is provided with signal bounce-back module according to claim 1 crosses the testing apparatus of silicon through hole, it is characterized in that, described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
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| CN103323731A (en) * | 2013-06-19 | 2013-09-25 | 西安理工大学 | Automatic detection method for through silicon via (TSV) defects of full-digital 3D integrated circuit |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
| CN104795342A (en) * | 2015-04-30 | 2015-07-22 | 合肥工业大学 | Testing device with Through Silicon Vias (TSV) self-test function and testing method |
| CN105047577A (en) * | 2015-07-08 | 2015-11-11 | 合肥工业大学 | Device used for TSV self detection and classification check |
| CN105206600A (en) * | 2014-06-30 | 2015-12-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor test structure |
| CN105632942A (en) * | 2014-10-31 | 2016-06-01 | 北京自动化控制设备研究所 | Three-dimensional packaging method of navigation computer chip |
| CN106199382A (en) * | 2016-07-06 | 2016-12-07 | 合肥工业大学 | Silicon through hole test structure before a kind of binding based on vernier ring |
| CN106556790A (en) * | 2015-09-24 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of silicon hole sensor and detection method, electronic installation |
| CN112765928A (en) * | 2019-11-06 | 2021-05-07 | 瑞昱半导体股份有限公司 | Test pattern generation method and failure model generation method |
| CN113053772A (en) * | 2021-03-18 | 2021-06-29 | 西安电子科技大学 | Test structure for packaged through-silicon-via laminated chip |
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| CN103323731A (en) * | 2013-06-19 | 2013-09-25 | 西安理工大学 | Automatic detection method for through silicon via (TSV) defects of full-digital 3D integrated circuit |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
| CN103780243B (en) * | 2014-01-28 | 2016-07-06 | 合肥工业大学 | A kind of 3D chip redundancy silicon through hole fault-tolerant architecture with transfer signal function |
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| CN105632942A (en) * | 2014-10-31 | 2016-06-01 | 北京自动化控制设备研究所 | Three-dimensional packaging method of navigation computer chip |
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| CN105047577A (en) * | 2015-07-08 | 2015-11-11 | 合肥工业大学 | Device used for TSV self detection and classification check |
| CN105047577B (en) * | 2015-07-08 | 2017-11-28 | 合肥工业大学 | It is a kind of to be used for TSV Autonomous tests and the device of classification check |
| CN106556790A (en) * | 2015-09-24 | 2017-04-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of silicon hole sensor and detection method, electronic installation |
| CN106199382A (en) * | 2016-07-06 | 2016-12-07 | 合肥工业大学 | Silicon through hole test structure before a kind of binding based on vernier ring |
| CN112765928A (en) * | 2019-11-06 | 2021-05-07 | 瑞昱半导体股份有限公司 | Test pattern generation method and failure model generation method |
| CN113053772A (en) * | 2021-03-18 | 2021-06-29 | 西安电子科技大学 | Test structure for packaged through-silicon-via laminated chip |
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