CN105047577A - Device used for TSV self detection and classification check - Google Patents
Device used for TSV self detection and classification check Download PDFInfo
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- CN105047577A CN105047577A CN201510400049.0A CN201510400049A CN105047577A CN 105047577 A CN105047577 A CN 105047577A CN 201510400049 A CN201510400049 A CN 201510400049A CN 105047577 A CN105047577 A CN 105047577A
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- H—ELECTRICITY
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Abstract
The invention discloses a device used for TSV self detection and classification check. TSVs are connected between an upper chip layer and a lower chip layer; the top ends of the TSVs in the upper chip layer are connected in pairs so as to form a closed ring, and an upper common point O is connected with the top ends of the TSVs respectively, and the upper chip layer is adopted as a receiving end; the upper common point O is connected with a time delay device so as to be adopted a roof of joint rebound of the TSVs; on the lower chip layer, an exclusive-OR gate is connected between the lower end points of every two TSVs, the output ends of the exclusive-OR gates are connected with the triggering ends of respective triggers in a one-to-one correspondence manner, and the output ends of the triggers are connected with a decoder; a lower common point F on the lower chip layer is connected with the lower ends of the TSVs respectively, and the lower chip layer is adopted as a receiving end; the top end of one of the TSVs is connected with the time delay device formed by a buffer and an phase inverter, and the lower end of the TSV is connected with a data comparison device. With the device of the invention adopted, a testing process can be simplified, and testing cost can be reduced, and testing precision can be guaranteed.
Description
Technical field
The present invention relates to a kind of device for TSV Autonomous test and classification check.
Background technology
Along with the development of ic manufacturing technology, the size of transistor also constantly reduces, and very lagre scale integrated circuit (VLSIC) (verylargescaleintegratedcircuit, VLSIC) is developed rapidly; But there is bottleneck according to international semiconductor way for development line chart (ITRS) report display process in recent years.In order to continue Moore's Law, promotion semiconductor industry is advanced, there has been proposed three-dimensional (three-dimensional, 3D) the concept of IC, this technology was mainly passed through silicon through hole (throughsiliconvia, TSV) technology and was realized modular unit connection communication in vertical direction.3DIC, as novel semi-conductor product, has continued Moore's Law, has had plurality of advantages compared to 2DIC, but also brings many challenges.
3D integrated circuit is achieved the vertical stacking of circuit devcie layer and is realized the perpendicular interconnection of device layer by TSV.The potential benefit of vertical stacking mode is: reduce bus length, improves interconnection density and reduces propagation delay, improving performance, reducing power consumption.Advantages such as although 3DIC have high-performance, low-power consumption, the uniqueness of its structure brings very large challenge to test problem, and such as test structure is complicated, and testing cost is excessively high.
Silicon through hole technology (TSV) is by between chip and chip, vertical conducting is made between wafer and wafer, realize the state-of-the-art technology of the interconnection between chip, because TSV can make chip stacking at three-dimensional, thus transistor density in unit are is increased, the interconnect length between chip shortens, overall dimension also reduces thereupon, and greatly improve chip speed, improve power consumption and performance, become the most noticeable a kind of technology in current Electronic Encapsulating Technology.Use TSV technology can be the numerous benefit of chip belt, if reduce package dimension, high frequency characteristics be outstanding, reduces transmission delay, reduces noise, and reduce the power consumption of chip, thermal expansion reliability is high.
But current TSV technology is non-full maturity also, in TSV preparation process, there are two kinds of typical defects: insulating barrier circuit defect and salient point open circuit defect.The Crack cause of these two kinds of defects is: TSV before bonding preparation may exist insulating layer growth flaw and sidewall slight crack, and the change of bonding material resistance or misalignment all may form TSV defect after bonding.Because TSV is the highdensity interconnection line of a class, TVS self to produce while heat also can by thermal coupling to it near TSV in, thus the interconnection line temperature near it is raised.It is reported, temperature often raises 10 degree, and delay will increase by 5%, hydraulic performance decline 30%, and therefore dispelling the heat also is one of TSV problem demanding prompt solution.Because single TSV lost efficacy, the known wafer that can normally work or chip may be caused at heap poststack cisco unity malfunction, cost is sharply increased.
In the manufacture process of chip or binding after-stage, TSV likely breaks down and TSV was lost efficacy, and causes chip normally to work.In order to improve the rate of finished products of chip, reduce manufacturing cost, the different phase manufacturing at TSV and bind is needed to test it, mainly comprise the test of following four-stage: test (pre-bondtest) before binding, (mid-bondtest) is tested, test (post-bondtest) and packaging and testing (finaltest) after binding in binding.
Before binding, test refers to: test single nude film, filter out trouble-free nude film, stacking for next step.Namely flawless kernel test (KnownGoodStack).
In binding, test refers to: to a n layer chip, two individual layer 2D die stacks being formed together the 3D chip semi-finished product of 2 layers from using TSV technology, to the 3D chip semi-finished product of formation (n-2) layer, in the process, each newly stacking 1 layer of 2D nude film is on existing 3D chip semi-finished product, all need and then once to test, carry out altogether (n-2) secondary, with guarantee pile poststack formed the half-finished correctness of 3D chip.This stacking process is repeatedly " in binding " process.Test is in the process " testing in binding ".
After binding, test refers to: for getting rid of last stacking issuable fault, once comprehensively tests the complete 3D chip structure formed.
Packaging and testing refer to: by the 3D chip of " after binding test ", after encapsulation link, once test the complete 3D chip of encapsulation again.This test terminates, and the chip by test can be consigned to user and use.
Wherein, the maximum probability that TSV breaks down in binding procedure, therefore in binding, test seems particularly important.Testing as a kind of new measuring technology in binding, not affecting under the prerequisite that chip normally works, can add test structure in the chips, Land use models switches and realizes controlling.
Following several situation is had for test in TSV binding in prior art:
One be, built-in self-test (Built-inSelfTest): implanting related functional circuits during design in circuit for providing the technology of selftest function, reducing the degree of dependence of device detection to automatic test equipment (ATE) with this.But this technology needs extra circuit to take valuable area, needs extra pin, also may there is test blindspot.
Two are, after binding, TSV two ends add identical test structure, utilize voltage division technology to realize test.But this method precision is not high enough, control signal is complicated, realizes difficulty.
Three be, on every one deck chip, increase scan chain and scanning island, utilize them to transmit control signal to carry out and to compare before and after transmitting thus to reach the object of test TSV, but this method area overhead is larger.
Four be, carry out RC modeling to two kinds of TSV, utilize voltage division and charge sharing techniques to realize test before TSV binding, but there is noise in side circuit, utilize theoretical value to reflect actual conditions, accuracy cannot ensure, fault coverage is lower.
Summary of the invention
The present invention is the weak point for avoiding existing for above-mentioned prior art, provides a kind of device for TSV Autonomous test and classification check, to simplifying test process, reduce testing cost, and can ensure measuring accuracy.
The present invention is that technical solution problem adopts following technical scheme:
The feature that the present invention is used for the device of TSV Autonomous test and classification check is:
Arrange a column construction, the support of described column construction is each TSV, by chip layer and lower chip layer in described each TSV connection; In upper chip layer, the top of each TSV is connected to form a closed-loop between two, and using a fixing point as upper public some O altogether, described upper public some O is altogether connected with the top of all each TSV, respectively as the terminal that each TSV is common, using described upper chip layer as receiving terminal; Altogether public some O connects a time-delay mechanism be composed in series by even number of inverters on described, as the top of the common bounce-back of all TSV;
In lower chip layer, the lower end of each TSV forms a corresponding virtual ring, described virtual ring connects an XOR gate between the lower extreme point of every two TSV, the output of each XOR gate is connected to the trigger end of respective trigger correspondingly, and the output of each trigger is connected on a decoder; Described lower chip layer has a fixing point as lower public some F altogether, described lower public some F is altogether connected with the lower end of all each TSV, respectively as the common source point of each TSV, using described lower chip layer as transmitting terminal;
The time-delay mechanism that the top of a TSV wherein connects buffer and is made up of inverter, connect a data comparison means in lower end, described data comparison means is made up of triple gate E, trigger and XOR gate.
The feature that the present invention is used for the method for testing of the device of TSV Autonomous test and classification check is: squeeze into TSV from source point by signal, transmit through TSV, to rebound all TSV through common terminal again, respectively the signal that two adjacent TSV transmission are returned is compared by XOR gate in lower chip layer, the result compared separately is transferred in the trigger connected separately, according to unified clock signal, signal in trigger is squeezed into decoder simultaneously, obtain the result of decoding, whether similarly judged between the TSV that mutually compares by the result comparing decoding, described similar referring to is all failure classes or is all non-faulting class, judge TSV by carrying out Autonomous test to wherein TSV whether fault is as first step judged result, recycle described first judged result and judge all the other all TSV whether fault.
Compared with the prior art, beneficial effect of the present invention is embodied in:
1, the test structure in the present invention is not when using complicated levels concurrency controlling mechanism, TSV realizes by standard modular test the self-test realizing vertical direction between two-layer up and down, greatly simplify test structure, reduce the too complicated and test risk that causes of controlling mechanism because of design, the TSV self-test of similar rebounding type can be realized separately, improve the reliability of test, and modular testing has run through the life cycle of whole SoC, can simplify test and follow-up module can reuse identical modularity.
2, the test structure in the present invention is classified by TSV by twice concurrent testing, then single TSV whether fault can be measured very easily by TSV Autonomous test, the failure condition other TSV is inferred again according to classification results, a point situation concurrent testing effectively can shorten the testing time like this, and the test structure proposed in the present invention decreases the dependence to tester, thus significantly reduces testing cost.
Accompanying drawing explanation
Fig. 1 is that testing apparatus of the present invention is distributed in two-layer overall structure figure;
Fig. 2 a goes up TSV apex structure schematic diagram in chip layer in the present invention;
Fig. 2 b descends TSV bottom structural representation in chip layer in the present invention;
Fig. 2 c in the present invention, lower chip layer is total to public some F syndeton schematic diagram under TSV bottom;
Fig. 3 is testing apparatus structural representation of the present invention;
Fig. 4 is the Autonomous test structure chart of TSV_3 in the present invention;
Fig. 5 is that in the present invention, each TSV carries out the precedence diagram tested;
Embodiment
The version of the device for TSV Autonomous test and classification check in the present embodiment is:
As shown in figures 1 and 3, arrange a column construction, the support of described column construction is each TSV, by chip layer L1 and lower chip layer L2 in described each TSV connection.
As shown in figs 2 a and 3, in upper chip layer L1, the top of each TSV is connected to form a closed-loop between two, using a fixing point as upper public some O altogether, described upper public some O is altogether connected with the top of all each TSV, respectively as the terminal that each TSV is common, using described upper chip layer L1 as receiving terminal; Altogether public some O connects a time-delay mechanism be composed in series by even number of inverters on described, as the top of the common bounce-back of all TSV.
As shown in Fig. 2 b, Fig. 2 c, Fig. 3 and Fig. 4, on lower chip layer L2, the lower end of each TSV forms a corresponding virtual ring, described virtual ring connects an XOR gate between the lower extreme point of every two TSV, the output of each XOR gate is connected to the trigger end of respective trigger correspondingly, and the output of each trigger is connected on a decoder; Described lower chip layer L2 has a fixing point as lower public some F altogether, described lower public some F is altogether connected with the lower end of all each TSV, respectively as the common source point of each TSV, using described lower chip layer as transmitting terminal.
As shown in Figure 3, the time-delay mechanism that the top of a TSV wherein connects buffer and is made up of inverter, connect a data comparison means in lower end, described data comparison means is made up of triple gate E, trigger and XOR gate.
The method of testing of the device for TSV Autonomous test and classification check in the present embodiment is: squeeze into TSV from source point by signal, transmit through TSV, to rebound all TSV through common terminal again, respectively the signal that two adjacent TSV transmission are returned is compared by XOR gate in lower chip layer, the result compared separately is transferred in the trigger connected separately, according to unified clock signal, signal in trigger is squeezed into decoder simultaneously, obtain the result of decoding, whether similarly judged between the TSV that mutually compares by the result comparing decoding, described similar referring to is all failure classes or is all non-faulting class, judge TSV by carrying out Autonomous test to wherein TSV whether fault is as first step judged result, recycle described first judged result and judge all the other all TSV whether fault.
As shown in Figure 3, for 4 TSV in the present embodiment, TSV_1 respectively, TSV_2, TSV_3, TSV_4, adopt 4-16 line decoder, the bottom of each TSV is on lower chip layer L2, the bottom A1 of each TSV, B1, C1, D1 is connected by XOR gate, and connection signal generator, XOR gate connects trigger DFF-1 respectively, DFF-2, DFF-3, DFF-4, multiple trigger connects 4-16 line decoder MSI simultaneously, the i.e. bottom A1 of TSV_1 and TSV_2, B1 is connected by XOR gate S1, the bottom B1 of TSV_2 and TSV_3, C1 is connected by XOR gate S3, the bottom C1 of TSV_3 and TSV_4, D1 is connected by XOR gate S4, the bottom D1 of TSV_4 and TSV_1, A1 is connected by XOR gate S2, A1 simultaneously, B1, C1, D1 is connected with the signal generator be on lower common point F, XOR gate S1, S2, S3, S4 respectively with trigger P1, P2, P3, P4 is connected, upper common point O is connected in series inverter T1, T2, T3 and T4.
Be illustrated in figure 4 the TSV_3 Autonomous test in the present embodiment, the upper end of TSV_3 connects the time-delay mechanism be made up of inverter M1, M2, M3 and M4, lower end connects a data selection means, and data selection means is made up of trigger dff-1, trigger dff-2, trigger dff, XOR gate S5 and triple gate E.
Test philosophy in the present embodiment: TSV_1 and TSV_2, TSV_4 can walk abreast survey, TSV_3 and TSV_2, TSV_4 can concurrent testings, and can concurrent testing TSV3 whether fault when TSV_1 and TSV_2, TSV_4 test, twice concurrent testing can shorten the testing time greatly.
As shown in Figure 5, test process:
Step 1: produce initialize signal by signal generator and be transferred in TSV_1 and TSV_3.Signal in TSV_1 arrives top, and on top, the time-delay mechanism of common point O, reflects back in TSV_2 and TSV_4.The signal that TSV_2 transmission is returned on lower chip layer L2 and initialize signal carry out XOR at S1, and the result obtained is stored in trigger DFF-1; The signal that TSV_4 transmission is returned and initialize signal carry out XOR at S2, and the result obtained is stored in trigger DFF-2.Meanwhile, triple gate E initial condition is connected state, and initialize signal is first stored in trigger dff-1 and dff-2 of TSV_3 lower end, and signal arrives receiving terminal through TSV_3.TSV_3 lower end is got back in bounce-back through the time-delay mechanism be made up of inverter, now triple gate E is closed, therefore what deposit in dff-1 is initialize signal, and what deposit in dff-2 is the signal reflected, signal in dff-1 and dff-2 is carried out XOR at S5, judges whether TSV_3 breaks down by the result of XOR.
Step 2: produce by signal generator the bottom that initialize signal is sent to TSV_3, signal is reflected back TSV_2 and TSV_4 through common top.The signal that TSV_2 transmission is returned on lower chip layer L2 and initialize signal carry out XOR at S3, and the signal that TSV_4 transmission is returned and initialize signal carry out XOR at S4, and the result obtained is respectively stored in trigger DFF-3 and DFF-4.
Step 3: the signal in 4 triggers DFF-1, DFF-2, DFF-3, DFF-4 is squeezed into simultaneously in 4-16 line decoder MSI, the relation of TSV_1, TSV_2, TSV_3, TSV_4 is obtained, i.e. the whether synchronous fault of these four TSV or synchronous not fault according to the result of decoding.
Step 4: according to the result of TSV classification in the failure condition of TSV_3 in step 1 and step 3, reasoning has all the other 3 TSV whether fault.
Claims (2)
1., for a device for TSV Autonomous test and classification check, it is characterized in that:
Arrange a column construction, the support of described column construction is each TSV, by chip layer and lower chip layer in described each TSV connection; In upper chip layer, the top of each TSV is connected to form a closed-loop between two, and using a fixing point as upper public some O altogether, described upper public some O is altogether connected with the top of all each TSV, respectively as the terminal that each TSV is common, using described upper chip layer as receiving terminal; Altogether public some O connects a time-delay mechanism be composed in series by even number of inverters on described, as the top of the common bounce-back of all TSV;
In lower chip layer, the lower end of each TSV forms a corresponding virtual ring, described virtual ring connects an XOR gate between the lower extreme point of every two TSV, the output of each XOR gate is connected to the trigger end of respective trigger correspondingly, and the output of each trigger is connected on a decoder; Described lower chip layer has a fixing point as lower public some F altogether, described lower public some F is altogether connected with the lower end of all each TSV, respectively as the common source point of each TSV, using described lower chip layer as transmitting terminal;
The time-delay mechanism that the top of a TSV wherein connects buffer and is made up of inverter, connect a data comparison means in lower end, described data comparison means is made up of triple gate E, trigger and XOR gate.
2. described in a claim 1 for the method for testing of the device of TSV Autonomous test and classification check, it is characterized in that: from source point, signal is squeezed into TSV, transmit through TSV, to rebound all TSV through common terminal again, respectively the signal that two adjacent TSV transmission are returned is compared by XOR gate in lower chip layer, the result compared separately is transferred in the trigger connected separately, according to unified clock signal, signal in trigger is squeezed into decoder simultaneously, obtain the result of decoding, whether similarly judged between the TSV that mutually compares by the result comparing decoding, described similar referring to is all failure classes or is all non-faulting class, judge TSV by carrying out Autonomous test to wherein TSV whether fault is as first step judged result, recycle described first judged result and judge all the other all TSV whether fault.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6991945B1 (en) * | 2002-08-30 | 2006-01-31 | Advanced Micro Devices, Inc. | Fault detection spanning multiple processes |
| CN102856226A (en) * | 2012-09-08 | 2013-01-02 | 合肥工业大学 | Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
-
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- 2015-07-08 CN CN201510400049.0A patent/CN105047577B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6991945B1 (en) * | 2002-08-30 | 2006-01-31 | Advanced Micro Devices, Inc. | Fault detection spanning multiple processes |
| CN102856226A (en) * | 2012-09-08 | 2013-01-02 | 合肥工业大学 | Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
Non-Patent Citations (2)
| Title |
|---|
| 欧阳一鸣 等: "面向非全互连3D NoC可靠通信的分布式路由算法", 《计算机辅助设计与图形学学报》 * |
| 王伟 等: "一种多链式结构的3D-SIC过硅通孔(TSV)容错方案", 《计算机工程与应用》 * |
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