CN102856226B - Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module - Google Patents
Testing device of 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with signal rebounding module Download PDFInfo
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Abstract
The invention discloses a testing device of a 3D-SIC (Three-Dimensional-Semiconductor Integrated Circuit) through silicon vias provided with a signal rebounding module. A sending end is connected with a receiving end by through a plurality of silicon vias TSVs. The sending end comprises a first tested chip, a decoder, a control unit CU, a latch D and a bidirectional switch DSW. The receiving end comprises a second tested chip and a signal rebounding module. The signal rebounding module comprises a signal generator F, a plurality of delay cells and a plurality of three-state gates. The upper ends of the TSVs are connected with the delay cells M and the signal generator F at the receiving end. The lower ends of the TSVs are connected with the decoder and the DSW at the sending end. The decoder, the latch D and the DSW are connected with the CU. The latch D is further connected with the DSW. The testing device of the 3D-SIC through silicon vias provided with the signal rebounding module can effectively solve the problem that failed TSVs in the 3D chip preparing process are hard to detect effectively, and has the advantages of smaller area and practical expenses and lower power consumption and the like.
Description
Technical field
The present invention relates to the testing apparatus that a kind of 3D-SIC being provided with signal bounce-back module crosses silicon through hole.
Background technology
Along with chip manufacturing process ground development, the size of chip constantly reduces, and performance improves constantly, and has continued the splendidness of Moore's Law nearly half a century.But semiconductor transistor size is close to nanoscale, and imply that manufacture of microchips will run into a great bottleneck, Moore's Law likely lost efficacy at this point.In order to continue Moore's Law, continue the performance promoting chip, 3D chip arises at the historic moment.In integrated circuit in the past, all elements are all in one plane distribute, and are namely called 2D integrated circuit.And the design of 3D integrated circuit is different from the graphic design method of 2D integrated circuit, it is by multiple wafer (Die) vertical stacking, by silicon through hole (TSV) interconnection, to realize Vertical collection.Thus obtain less volume, better power consumption and radio-frequency performance.
The vertical stacking mode of chip can be divided into stacking (Face-to-Face Bonding) face-to-face, in the face of the back of the body stacking (Face-to-Back Bonding) and back-to-back stacking (Back-to-Back Bonding) three kinds.Wherein stacking is face-to-face the stacking formation of metal layer vertical of two integrated circuits, does not need to be interconnected by TSV.And in the face of back of the body heap superimposition back-to-back stack manner is not two integrated circuits, metal level is directly contacted, so must be interconnected by TSV.In chip-stacked technology, two-layer above integrated circuit stacking just inevitably will be used in the face of the back-to-back stack manner of back of the body heap superimposition.The importance of TSV in 3D integrated circuit as can be seen here.
TSV technology (Through-Silicon Vias, cross silicon through hole) be by between nude film (Die) and nude film, between wafer (Wafer) and wafer, make vertical conducting between wafer and nude film, realize the state-of-the-art technology interconnected between chip.TSV just represents the data link in a vertical direction, is used for signal transmission.Encapsulate from IC in the past and use the superimposing technique of salient point different, TSV can make that chip is maximum in the density that three-dimensional is stacking, overall dimension is minimum, and greatly improves the performance of chip speed and low-power consumption.But due to the restriction of technology, may there is fracture in TSV in the fabrication process, injects uneven and have impurity situation, causing occurring short circuit and breaking phenomena.Can not ensure that all TSV made are intact.The failure problems of TSV has a lot, in the injection conductive copper stage, also exists to inject and insufficiently causes TSV to rupture or the very very thin problem of TSV, cause being easy to break down during Signal transmissions.The last process also having a skiving in the making of TSV, the diameter of TSV is generally 4 ~ 8um, and the process thinned easily causes the fracture of TSV.In the stacking process of wafer, require that TSV aims at due to two-layer up and down, but the TSV of tens thousand of to align very difficult, but also be when the diameter of TSV is so little.Because TSV is the highdensity interconnection line of a class, while TSV self produces also can by thermal coupling to it near TSV in, thus heat the interconnection line near it.It is reported, often increase by 10 degree, delay will increase by 5%, hydraulic performance decline 30%.Therefore heat dissipation problem is also a TSV problem urgently to be resolved hurrily.Inefficacy due to single TSV likely can cause two known wafers that can normally work or chip at heap poststack cisco unity malfunction, and such cost can rise rapidly.
Three-dimensional stacked integrated circuit (3D-SIC) mainly adopted silicon through hole technology to realize module interconnection in vertical direction, but silicon through hole all likely occurs losing efficacy in manufacture process or binding after-stage, causes whole chip normally to work.In order to improve the rate of finished products of 3D chip, reduce manufacturing cost, need different phase in the fabrication process to test it, mainly comprise the test of following three phases: test (post bond test) and final test (final test) after test (pre bond test) before binding, binding.
1, test (pre bond test), namely flawless kernel test (Known Good Die, KGD) before binding.Need through series of process step owing to crossing the making of silicon through hole, wherein each step likely goes wrong, such as in the injection conductive copper stage, also exist to inject and insufficiently cause the problems such as TSV ruptures or TSV is too very thin, need to test chip before binding, to remove problematic chip, thus reduce costs, boost productivity.
2, test (post bond test) after binding, namely flawless stacking test (Known Good Stack, KGS).In multilayer chiop binding procedure, may, because binding pressure is excessive, insulation or the phenomenon such as TSV misalignment appear in binding interface, cause TSV to occur short circuit or open circuit conditions, make signal cannot normal transmission, so will test chip after binding.
3, final test (final test), tests finally packaged chip exactly, finally determines which chip is qualified.
Wherein, the probability that TSV breaks down after binding is higher, and TSV is as a kind of mode of important 3D IC module communication, and therefore after binding, test seems particularly important.Normally working to not affect chip, adding test structure in the chips, Land use models switching mode realizes controlling.
Test for after the binding of TSV, in research approach both domestic and external, mainly contain following several method:
1, by using BIST(Built-in Self Test, built-in self-test) method, identical test structure is added in layers of chips after binding, utilize control signal by test vector maker (TPG, Test-Pattern Generator) test vector that generates carry out transmitting before and after comparison, and then reach the object of test, realize higher fault coverage.But this method, area overhead is larger with displacement power consumption;
2, after binding, TSV two ends add identical test structure, utilize voltage division technology to realize test; But this method is based upon in certain theoretical foundation, and precision is not high enough, and control signal is complicated, implements difficulty;
3, pass through the method increasing scan chain and scanning island on every one deck chip, utilize these scan chains and scanning island to transmit control signal and carry out transmitting the comparison of front and back, effectively can reach the object of test TSV.But this method area overhead is large;
4, by carrying out RC modeling to two kinds of TSV, test before using voltage division and charge sharing techniques to realize TSV binding, but owing to there is noise in side circuit, result through theoretical value calculating and reflect actual conditions, accuracy can not be guaranteed; Fault coverage is lower.
Summary of the invention
The present invention is for avoiding the weak point that exists in above-mentioned prior art, provides the testing apparatus that a kind of 3D-SIC being provided with signal bounce-back module crosses silicon through hole, to solve the problem of inefficacy TSV being carried out to effective detection difficult in 3D chip manufacturing proces.
The present invention is technical solution problem, provides the testing apparatus that a kind of 3D-SIC being provided with signal bounce-back module crosses silicon through hole.
The 3D-SIC being provided with signal bounce-back module crosses the testing apparatus of silicon through hole, and its design feature is, comprises transmitting terminal and receiving terminal; Cross silicon through hole TSV by many between described transmitting terminal and receiving terminal to be connected; Described transmitting terminal comprises the first chip under test, decoder, control unit CU, latch D and bidirectional switch DSW; Described receiving terminal comprises the second chip under test and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, multiple delay cell M and multiple triple gate;
The described upper end crossing silicon through hole TSV is connected with signal generator F with the delay cell M of described receiving terminal, and described delay cell M is all connected with described signal generator F by respective triple gate;
The described lower end crossing silicon through hole TSV is connected with bidirectional switch DSW with the decoder of described transmitting terminal; Described decoder, latch D and bidirectional switch DSW are all connected with described control unit CU; Described latch D is also connected with described bidirectional switch DSW.
The testing apparatus that the 3D-SIC being provided with signal bounce-back module of the present invention crosses silicon through hole also has following technical characterstic.
Described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
Compared with the prior art, beneficial effect of the present invention is embodied in:
The present invention proposes a kind of testing apparatus, test for binding after-stage silicon through hole, utilize the irreversibility that signal transmits in the conductor, bounce-back module is increased at signal receiving end, by applying twice different test and excitation at transmitting terminal, utilize trigger and MUX that twice Output rusults is carried out XOR, reach test purpose.The present invention, by applying twice different test vector to single TSV, is 0 and 1 respectively.Compared the result of two secondary responses by XOR gate logic, if exporting is 0, indicate fault; If export time 1, represent fault-free.
3D-SIC of the present invention crosses the testing apparatus of silicon through hole, utilize the irreversibility that signal transmits in the conductor, bounce-back module is increased at signal receiving end, by applying twice different test and excitation at transmitting terminal, utilize trigger and MUX that twice Output rusults is carried out XOR, reach test purpose, efficiently solve a difficult problem of inefficacy TSV being carried out to effectively detection in 3D chip manufacturing proces.Testing apparatus of the present invention is accomplishing, under the prerequisite carrying out inefficacy TSV effectively detecting, to have area and put into practice expense less, the advantages such as power consumption is lower.
Accompanying drawing explanation
Fig. 1 is the overall structure stereogram of testing apparatus of the present invention.
Fig. 2 is the TSV block sending end structure of testing apparatus of the present invention.
Fig. 3 is the enlarged drawing of bus lower end module in Fig. 2.
Fig. 4 is the TSV block receiving terminal structure of testing apparatus of the present invention.
Label in accompanying drawing 1 ~ accompanying drawing 4: 1 transmitting terminal, 101 first chip under test, 102 decoders, 2 receiving terminals, 201 second chip under test, 202 triple gates.
Below by way of embodiment, the invention will be further described.
Embodiment
Participate in Fig. 1 ~ Fig. 4, the 3D-SIC being provided with signal bounce-back module crosses the testing apparatus of silicon through hole, comprises transmitting terminal 1 and receiving terminal 2; Cross silicon through hole TSV by many between described transmitting terminal and receiving terminal to be connected; Described transmitting terminal comprises the first chip under test 101, decoder 102, control unit CU, latch D and bidirectional switch DSW; Described receiving terminal 2 comprises the second chip under test 201 and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, multiple delay cell M and multiple triple gate 202;
The described upper end crossing silicon through hole TSV is connected with signal generator F with the delay cell M of described receiving terminal, and described delay cell M is all connected with described signal generator F by respective triple gate 202;
The described lower end crossing silicon through hole TSV is connected with bidirectional switch DSW with the decoder 102 of described transmitting terminal; Described decoder 102, latch D and bidirectional switch DSW are all connected with described control unit CU; Described latch D is also connected with described bidirectional switch DSW.
Described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
Principle foundation of the present invention: TSV may have three kinds of situations after binding: stuck at 0 fault, stuck at 1 fault and fault-free.In order to improve fault coverage, the present invention, by applying twice different test vector to single TSV, is 0 and 1 respectively.The result of two secondary responses is compared by XOR gate logic.
The overall architecture of structure of the present invention: in order to describe the problem better, carries out logic function piecemeal by TSV, such as, be divided into 4x4 mode, double-layer structure.Fig. 1 is the overall architecture of test structure.Wherein in bottom, CU represents unit of testing and controlling, mainly provides test and excitation, test control signal and test response analysis.D represents XOR, multi-path choice and latch logical network, and main preservation response and response ratio are comparatively.DECODER represents decoder, mainly screens wherein a line and tests.DSW is bidirectional switch.In upper strata, M is delay cell.F is enable control signal generator.Die1 is the first chip under test, and Die2 is the second chip under test.In Fig. 4, Delay cell is delay cell M.
As shown in Figure 2, wherein FG is square wave maker to TSV block sending end structure, generates 0 and 1 twice test and excitation.SWCM is bidirectional switch control module.AG is the address signal generating decoder.TC is testing and control and testing analysis module.The each TSV end points being wherein in transmitting terminal has a bidirectional switch logic.Each column address conductor with provide the bus infall of test and excitation to have a bidirectional switch DSW.As shown in Figure 3 be the enlarged drawing of a module below Fig. 2 bus, often row below bus have XOR, multi-path choice and a latching logic, final test signal is all connected on respective NMOS grid, the drain electrode of rightmost NMOS connects VDD, and the source electrode of leftmost NMOS is connected on test controller.In Fig. 2 and Fig. 3, C is level pulse signal, and C ' is its complementary signal, and Q is the output signal of transparent D lock.
As shown in Figure 4, F is the generator generating enable control signal according to TSV signal to TSV block receiving terminal structure.The public delay unit M of each row TSV.Generate different enable signals by F and control complementary triple gate, realize signal bounce-back.
Specific implementation process of the present invention is: first send test massage 0 by transmitting terminal, and after receiving terminal receives signal, by signal rebounding device, signal is back to transmitting terminal, transmitting terminal is preserved in a register after receiving the signal returned.Then transmitting terminal is to sending test massage 1, with comprehending the signal receiving receiving terminal bounce-back and return.This signal and the signal be kept in register are before carried out XOR, if result is 1, then represents that time TSV is normal; If be 0, then represent that this TSV lost efficacy.
As shown in Figure 2, transmitting terminal produces test and excitation signal.The address generator AG of the controller inside of the control unit CU in TSV block sending end structure generates the decode address selection information of decoder, and act on Y3 address wire, wherein Y2, Y1 and Y0 are invalid.
First time is when testing, first square wave maker FG generates 0 test vector and acts in the bus of connection, bidirectional switch control module SWCM sends a high level signal, the bidirectional switch be in bus is made to be in conducting state, now X0, X1, X2 and X3 select on line is all 0 signal, but only has Y3 to select the TSV on line just can obtain this signal.The bidirectional switch be on Y3 holding wire is in conducting state, and test signal is transferred to receiving terminal module along TSV.
Receiving terminal bounce-back test and excitation signal.In receiving terminal module, X selects the TSV end points on line to be connected on enable signal controller F.When the capable TSV of transmitting terminal has test signal, act on enable signal controller, now produce a high level signal, complementary triple gate is in conducting state.Test signal is transmitted along delay unit, in order to avoid the situation in loop appears in signal in delay unit, chooses pulse duration and the delay unit time consistency of enable signal controller F, when returning from delay unit signal one curb TSV out; Triple gate is arrived again in another road, but produces a high level signal due to this Time Controller, and triple gate ends.Would not be there is the situation of circling round in such signal, avoid the interference of signal and reduce power consumption.
Then, the corresponding test signal of transmitting terminal process.When signal returns, generate a low level signal by the square wave maker FG of the controller inside of control unit CU, act on the bidirectional switch in bus, make it be in cut-off state.Such Y3 selects each TSV inverse signal on line would not occur situation about disturbing.Test response is saved in transparent D-latch by multi-path choice logic for the first time.
When second time is tested, square wave maker FG generates 1 test vector and acts in bus, and process is thereafter identical with first time test process.When second time test response signal arrives XOR and multi-path choice logic time, control unit CU provides a high level C pulse signal, and now primary test response result is just transferred to an input of XOR.By comparing the test response result of front and back twice, there is individual comparison signal at the output of XOR.These Output rusults are all connected to the grid of respective NMOS.When grid is high level time, conducting; Otherwise, cut-off.Utilize twice response results analytical table of three kinds of situations above known, if out of order words, the source electrode of Far Left NMOS is individual 0; If trouble-free words, be individual 1.Whether analyze Y3 by test controller TC has fault to exist.After Y3 test terminates, and then carry out the test of Y2, Y1 and Y0 respectively.
During concrete enforcement, determine that TSV is divided into several row of a few row at the design initial stage, according to the number of TSV in the position of each TSV block and corresponding TSV block, multiple TSV is divided into a TSV chain.
At the transmitting terminal of TSV, connect all TSV chains with a decoder, and square wave maker is set, generate 0 and 1 twice test and excitation.The each TSV end points being wherein in transmitting terminal has a bidirectional switch logic, each column address conductor with provide the bus infall of test and excitation to have a bidirectional switch, often row below bus have XOR, multi-path choice and a latching logic, final test signal is all connected on respective NMOS grid, the drain electrode of rightmost NMOS connects VDD, and the source electrode of leftmost NMOS is connected on test controller.
At the receiving terminal of TSV block, have one to generate the generator F of enable control signal according to TSV signal, the public delay unit M of each row TSV, generates different enable signals by signal generator and controls complementary triple gate, realizes signal bounce-back.
The detailed step of test is as follows:
1) address generator in TSV block sending end structure generates decoding address selecting information, and act on a TSV chain, other TSV chains are invalid.First square wave maker generates 0 test vector and acts in the bus of connection, bidirectional switch control module sends a high level signal, the bidirectional switch be in bus is made to be in conducting state, TSV on the TSV chain now chosen by decoder obtains this signal, and test signal is transferred to receiving terminal module along TSV.
2) in receiving terminal module, when the capable TSV of transmitting terminal has test signal, act on enable signal controller, now produce a high level signal, complementary triple gate is in conducting state.Test signal is transmitted along delay unit, and signal bounce-back is postbacked sending end.
3) in initiator block, be saved in D-latch by first time test response by multi-path choice logic, then square wave maker FG generates 1 test vector and acts in bus, and following processes is identical with first time.When second time test response signal arrives XOR and multi-path choice logic time, compare the test response result of front and back twice, have individual comparison signal at the output of XOR.These Output rusults are all connected to the grid of respective NMOS.When grid is high level time, conducting, otherwise, cut-off.Utilize twice response results analytical table of three kinds of situations above known, if out of order words, the source electrode of Far Left NMOS is individual 0; If trouble-free words, be individual 1; Again other TSV chain is implemented to the testing procedure of above-mentioned 1 to 4.
At sending module, generating a low level signal, act on the bidirectional switch in bus, make it be in cut-off state by square wave maker FG, would not there is situation about disturbing in each TSV inverse signal on such TSV chain.
Claims (2)
1. the 3D-SIC being provided with signal bounce-back module crosses the testing apparatus of silicon through hole, it is characterized in that, comprises transmitting terminal (1) and receiving terminal (2); Cross silicon through hole by many between described transmitting terminal and receiving terminal to be connected; Described transmitting terminal comprises the first chip under test (101), decoder (102), control unit CU, latch D and bidirectional switch DSW; Described receiving terminal comprises the second chip under test (201) and signal bounce-back module; Described signal bounce-back module comprises a signal generator F, multiple delay cell M and multiple triple gate (202);
The described upper end crossing silicon through hole is connected with signal generator F with the delay cell M of described receiving terminal, and described delay cell M is all connected with described signal generator F by respective triple gate (202);
The described lower end crossing silicon through hole is connected with bidirectional switch DSW with the decoder (102) of described transmitting terminal; Described decoder (102), latch D and bidirectional switch DSW are all connected with described control unit CU; Described latch D is also connected with described bidirectional switch DSW.
2. the 3D-SIC being provided with signal bounce-back module according to claim 1 crosses the testing apparatus of silicon through hole, and it is characterized in that, described latch D is connected with power vd D by metal-oxide-semiconductor field effect transistor.
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| CN103323731B (en) * | 2013-06-19 | 2015-12-02 | 西安理工大学 | A kind of digital 3D integrated circuit silicon defective hole automatic testing method |
| CN103780243B (en) * | 2014-01-28 | 2016-07-06 | 合肥工业大学 | A kind of 3D chip redundancy silicon through hole fault-tolerant architecture with transfer signal function |
| CN105206600B (en) * | 2014-06-30 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor test structure |
| CN105632942A (en) * | 2014-10-31 | 2016-06-01 | 北京自动化控制设备研究所 | Three-dimensional packaging method of navigation computer chip |
| CN104795342A (en) * | 2015-04-30 | 2015-07-22 | 合肥工业大学 | Testing device with Through Silicon Vias (TSV) self-test function and testing method |
| CN105047577B (en) * | 2015-07-08 | 2017-11-28 | 合肥工业大学 | It is a kind of to be used for TSV Autonomous tests and the device of classification check |
| CN106556790B (en) * | 2015-09-24 | 2020-05-12 | 中芯国际集成电路制造(上海)有限公司 | Through silicon via sensor, detection method and electronic device |
| CN106199382A (en) * | 2016-07-06 | 2016-12-07 | 合肥工业大学 | Silicon through hole test structure before a kind of binding based on vernier ring |
| CN112765928A (en) * | 2019-11-06 | 2021-05-07 | 瑞昱半导体股份有限公司 | Test pattern generation method and failure model generation method |
| CN113053772A (en) * | 2021-03-18 | 2021-06-29 | 西安电子科技大学 | Test structure for packaged through-silicon-via laminated chip |
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