CN110120242A - Method for testing memory, device, computer equipment and storage medium - Google Patents
Method for testing memory, device, computer equipment and storage medium Download PDFInfo
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- CN110120242A CN110120242A CN201910366150.7A CN201910366150A CN110120242A CN 110120242 A CN110120242 A CN 110120242A CN 201910366150 A CN201910366150 A CN 201910366150A CN 110120242 A CN110120242 A CN 110120242A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
This application involves a kind of method for testing memory, device, computer equipment and storage mediums.Method includes: to obtain test signal first；The first built-in self-test test first is carried out to the region for not having data, obtains the test result of the first built-in self-test test；When the test of the first built-in self-test passes through, migration has data in the region of data and testing control module is written in the second test signal, tests the region for having data, the test result of memory is obtained according to the result of test to the region for not having data.The method for testing memory of the application is controlled by testing control module to embed built-in self-test test to chip, the region for having data and the region for not having data are tested respectively simultaneously, it is optimized so that the built-in self-test of internal storage is tested, so as to shorten the testing time of built-in self-test test.
Description
Technical field
This application involves chip testing technology fields, set more particularly to a kind of method for testing memory, device, computer
Standby and storage medium.
Background technique
With the fast development of IC industry, the logic scale of chip be increased dramatically, chip RAM (Random
Access Memory, random access memory) demand increase.Random access memory is mainly used for loading miscellaneous journey
Sequence and data are so that chip is directly run and is used.Shared specific gravity is increasing in a chip design by chip RAM, therefore RAM
Yield and the degree of reliability are increasingly important.However, few chip RAM can directly pass through core since RAM is in the inside of chip
Piece pin is connected directly, and increases the difficulty of test to chip interior RAM；And with the raising of IC industry technology
And the reduction of characteristic size, the RAM on chip also become increasingly density, the failure type occurred is also more and more.This
Sample just considerably increases testing cost and security risk, so that original test method is difficult to cope with these new challenges.
In recent years, MBIST (Memory Build-In Self Test, memory built in self test of sram), is to be widely used for surveying
A kind of circuit of memory is tried, MBIST is small with its area occupied, test development expense is low and reads and writes RAM using failure algorithm
It determines the whether defective feature of RAM, is widely adopted in IC design.However traditional MBIST to RAM carry out
The testing time of test is longer, and testing efficiency is low.
Summary of the invention
Based on this, it is necessary to, testing efficiency longer for the testing time of traditional MBIST tested memory
Low problem provides a kind of method for testing memory that can be efficiently tested to memory, device, computer equipment and deposits
Storage media.
A kind of method for testing memory, which is characterized in that be applied to memory testing system, the memory testing system
Including testing control module interconnected and memory built self-testing circuit, the memory built self-testing circuit with it is to be measured
Memory connection；
The method for testing memory includes:
Obtain first test signal and second test signal, it is described first test signal be used for in memory to be measured not
The region of storing data carries out memory built from testing, and the second test signal is used for storing number in memory to be measured
According to region carry out memory built from test；
By testing control module input the first test signal to memory built self-testing circuit, do not have to described
The region of data carries out the first built-in self-test test, obtains the test result of the first built-in self-test test；
When first built-in self-test test passes through, there are data in the region of data described in migration and do not have to described
The region of data；
By testing control module input the second test signal to memory built self-testing circuit, there is number to described
According to region carry out the second built-in self-test test, the survey of the memory is obtained according to the result that second built-in self-test is tested
Test result.
It is described by testing control module input the first test signal to memory in one of the embodiments,
Self-testing circuit is built, the first built-in self-test test is carried out to the region for not having data, first built-in self-test is obtained and surveys
After the test result of examination, further includes:
When first built-in self-test test does not pass through, determine that the memory to be measured is unqualified.
Memory built self-testing circuit includes test vector generation circuit, built-in self-test control in one of the embodiments,
Circuit processed, response analyzer, it is described by the first test signal of testing control module input to memory built from surveying electricity
Road, carrying out the test of the first built-in self-test to the region for not having data includes:
The first test signal is inputted to test vector generation circuit, controls the test vector generation circuit generation pair
Answer test vector；
The test vector is sent to the built-in self-test control circuit, institute is inputted by the built-in self-test control circuit
Test vector is stated to the region for not having data；
It obtains the region for not having data by the response analyzer to respond the test of the test vector, root
The test result of the first built-in self-test test is obtained according to the test response.
There is not the region of data to the survey by the way that response analyzer acquisition is described in one of the embodiments,
The test response for trying vector, accordingly obtaining the test result that first built-in self-test is tested according to the test includes:
The region for not having data is obtained by the response analyzer to respond the test of the test vector；
It compares the normal memory prestored to respond the normal response of the test vector and the test, when described normal
When responding identical as the test response, determine that the first built-in self-test test passes through, when the normal response and the survey
When examination response is not identical, discriminating test does not pass through.
In one of the embodiments, it is described compare the normal memory that prestores to the normal response of the test vector with
The test response determines that the region for not having data is qualified when the normal response is identical as the test response,
When the normal response and not identical test response, after determining that the region for not having data is unqualified, also wrap
It includes:
According to the difference of the normal response and the test response, the address information in memory exception region is obtained, and
Generate memory test report corresponding with the address information in the memory exception region.
It is described when first built-in self-test test passes through in one of the embodiments, there are data described in migration
Region in data to the region for not having data include:
When first built-in self-test test passes through, data in the region for having data are read according to processor pointer,
Will the data write-in region for not having data, while the processor pointer being jumped to and described does not have data
The storage address in region.
A kind of memorizer test device, the memorizer test device are applied to memory testing system, the memory
Test macro includes that memorizer test device, testing control module and memory built self-testing circuit, described device include:
Signal acquisition module, for obtaining the first test signal and the second test signal, the first test signal is used
In to memory to be measured not stored data region carry out memory built from test, it is described second test signal for pair
The region of storing data carries out memory built from test in memory to be measured；
First testing control module, for passing through the first test signal of testing control module input to memory built
Self-testing circuit carries out the first built-in self-test test to the region for not having data, obtains the first built-in self-test test
Test result；
Data Migration module, for having the region of data described in migration when first built-in self-test test passes through
Interior data are to the region for not having data；
Second testing control module, for passing through the second test signal of testing control module input to memory built
Self-testing circuit carries out the second built-in self-test test to the region for having data, according to second built-in self-test test
As a result the test result of the memory is obtained.
It in one of the embodiments, further include fault interrupting determination module, the fault interrupting determination module, for working as
When the first built-in self-test test does not pass through, determine that the memory to be measured is unqualified.
A kind of computer equipment, including memory and processor, the memory are stored with computer program, the processing
Device performs the steps of when executing the computer program
Obtain first test signal and second test signal, it is described first test signal be used for in memory to be measured not
The region of storing data carries out memory built from testing, and the second test signal is used for storing number in memory to be measured
According to region carry out memory built from test；
By testing control module input the first test signal to memory built self-testing circuit, do not have to described
The region of data carries out the first built-in self-test test, obtains the test result of the first built-in self-test test；
When first built-in self-test test passes through, there are data in the region of data described in migration and do not have to described
The region of data；
By testing control module input the second test signal to memory built self-testing circuit, there is number to described
According to region carry out the second built-in self-test test, the survey of the memory is obtained according to the result that second built-in self-test is tested
Test result.
A kind of computer readable storage medium, is stored thereon with computer program, and the computer program is held by processor
It is performed the steps of when row
Obtain first test signal and second test signal, it is described first test signal be used for in memory to be measured not
The region of storing data carries out memory built from testing, and the second test signal is used for storing number in memory to be measured
According to region carry out memory built from test；
By testing control module input the first test signal to memory built self-testing circuit, do not have to described
The region of data carries out the first built-in self-test test, obtains the test result of the first built-in self-test test；
When first built-in self-test test passes through, there are data in the region of data described in migration and do not have to described
The region of data；
By testing control module input the second test signal to memory built self-testing circuit, there is number to described
According to region carry out the second built-in self-test test, the survey of the memory is obtained according to the result that second built-in self-test is tested
Test result.
Above-mentioned method for testing memory, device, computer equipment and storage medium, the method for testing memory of the application
It is controlled by testing control module to embed built-in self-test test to chip, while not deposited to the region for having data and
There is the region of data to be tested respectively, is optimized so that the built-in self-test of internal storage is tested, so as to shorten built-in self-test
The testing time of test.
Detailed description of the invention
Fig. 1 is the applied environment figure of method for testing memory in one embodiment；
Fig. 2 is the flow diagram of method for testing memory in one embodiment；
Fig. 3 is the flow diagram of method for testing memory in another embodiment；
Fig. 4 is the sub-process schematic diagram of the step S400 of Fig. 2 in one embodiment；
Fig. 5 is the sub-process schematic diagram of the step S400 of Fig. 2 in another embodiment；
Fig. 6 is the structural block diagram of memorizer test device in one embodiment；
Fig. 7 is the internal structure chart of computer equipment in one embodiment.
Specific embodiment
It is with reference to the accompanying drawings and embodiments, right in order to which the objects, technical solutions and advantages of the application are more clearly understood
The application is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the application, not
For limiting the application.
Method for testing memory provided by the present application can be applied to the memory test system of chip 100 as shown in Figure 1
It in system, is realized by processor 120, test for the RAM to chip, wherein memory testing system includes processor
120, testing control module 140 and memory built self-testing circuit 160,.Processor 120 obtain for memory to be measured into
First test signal of line storage built-in self-test test and the second test signal；And preprocessor 120 believes the first test
Number write-in testing control module 140, testing control module 140 for input control signal to memory built self-testing circuit 160,
It controls memory built self-testing circuit and memory test is carried out to memory 180；First processing device 120 passes through testing control module
It is built-in to carry out first to the region 181 for not having data to memory built self-testing circuit 160 for 140 the first test signals of input
From testing, the test result of the first built-in self-test test is obtained；When the test of the first built-in self-test passes through, processor 120 is moved
183 internal program of region for having data is moved to the region 181 for not having data, testing control module is written into the second test signal
140, by the input of testing control module 140 second test signal to memory built self-testing circuit 160, to the area for having data
Domain 183 carries out the second built-in self-test test, and the test result of memory 180 is obtained according to the result of the second built-in self-test test.
As shown in Fig. 2, the method for testing memory of the application in one of the embodiments, is realized by processor, have
Body the following steps are included:
S200, obtains the first test signal and the second test signal, and the first test signal is used for in memory to be measured
The region of not stored data carries out memory built from testing, and the second test signal is used for storing data in memory to be measured
Region carry out memory built from test.
Wherein, memory to be measured refers to comprising random access memory in the chip, and memory built is from test is surveyed
Refer to Memory Build-In Self Test measuring technology, abbreviation MBIST is one of BIST technology.BIST is to set
Timing is implanted into related functional circuits for providing the technology of selftest function in circuit, reduces device detection to automatic with this
The degree of dependence of test equipment (ATE).BIST is a kind of DFT (Design for Testability) technology, it can be applied
It is widely used in nearly all circuit, therefore in semi-conductor industry.First test signal is respectively used to the second test signal
The region for having data and the region for not having data are tested.First test signal and the second test signal specifically may be used
Think IJTAG (Internal, Joint Test Action Group, network association test job group) signal.First test letter
It number is generated based on different testing algorithm, is used for input test vector generation circuit, generates what a variety of pairs of memories were tested
Test vector.Processor is connected with the pin of chip, and processor can obtain the first test of extraneous input by chip pin
Signal and the second test signal.It is used for memory test processor first in chip, can be obtained by the pin of chip
First test signal of external world's input and the second test signal.
S400, by testing control module input the first test signal to memory built self-testing circuit, to there not being number
According to region carry out the first built-in self-test test, obtain the first built-in self-test test test result.
Testing control module refers to that the memory built self-testing circuit for controlling chip interior carries out the mould of built-in self-test
Block, testing control module can pass through the TAP (Test Access Port, test access port) of memory built self-testing circuit
It is connect with memory built self-testing circuit, memory built self-testing circuit is tested.The major function of testing control module
It is that the data communicated on original interface are restored by way of the read-write of controller.Memory built self-testing circuit refers in chip
Inside carries out the circuit of built-in self-test test for the memory to chip.
Processor can be written to testing control module for not after receiving the test signal from chip exterior
There is the first test signal that the region of data is tested.Later, the first test signal is being input to testing control module
Later, the first test signal can be restored by testing control module, and is input to memory built self-testing circuit, deposited
Reservoir build-in self-test tests signal to depositing after obtaining the first test signal of testing control module input, according to first
The region for not having data in reservoir carries out built-in self-test test, and obtains the test result of response.
S600, when the test of the first built-in self-test passes through, migration has in the regions of data data to there not being data
Region.
It may include the data of such as program etc in the memory of specific chip, when for the area for not having data
When the first built-in self-test test that domain is tested passes through, that is, determine that the region for not having data is the non-defective unit that can normally read and write
When, it can be read by processor and have data in the regions of data, and be written into memory to be measured does not have data
There are in the regions of data data the part in region, i.e. migration to the region for not having data.
S800, by testing control module input the second test signal to memory built self-testing circuit, to there being data
Region carry out the second built-in self-test test, according to the second built-in self-test test result obtain memory test result.
Then to after migrator have data region carry out the second built-in self-test test, according to second it is built-in from
The test result of test obtains the built-in self-test test result of entire chip memory.Due to the process tested in built-in self-test
The code of middle memory inside cannot be capped, so needing to have by processor migration in the region of data data to prevent
These data are capped in test process.When the first built-in testing by the second built-in self-test test simultaneously also by when, can be with
Determine that current memory to be measured has passed through test, when the first built-in testing passes through but the test of the second built-in self-test does not pass through, then
Determine that there are problems not to pass through test for current memory to be measured.
Above-mentioned method for testing memory, device, computer equipment and storage medium, the method for testing memory of the application
It is controlled by testing control module to embed built-in self-test test to chip, while not deposited to the region for having data and
There is the region of data to be tested respectively, is optimized so that the built-in self-test of internal storage is tested, so as to shorten built-in self-test
The testing time of test.
As shown in figure 3, in one of the embodiments, after S400 further include:
S500 determines that memory to be measured is unqualified when the test of the first built-in self-test does not pass through.
When the first built-in self-test test carried out to the region for not having data does not pass through, current storage to be measured is judged
Device cannot be written and read, and determine that memory to be measured is unqualified, and terminate the test process of memory, when the first built-in self-test does not lead to
It is out-of-date, it can be determined that current storage has certain problems, and can directly terminate to test, and determines current memory to be measured
It is unqualified, by the way that memory to be measured, whether qualification determines during the first built-in self-test is tested, avoid to first
The memory to be measured of test crash carries out the second test, can effectively shorten the whole flow process of test, improves testing efficiency.
As shown in figure 4, in one of the embodiments, memory built self-testing circuit include test vector generation circuit,
Built-in self-test control circuit, response analyzer, S400 include:
S410, the first test signal of input to test vector generation circuit, controls test vector generation circuit and generates correspondence
Test vector；
S430 sends test vector to built-in self-test control circuit, passes through built-in self-test control circuit input test vector
To the region for not having data；
S450 is obtained the region for not having data by response analyzer and responded to the test of test vector, according to test
Response obtains the test result of the first built-in self-test test.
Wherein test vector refers to the data for carrying out specific mode test to memory, it is based on testing control module
First test signal input of simulation generates.Test vector generation circuit can be generated based on the first test signal for memory
It carries out testing a variety of test vectors, tests multiple memorizers failure type, obtain more accurate test effect.Built-in self-test control
Circuit can usually be realized by state machine, control the read-write operation to memory, and response analyzer can both be realized with comparator,
It can also be realized with MISR (Multi-Input Signature Register compressor multi input shift register) circuit, it
Known normal memory response is compareed, compares actual storage model and responds and detect device mistake.Can by it is built-in from
Each device in slowdown monitoring circuit, to realize the built-in self-test test to memory.Similarly, the second built-in self-test is tested,
It can be tested using identical process.
As shown in figure 5, S450 includes: in one of the embodiments,
S452 is obtained the region for not having data by response analyzer and responded to the test of test vector；
S454 compares the normal memory that prestores and responds to the normal response of test vector and test, when normal response with
When test response is identical, determine that the test of the first built-in self-test passes through, when normal response and not identical test response, discriminating test
Do not pass through.
Processor can obtain memory to be measured to the real response of test vector by response analysis module, and compare pre-
The response deposited, to analyze the actual test result for obtaining memory to be measured.Consistent, i.e., the test of memory to be measured is responded when two kinds
When response in the process is identical as response of the normal memory to the test vector, it is possible to determine that there is no ask memory to be measured
Topic, test pass through, and when responding different, determine memory to be measured there are problem, test does not pass through.One embodiment wherein
In, response analysis module includes exclusive or comparator, and exclusive or comparator is to the test response data of memory and prestores ideal
Response carries out xor operation, judges whether real response is correct accordingly.Current storage to be measured can be effectively confirmed by comparison
Device whether there is Problem of Failure.
In one of the embodiments, after S450 further include:
According to the difference of normal response and test response, the address information in memory exception region is obtained, and generates and deposits
The address information of reservoir abnormal area corresponds to memory test report.
When memory to be measured is to the response of test vector and the different response of normal memory, response analysis module is also
It can be analyzed according to the difference that the two responds, according to different responses, position tool of the disabling portion in memory to be measured
The address space of body generates corresponding memory test report.Tester can be reported clearly by memory test
Solve memory there are the problem of, improve the efficiency of test.
S600 includes: in one of the embodiments,
When the test of the first built-in self-test passes through, data in the region for having data are read according to processor pointer, will be counted
There is not the region of data according to write-in, while processor pointer being jumped to the storage address for not having the region of data.
Processor pointer is directed toward the data for having the region of data, when data in the complete region for having data of processor migration
When in the region for not having data, at the same the pointer of processor jumped to do not have data region move after correspondence position
It sets, so that the memory of storage program can also carry out memory built from test originally.
The method for testing memory of the application is applied to memory testing system, memory in one of the embodiments,
Test macro includes testing control module and memory built self-testing circuit, memory built self-testing circuit and memory to be measured
Connection, memory built self-testing circuit includes test vector generation circuit, built-in self-test control circuit, response analyzer.Method
It include: to obtain the first test signal and the second test signal, the first test signal is used for not stored number in memory to be measured
According to region carry out memory built from testing, the second test signal be used for the region of storing data in memory to be measured into
The test of line storage built-in self-test.The first test signal of input controls test vector generation circuit to test vector generation circuit
Generate corresponding test vector；Test vector is sent to built-in self-test control circuit, passes through built-in self-test control circuit input test
Vector is to the region for not having data；The region for not having data is obtained by response analyzer to ring the test of test vector
It answers, the test result for obtaining the test of the first built-in self-test is responded according to test.Simultaneously according to the difference of normal response and test response
It is different, the address information in memory exception region is obtained, and generate storage corresponding with the address information in the memory exception region
Device test report.When the test of the first built-in self-test does not pass through, determine that memory to be measured is unqualified.When the first built-in self-test is tested
By when, read according to processor pointer and have data in the regions of data, write data into the region for not having data, simultaneously
Processor pointer is jumped to the storage address for not having the region of data.Testing control module is written into second test signal,
The second test signal of input controls test vector generation circuit and generates corresponding test vector to test vector generation circuit；It sends
Test vector passes through built-in self-test control circuit input test vector to the area for not having data to built-in self-test control circuit
Domain；The region for not having data is obtained by response analyzer to respond the test of test vector；Compare the normal storage prestored
Device responds the normal response of test vector and test, when normal response is identical as test response, determines the second built-in self-test
Test passes through, and when normal response and not identical test response, determines that the test of the second built-in self-test does not pass through.It is built-in according to second
The test result of memory is obtained from the result of test.
It should be understood that although each step in the flow chart of Fig. 2-5 is successively shown according to the instruction of arrow,
These steps are not that the inevitable sequence according to arrow instruction successively executes.Unless expressly stating otherwise herein, these steps
Execution there is no stringent sequences to limit, these steps can execute in other order.Moreover, at least one in Fig. 2-5
Part steps may include that perhaps these sub-steps of multiple stages or stage are not necessarily in synchronization to multiple sub-steps
Completion is executed, but can be executed at different times, the execution sequence in these sub-steps or stage is also not necessarily successively
It carries out, but can be at least part of the sub-step or stage of other steps or other steps in turn or alternately
It executes.
As shown in fig. 6, the application also provides a kind of memorizer test device, device includes:
Signal acquisition module 200, for obtaining the first test signal and the second test signal, the first test signal is used for
Memory built is carried out from testing to the region of not stored data in memory to be measured, the second test signal to be measured for depositing
The region of storing data carries out memory built from test in reservoir；
First testing control module 400, for passing through the first test signal of testing control module input to memory built
Self-testing circuit carries out the first built-in self-test test to the region for not having data, obtains the test knot of the first built-in self-test test
Fruit；
Data Migration module 600, for when the test of the first built-in self-test passes through, migration to have data in the region of data
To the region for not having data；
Second testing control module 800, for passing through the second test signal of testing control module input to memory built
Self-testing circuit carries out the second built-in self-test test to the region for having data, is obtained according to the result of the second built-in self-test test
The test result of memory.
It in one of the embodiments, further include fault interrupting determination module, fault interrupting determination module, for when first
When built-in self-test test does not pass through, determine that memory to be measured is unqualified.
Memory built self-testing circuit includes test vector generation circuit, built-in self-test control in one of the embodiments,
Circuit processed, response analyzer, the first testing control module 400 are specifically used for: the first test signal of input to test vector generates
Circuit, control test vector generation circuit generate corresponding test vector；Test vector is sent to built-in self-test control circuit, is passed through
Built-in self-test control circuit input test vector is to the region for not having data；There are not data by response analyzer acquisition
Region responds the test of test vector, and the test result for obtaining the test of the first built-in self-test is responded according to test.
The first testing control module 400 is also used in one of the embodiments: not being had by response analyzer acquisition
The region of data responds the test of test vector；Normal response and test of the normal memory that comparison prestores to test vector
Response determines that the test of the first built-in self-test passes through when normal response is identical as test response, when normal response and test respond
When not identical, discriminating test does not pass through.
The first testing control module 400 is also used in one of the embodiments: being responded according to normal response and test
Difference obtains the address information in memory exception region, and generates memory corresponding with the address information in memory exception region
Test report.
Data Migration module in one of the embodiments, is used for: when the test of the first built-in self-test passes through, according to place
Reason device pointer, which is read, has data in the regions of data, writes data into the region for not having data, while by processor pointer
Jump to the storage address for not having the region of data.
Specific about memorizer test device limits the restriction that may refer to above for method for testing memory,
This is repeated no more.Modules in above-mentioned memorizer test device can come fully or partially through software, hardware and combinations thereof
It realizes.Above-mentioned each module can be embedded in the form of hardware or independently of in the processor in computer equipment, can also be with software
Form is stored in the memory in computer equipment, executes the corresponding operation of the above modules in order to which processor calls.
In one embodiment, a kind of computer equipment is provided, which can be terminal, internal structure
Figure can be as shown in Figure 7.The computer equipment includes processor, the memory, network interface, display connected by system bus
Screen and input unit.Wherein, the processor of the computer equipment is for providing calculating and control ability.The computer equipment is deposited
Reservoir includes non-volatile memory medium, built-in storage.The non-volatile memory medium is stored with operating system and computer journey
Sequence.The built-in storage provides environment for the operation of operating system and computer program in non-volatile memory medium.The calculating
The network interface of machine equipment is used to communicate with external terminal by network connection.When the computer program is executed by processor with
Realize a kind of method for testing memory.The display screen of the computer equipment can be liquid crystal display or electric ink is shown
Screen, the input unit of the computer equipment can be the touch layer covered on display screen, be also possible on computer equipment shell
Key, trace ball or the Trackpad of setting can also be external keyboard, Trackpad or mouse etc..
It will be understood by those skilled in the art that structure shown in Fig. 7, only part relevant to application scheme is tied
The block diagram of structure does not constitute the restriction for the computer equipment being applied thereon to application scheme, specific computer equipment
It may include perhaps combining certain components or with different component layouts than more or fewer components as shown in the figure.
In one embodiment, a kind of computer equipment, including memory and processor are provided, is stored in memory
Computer program, the processor perform the steps of when executing computer program
The first test signal and the second test signal are obtained, the first test signal is used for not stored in memory to be measured
The region of data carries out memory built from testing, and the second test signal is used for the region to storing data in memory to be measured
Memory built is carried out from test；
By testing control module input the first test signal to memory built self-testing circuit, to the area for not having data
Domain carries out the first built-in self-test test, obtains the test result of the first built-in self-test test；
When the test of the first built-in self-test passes through, migration has in the regions of data data to the region for not having data；
By testing control module input the second test signal to memory built self-testing circuit, to the region for having data
The second built-in self-test test is carried out, the test result of memory is obtained according to the result of the second built-in self-test test.
In one embodiment, it is also performed the steps of when processor executes computer program when the first built-in self-test is surveyed
When examination does not pass through, determine that memory to be measured is unqualified.
In one embodiment, input the first test signal is also performed the steps of when processor executes computer program
To test vector generation circuit, controls test vector generation circuit and generate corresponding test vector；Send test vector to it is built-in from
Control circuit is surveyed, built-in self-test control circuit input test vector to the region for not having data is passed through；Pass through response analyzer
It obtains the region for not having data to respond the test of test vector, the survey for obtaining the test of the first built-in self-test is responded according to test
Test result.
In one embodiment, it also performs the steps of when processor executes computer program and is obtained by response analyzer
The region for not having data is taken to respond the test of test vector；Normal sound of the normal memory that comparison prestores to test vector
Should be responded with test, when normal response is identical as test response, determine that the first built-in self-test is tested and passes through, when normal response and
When test response is not identical, discriminating test does not pass through.
In one embodiment, it is also performed the steps of when processor executes computer program according to normal response and is surveyed
The difference of response is tried, obtains the address information in memory exception region, and generate the address information pair with memory exception region
Memory test is answered to report.
In one embodiment, it is also performed the steps of when processor executes computer program when the first built-in self-test is surveyed
It is out-of-date to ping, and data in the region for having data are read according to processor pointer, write data into the region for not having data, together
When processor pointer is jumped to the storage address for not having the region of data.
In one embodiment, a kind of computer readable storage medium is provided, computer program is stored thereon with, is calculated
Machine program performs the steps of when being executed by processor
The first test signal and the second test signal are obtained, the first test signal is used for not stored in memory to be measured
The region of data carries out memory built from testing, and the second test signal is used for the region to storing data in memory to be measured
Memory built is carried out from test；
By testing control module input the first test signal to memory built self-testing circuit, to the area for not having data
Domain carries out the first built-in self-test test, obtains the test result of the first built-in self-test test；
When the test of the first built-in self-test passes through, migration has in the regions of data data to the region for not having data；
By testing control module input the second test signal to memory built self-testing circuit, to the region for having data
The second built-in self-test test is carried out, the test result of memory is obtained according to the result of the second built-in self-test test.
In one embodiment, it also performs the steps of when computer program is executed by processor when the first built-in self-test
When test does not pass through, determine that memory to be measured is unqualified.
In one embodiment, input the first test letter is also performed the steps of when computer program is executed by processor
Number to test vector generation circuit, controls test vector generation circuit and generate corresponding test vector；Test vector is sent to built-in
Self-measured/controlled circuit passes through built-in self-test control circuit input test vector to the region for not having data；Pass through response analysis
Device obtains the region for not having data and responds to the test of test vector, is responded according to test and obtains the test of the first built-in self-test
Test result.
In one embodiment, it is also performed the steps of when computer program is executed by processor and passes through response analyzer
The region for not having data is obtained to respond the test of test vector；The normal memory prestored is compared to the normal of test vector
Response is responded with test, when normal response is identical as test response, is determined that the test of the first built-in self-test passes through, is worked as normal response
When not identical as test response, discriminating test does not pass through.
In one embodiment, also performed the steps of when computer program is executed by processor according to normal response with
The difference of response is tested, obtains the address information in memory exception region, and generate the address information with memory exception region
Corresponding memory test report.
In one embodiment, it also performs the steps of when computer program is executed by processor when the first built-in self-test
When test passes through, data in the region for having data are read according to processor pointer, write data into the region for not having data,
Processor pointer is jumped to the storage address for not having the region of data simultaneously.
Those of ordinary skill in the art will appreciate that realizing all or part of the process in above-described embodiment method, being can be with
Instruct relevant hardware to complete by computer program, computer program to can be stored in a non-volatile computer readable
It takes in storage medium, the computer program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, this Shen
Please provided by any reference used in each embodiment to memory, storage, database or other media, may each comprise
Non-volatile and/or volatile memory.Nonvolatile memory may include read-only memory (ROM), programming ROM
(PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM) or flash memory.Volatile memory may include
Random access memory (RAM) or external cache.By way of illustration and not limitation, RAM is available in many forms,
Such as static state RAM (SRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate sdram (DDRSDRAM), enhancing
Type SDRAM (ESDRAM), synchronization link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM
(RDRAM), direct memory bus dynamic ram (DRDRAM) and memory bus dynamic ram (RDRAM) etc..
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Above embodiments only express the several embodiments of the application, and the description thereof is more specific and detailed, but can not
Therefore it is construed as limiting the scope of the patent.It should be pointed out that for those of ordinary skill in the art,
Under the premise of not departing from the application design, various modifications and improvements can be made, these belong to the protection scope of the application.
Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of method for testing memory, which is characterized in that be applied to memory testing system, the memory testing system packet
Testing control module interconnected and memory built self-testing circuit are included, the memory built self-testing circuit is deposited with to be measured
Reservoir connection；
The method for testing memory includes:
The first test signal and the second test signal are obtained, the first test signal is used for not stored in memory to be measured
The region of data carries out memory built from testing, and the second test signal is used for storing data in memory to be measured
Region carries out memory built from test；
By testing control module input the first test signal to memory built self-testing circuit, there are not data to described
Region carry out the first built-in self-test test, obtain the test result of first built-in self-test test；
When first built-in self-test test passes through, there are in the region of data data described in migration to described and do not have data
Region；
By testing control module input the second test signal to memory built self-testing circuit, there are data to described
Region carries out the second built-in self-test test, and the test knot of the memory is obtained according to the result that second built-in self-test is tested
Fruit.
2. the method according to claim 1, wherein described pass through the first test of testing control module input
Signal carries out the first built-in self-test test to memory built self-testing circuit, to the region for not having data, described in acquisition
After the test result of first built-in self-test test, further includes:
When first built-in self-test test does not pass through, determine that the memory to be measured is unqualified.
3. the method according to claim 1, wherein memory built self-testing circuit includes that test vector generates electricity
Road, built-in self-test control circuit, response analyzer, it is described to pass through the first test signal of testing control module input to storage
Device build-in self-test, carrying out the test of the first built-in self-test to the region for not having data includes:
The first test signal is inputted to test vector generation circuit, the test vector generation circuit is controlled and generates corresponding survey
Try vector；
The test vector is sent to the built-in self-test control circuit, the survey is inputted by the built-in self-test control circuit
Vector is tried to the region for not having data；
It obtains the region for not having data by the response analyzer to respond the test of the test vector, according to institute
State the test result that test response obtains the first built-in self-test test.
4. according to the method described in claim 3, it is characterized in that, not having data by the way that response analyzer acquisition is described
Region the test of the test vector is responded, the test of the first built-in self-test test is accordingly obtained according to the test
Result includes:
The region for not having data is obtained by the response analyzer to respond the test of the test vector；
It compares the normal memory prestored to respond the normal response of the test vector and the test, when the normal response
When identical as the test response, determine that the first built-in self-test test passes through, when the normal response and the test are rung
When should be not identical, discriminating test pass through.
5. according to the method described in claim 4, it is characterized in that, it is described compare the normal memory that prestores to it is described test to
The normal response of amount and the test respond, and when the normal response is identical as the test response, judgement is described not to be had
The region of data is qualified, when the normal response and not identical test response, determines the region for not having data
After unqualified, further includes:
According to the difference of the normal response and the test response, the address information in memory exception region is obtained, and generate
Memory test report corresponding with the address information in the memory exception region.
6. the method according to claim 1, wherein it is described when first built-in self-test test pass through when, move
Having data to the region for not having data in the region of data described in shifting includes:
When first built-in self-test test passes through, data in the region for having data are read according to processor pointer, by institute
The data write-in region for not having data is stated, while the processor pointer is jumped into the region for not having data
Storage address.
7. a kind of memorizer test device, which is characterized in that the memorizer test device is applied to memory testing system, institute
Stating memory testing system includes memorizer test device, testing control module and memory built self-testing circuit, the dress
It sets and includes:
Signal acquisition module, for obtain first test signal and second test signal, it is described first test signal for pair
The region of not stored data carries out memory built from testing in memory to be measured, and the second test signal is used for to be measured
The region of storing data carries out memory built from test in memory；
First testing control module, for being surveyed certainly by the first test signal of testing control module input to memory built
Circuit carries out the first built-in self-test test to the region for not having data, obtains the survey of the first built-in self-test test
Test result；
Data Migration module, for having number in the region of data described in migration when first built-in self-test test passes through
According to the region for not having data described in；
Second testing control module, for being surveyed certainly by the second test signal of testing control module input to memory built
Circuit carries out the second built-in self-test test to the region for having data, the result tested according to second built-in self-test
Obtain the test result of the memory.
8. device according to claim 7, which is characterized in that further include fault interrupting determination module, the fault interrupting
Determination module, for determining that the memory to be measured is unqualified when first built-in self-test test does not pass through.
9. a kind of computer equipment, including memory and processor, the memory are stored with computer program, feature exists
In the step of processor realizes any one of claims 1 to 6 the method when executing the computer program.
10. a kind of computer readable storage medium, is stored thereon with computer program, which is characterized in that the computer program
The step of method described in any one of claims 1 to 6 is realized when being executed by processor.
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