CN109581197A - A kind of SiP encapsulation test macro based on jtag interface - Google Patents
A kind of SiP encapsulation test macro based on jtag interface Download PDFInfo
- Publication number
- CN109581197A CN109581197A CN201811629155.6A CN201811629155A CN109581197A CN 109581197 A CN109581197 A CN 109581197A CN 201811629155 A CN201811629155 A CN 201811629155A CN 109581197 A CN109581197 A CN 109581197A
- Authority
- CN
- China
- Prior art keywords
- register
- input terminal
- module
- test
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0433—Sockets for IC's or transistors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The SiP encapsulation test macro based on jtag interface that the invention discloses a kind of, including jtag interface, SOC TAP controller, command register and the MUX module exported for TDO, jtag interface is for controlling SOC TAP controller, SOC TAP controller is used to the instruction of SOC TAP controller being sent to command register, command register is used to export the control signal of corresponding test pattern according to the received instruction of command register, and the output end of command register is also electrically connected with the input terminal of required test device.The present invention allows multiple debugging tools to access and debug the TAP controller of respective debugged kernel, and debugging operations are carried out on other kernels without influencing, and has the advantages that structure is simple, is compatible with JTAG protocol.
Description
Technical field
The invention belongs to ic test technique fields, and in particular to a kind of SiP encapsulation survey based on jtag interface
Test system.
Background technique
System in package (Systemin Package, SiP) be by multiple active electron components with different function and
Other devices such as optional passive device and MEMS or optical device are preferentially assemblied together, and realize certain function
Single standard packaging part, forms a system or subsystem.From framework, SiP be by multiple functions chip, including SoC,
The polymorphic types functional chip such as ADC, DAC, memory, LDO is integrated in an encapsulation, to realize complicated system function, thus
Carry out huge challenge to the calibration tape of SiP, when especially integrated each working frequency of chip is higher and higher, pin is more and more,
It is even more so.The measuring technology of SiP achieves many research achievements as an important research hotspot.JTAG is as one
Kind is the standard for meeting test and debugging and design, is often embedded in large scale integrated circuit, such as SoC, CPU, DSP, FPGA
Deng so multiple devices in SiP may contain jtag interface, therefore jtag interface can be multiplexed as a preferable choosing
It selects.
The JTAG protocol of the current all incompatible standard of SiP self-test technology based on jtag interface, test logic are opposite
It is more complicated, higher cost.The scheme of the JTAG interconnection of current existing multiple devices, such as daisy chain (Daisy-Chain)
Structure, TLM (TAP Linking Module) connection and parallel more TAP controller interconnection debugging structures etc., these test structures
Have the shortcomings that different.
Therefore, the SiP encapsulation test and debugging technology based on jtag interface that it is urgent to provide a kind of has structure simple, simultaneous
The advantages of holding JTAG protocol.
Summary of the invention
The SiP encapsulation test macro based on jtag interface that in order to solve the above-mentioned technical problems, the present invention provides a kind of.
In order to achieve the above object, technical scheme is as follows:
The present invention provides a kind of SiP encapsulation test macro based on jtag interface, including jtag interface, SOC TAP control
Device, command register and the MUX module for TDO output processed, the input terminal of the jtag interface and SOC TAP controller
Electrical connection is for controlling SOC TAP controller, the input of the output end and command register of the SOC TAP controller
End electrical connection is for being sent to command register, the output end and MUX of described instruction register for the instruction of SOC TAP controller
The input terminal electrical connection of module is for exporting the control signal of corresponding test pattern, institute according to the received instruction of command register
The output end for stating command register is also electrically connected with the input terminal of required test device, it is described test device output end with
The input terminal of MUX module is electrically connected for the signal that outputs test result.
As a preferred option, further include BYPASS shift register, the input terminal of the BYPASS shift register with
The output end of command register is electrically connected；When not needing to carry out any test, is instructed by BYPASS and post BYPASS
Storage is connected between TDI and TDO, a shortest serial path of length is provided between TDI and TDO, to allow to test
Data quickly move through other chip that current chip is sent on development board up.
It as a preferred option, further include ID register, the output of the input terminal and command register of the ID register
End electrical connection, the ID register memory contain production firm's information, parts number, version information and the ID for storing SoC
Number.
As a preferred option, further include boundary scan chain register, the input terminal of the boundary scan chain register with
The output end of command register is electrically connected, and the output end of the boundary scan chain register is electrically connected with each test device, is used
In between it is each test device connectivity tested and to test device input and output be observed and control, with
Achieve the purpose that the internal logic for testing device.
It as a preferred option, further include CPU module, the input terminal of the CPU module and the output end of command register
Electrical connection, the output end of the CPU module is electrically connected with the input terminal of MUX module, for debugging to CPU module.
It as a preferred option, further include bus module, the output of the input terminal and command register of the bus module
End electrical connection, the output end of the bus module is electrically connected with the input terminal of MUX module, for debugging to bus module.
As a preferred option, further include Cache module, the input terminal of the Cache module and command register it is defeated
Outlet electrical connection, the output end of the Cache module is electrically connected with the input terminal of MUX module, for adjusting to Cache module
Examination.
It as a preferred option, further include that MBIST enables register, the MBIST enables the input terminal and finger of register
The output end of register is enabled to be electrically connected, the output end that the MBIST enables register is electrically connected with the input terminal of MUX module, is used
It is debugged in enabling register to MBIST.
It as a preferred option, further include that DAC performance test enables register and DAC performance test frequency-selecting module,
The DAC performance test enables the output end of register, the input terminal of DAC performance test frequency-selecting module and command register
Electrical connection, the DAC performance test enable register, the output end of DAC performance test frequency-selecting module and MUX module, show
The input terminal of wave device is electrically connected, and is tested for the performance to DAC.
It as a preferred option, further include that ADC performance test enables register, the ADC performance test enables register
Input terminal be electrically connected with the output end of command register, the ADC performance test enable register output end and MUX module
Input terminal electrical connection, tested for the performance to ADC.
The invention has the following advantages:
(1) present invention only uses a jtag interface, so that it may to SiP encapsulation in each device individually carry out test with
Debugging, and the normal use of other IP jtag interfaces is not influenced；
(2) present invention can control a variety of test patterns inside SoC and enabled polymorphic type while test and debugging
Test logic；
(3) when the present invention debugs any one module, other test modules will be in invalid state, in terms of the external world
Still only one JTAG, is thus multiplexed debugging routine.
(4) when the present invention carries out other chip testings, by integrated data generation and data analysis module inside SoC, with right
Other chips generate excitation or export to it and are monitored, analyze, comparing, and the test pattern is also controlled by jtag interface
System.
Detailed description of the invention
Fig. 1 is a kind of structural block diagram of the SiP encapsulation test macro based on jtag interface of the present invention.
Specific embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
In order to reach the purpose of the present invention, as shown in Figure 1, providing a kind of base in one of embodiment of the invention
In the SiP encapsulation test macro of jtag interface, including jtag interface, SOC TAP controller, command register and it is used for
The MUX module of TDO output, the jtag interface are electrically connected with the input terminal of SOC TAP controller for SOC TAP controller
It is controlled, the output end of the SOC TAP controller is electrically connected for controlling SOC TAP with the input terminal of command register
The instruction of device is sent to command register, and the output end of described instruction register is electrically connected for root with the input terminal of MUX module
Export the control signal of corresponding test pattern according to the received instruction of command register, the output end of described instruction register also with
The input terminal electrical connection of required test device, the output end of the test device is electrically connected with the input terminal of MUX module to be used for
Output test result signal.
SoC TAP controller completely compatible 1149.1 standard, it is specified that common instruction in IEEE1149.1 standard
(shown in table 1) and its relevant register.The relevant register of IEEE1149.1 standard is specific as follows: the ID register of standard
(hereinafter referred to as R_ID register), BYPASS shift register (hereinafter referred to as R_BP register), command register are (hereinafter referred to as
R_inst register) and boundary scan chain register (hereinafter referred to as R_BSC register).It include production in R_ID register
The ID number of manufacturer's information, parts number, the version information of device and SoC, is instructed using IDCODE, so that it may by TAP come
Determine the relevant information of device.R_inst register allows specific instruction to be loaded onto command register, for selecting to need
The test to be executed, or the test data that selection needs to access.R_BP register is one one shift register, is passed through
BYPASS instruction, BYPASS register is connected between TDI and TDO.It, will when not needing to carry out any test
BYPASS register is connected between TDI and TDO, and a shortest serial path of length is provided between TDI and TDO, thus
Allow test data that can quickly move through other chip that current chip is sent on development board up.R_BSC register is one
A boundary scan chain register can carry out the continuity testing between component by boundary scan chain register, prior to go back
The input and output of test device can be observed and be controlled, to achieve the purpose that test the internal logic of device.INSERT
Instruction is the important instruction defined inside IEEE1149.1 standard, and in conjunction with boundary scan chain, which allows to exploitation
The system logic of device carries out close beta on plate.In debugging, boundary scan chain register is most important, using also the most frequency
It is numerous.
Table 1: each instruction and its corresponding test pattern list.
On the basis of IEEE1149.1 standard, SoC TAP controller has expanded some privately owned instruction and data registers,
To help more convenient and comprehensive test and debugging, relevant privately owned register specific as follows: MBIST enables register, ADC
Enabled register can be tested, DAC performance test enables register, CPU JTAG resets control register, bus reset control is posted
Storage, Cache reset control register and MUX mask register.MBIST enable register control MBIST function whether by
It is enabled, it is instructed by MBIST_EN, can control the enabled and disabling of MBIST module.ADC performance test enables register control
Whether ADC performance test is enabled, and is instructed by ADC_TEST_EN, can control the enabled of ADC performance test module and prohibits
With.DAC performance test enables whether register control DAC performance test is enabled, and is instructed, can be controlled by DAC_TEST_EN
The enabled and disabling of DAC performance test module processed.CPU JTAG resets the reset signal of control register control CPU JTAG, leads to
CPUJTAG_RST instruction is crossed, CPU JTAG module is can control and is in reset state or test mode.Bus JTAG resets control
The reset signal of register control bus JTAG processed, is instructed by bus JTAG_RST, be can control bus JTAG module and is in
Reset state or test mode.CACHE JTAG resets the reset signal of control register control CACHE JTAG, passes through
CACHE JTAG_RST instruction, can control CACHE JTAG module and is in reset state or test mode.MUX selection deposit
Device controls the output of TDO pin, is instructed by TDO_MUX_SEL, in CPUJTAG, bus JTAG, CACHE JTAG, R_ID
Selected in JTAG, R_BP JTAG and R_BSC JTAG, MBIST result and ADC the performance test results all the way result drawn by TDO
Foot output.
SiP further includes SoC TAP controller and command register, is mainly controlled using a jtag interface SoC TAP
Device is controlled, thus SoC TAP controller to command register send instruction (table 1 list command bits and its corresponding to
Test pattern), command register exports the control signal of corresponding test pattern according to the instruction received, these signals have:
The enable signal of MBIST, the enable signal of ADC test module, the reset signal of CPU, the reset signal of bus, Cache's answers
Position signal, the selection signal of MUX, the selection signal of digital signal MUX., reset enabled by these, MUX selection signal are realized
To SiP encapsulation in each device individually tested and debugged, while can also control a variety of test patterns inside SoC and
The test logic of enabled ADC, DAC.
It specifically, further include BYPASS shift register, the input terminal and order register of the BYPASS shift register
The output end of device is electrically connected；When not needing to carry out any test, is instructed by BYPASS and connect BYPASS register
To between TDI and TDO, a shortest serial path of length is provided between TDI and TDO, to allow test data quick
Ground is sent to other chip on development board up by current chip.
It specifically, further include ID register, the input terminal of the ID register is electrically connected with the output end of command register,
The ID register memory contains production firm's information, parts number, version information and the ID number for storing SoC.
It specifically, further include boundary scan chain register, the input terminal and order register of the boundary scan chain register
The output end of device is electrically connected, and the output end of the boundary scan chain register is electrically connected with each test device, for each
Connectivity between test device is tested and the input and output of test device is observed and is controlled, to reach test
The purpose of the internal logic of device.
It specifically, further include CPU module, the input terminal of the CPU module is electrically connected with the output end of command register, institute
The output end for stating CPU module is electrically connected with the input terminal of MUX module, for debugging to CPU module.
It specifically, further include bus module, the input terminal of the bus module is electrically connected with the output end of command register,
The output end of the bus module is electrically connected with the input terminal of MUX module, for debugging to bus module.
It specifically, further include Cache module, the input terminal of the Cache module and the output end of command register are electrically connected
It connects, the output end of the Cache module is electrically connected with the input terminal of MUX module, for debugging to Cache module.
It specifically, further include that MBIST enables register, the MBIST enables the input terminal and command register of register
Output end electrical connection, the MBIST enable register output end be electrically connected with the input terminal of MUX module, be used for MBIST
Enabled register is debugged.
It specifically, further include that DAC performance test enables register and DAC performance test frequency-selecting module, the DAC
Enabled register can be tested, the input terminal of DAC performance test frequency-selecting module is electrically connected with the output end of command register, institute
State the input that DAC performance test enables register, the output end of DAC performance test frequency-selecting module and MUX module, oscillograph
End electrical connection, is tested for the performance to DAC.
It specifically, further include that ADC performance test enables register, the ADC performance test enables the input terminal of register
It is electrically connected with the output end of command register, the ADC performance test enables the output end of register and the input terminal of MUX module
Electrical connection, is tested for the performance to ADC.
When being debugged to CPU module, it is therefore an objective to export cpu_tdo signal outward by TDO pin；Process is main
It is: SoC TAP controller is controlled by jtag interface, the instruction of cpu test mode is issued to command register, according to
Table 1 refer to JTAG will in reset state simultaneously by command register output bus, the reset signal of two modules of Cache
The disabling signal for enabling register output MBIST and ADC test module makes the two test modules will be in invalid state, simultaneously
Command register exports the solution reset signal of CPU module and MUX selects cpu_tdo signal, from it is extraneous still only one
Thus CPU JTAG can be multiplexed the debugging routine of CPU.
When being debugged to bus module, it is therefore an objective to export bus _ tdo signal outward by TDO pin；Process is main
It is: SoC TAP controller is controlled by jtag interface, the instruction of bus test mode, root is issued to command register
Refer to JTAG will in reset state simultaneously by the reset signal of command register output two modules of CPU, Cache according to table 1
The disabling signal for enabling register output MBIST and ADC test module makes the two test modules will be in invalid state, simultaneously
The solution reset signal and MUX of command register output bus module select bus _ tdo signal.
When being debugged to Cache module, it is therefore an objective to export cache_tdo signal outward by TDO pin；Process master
If: SoC TAP controller is controlled by jtag interface, the instruction of Cache test pattern is issued to command register,
Make JTAG will be in reset state, simultaneously by command register output CPU, the reset signal of two modules of bus according to table 1
Command register exports the disabling signal of MBIST and ADC test module, makes the two test modules will be in invalid state, together
When command register output Cache module solution reset signal and MUX select cache_tdo signal.
When carrying out MBIST test, it is therefore an objective to export MBIST result outward by TDO pin；Process is mainly: passing through
Jtag interface controls SoC TAP controller, issues MBIST_EN instruction and TDO_MUX_SEL choosing to command register
The instruction for selecting output MBIST result, according to table 1, TDO final output MBIST result.
When carrying out ADC performance test, it is therefore an objective to export ADC the performance test results outward by TDO pin；Process is main
It is: SoC TAP controller is controlled by jtag interface, issues ADC_TEST_EN instruction and TDO_ to command register
The instruction of MUX_SEL selection output ADC the performance test results, according to table 1, TDO final output ADC the performance test results.
When carrying out DAC performance test, it is therefore an objective to export DAC the performance test results outward by TDO pin；Process is main
It is: SoC TAP controller is controlled by jtag interface, issues DAC_TEST_EN instruction to command register, make SOC
After internal DDS data or normal data are converted by DAC module, data are analyzed by oscillograph.
What has been described above is only a preferred embodiment of the present invention, it is noted that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, various modifications and improvements can be made, these belong to the present invention
Protection scope.
Claims (10)
1. a kind of SiP encapsulation test macro based on jtag interface, which is characterized in that controlled including jtag interface, SOC TAP
The input terminal electricity of device, command register and the MUX module for TDO output, the jtag interface and SOC TAP controller
Connection is for controlling SOC TAP controller, the output end of the SOC TAP controller and the input terminal of command register
Electrical connection is for being sent to command register, the output end and MUX mould of described instruction register for the instruction of SOC TAP controller
The input terminal electrical connection of block is described for exporting the control signal of corresponding test pattern according to the received instruction of command register
The output end of command register is also electrically connected with the input terminal of required test device, the output end and MUX of the test device
The input terminal of module is electrically connected for the signal that outputs test result.
2. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include
The input terminal of BYPASS shift register, the BYPASS shift register is electrically connected with the output end of command register；Not
When needing to carry out any test, instructed by BYPASS and BYPASS register be connected between TDI and TDO, in TDI and
A shortest serial path of length is provided between TDO, so that allowing test data to quickly move through current chip is sent to exploitation
Other chip on plate gets on.
3. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include ID
The input terminal of register, the ID register is electrically connected with the output end of command register, and the ID register memory contains life
Produce manufacturer's information, parts number, version information and the ID number for storing SoC.
4. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include side
The input terminal of boundary's scan chain register, the boundary scan chain register is electrically connected with the output end of command register, the side
The output end of boundary's scan chain register is electrically connected with each test device, for surveying between the connectivity each test device
It tries and the input and output of test device is observed and is controlled, to achieve the purpose that test the internal logic of device.
5. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include CPU
Module, the input terminal of the CPU module are electrically connected with the output end of command register, the output end and MUX mould of the CPU module
The input terminal of block is electrically connected, for debugging to CPU module.
6. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include total
Wire module, the input terminal of the bus module are electrically connected with the output end of command register, the output end of the bus module with
The input terminal of MUX module is electrically connected, for debugging to bus module.
7. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include
The input terminal of Cache module, the Cache module is electrically connected with the output end of command register, the output of the Cache module
End is electrically connected with the input terminal of MUX module, for debugging to Cache module.
8. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include
MBIST enables register, and the input terminal that the MBIST enables register is electrically connected with the output end of command register, described
The output end that MBIST enables register is electrically connected with the input terminal of MUX module, is debugged for enabling register to MBIST.
9. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include DAC
Performance test enables register and DAC performance test frequency-selecting module, the DAC performance test enable register, DAC performance
The input terminal of test frequency selecting module is electrically connected with the output end of command register, the DAC performance test enable register,
The output end of DAC performance test frequency-selecting module is electrically connected with the input terminal of MUX module, oscillograph, for the performance to DAC
It is tested.
10. the SiP encapsulation test macro according to claim 1 based on jtag interface, which is characterized in that further include
ADC performance test enables register, and the ADC performance test enables the input terminal of register and the output end electricity of command register
Connection, the output end that the ADC performance test enables register is electrically connected with the input terminal of MUX module, for the performance to ADC
It is tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811629155.6A CN109581197A (en) | 2018-12-28 | 2018-12-28 | A kind of SiP encapsulation test macro based on jtag interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811629155.6A CN109581197A (en) | 2018-12-28 | 2018-12-28 | A kind of SiP encapsulation test macro based on jtag interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109581197A true CN109581197A (en) | 2019-04-05 |
Family
ID=65932342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811629155.6A Pending CN109581197A (en) | 2018-12-28 | 2018-12-28 | A kind of SiP encapsulation test macro based on jtag interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109581197A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112466381A (en) * | 2020-11-26 | 2021-03-09 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112612264A (en) * | 2020-12-22 | 2021-04-06 | 北京时代民芯科技有限公司 | Serial port self-testing method in CAN bus controller |
| CN113671360A (en) * | 2020-05-13 | 2021-11-19 | 圣邦微电子（北京）股份有限公司 | I2C interface device testing method and device and I2C interface device |
| CN114089172A (en) * | 2021-11-22 | 2022-02-25 | 中国电子科技集团公司第五十八研究所 | JTAG debugging method of PCIE IO expansion chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100357751C (en) * | 2004-02-26 | 2007-12-26 | 联想(北京)有限公司 | JTAG module and debug method applying the module |
| US20090019328A1 (en) * | 2006-03-01 | 2009-01-15 | Koninklijke Philips Electronics N.V. | Ic circuit with test access control circuit using a jtag interface |
| CN101719088B (en) * | 2009-11-23 | 2012-09-26 | 龙芯中科技术有限公司 | Device and method for detecting processor chip on line |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN103033736A (en) * | 2011-09-30 | 2013-04-10 | 飞思卡尔半导体公司 | Methods and apparatus for testing multiple-IC devices |
| CN105450251A (en) * | 2015-12-07 | 2016-03-30 | 中国电子科技集团公司第十研究所 | Miniature double-receiving and double-sending universal terminal system level package method |
-
2018
- 2018-12-28 CN CN201811629155.6A patent/CN109581197A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100357751C (en) * | 2004-02-26 | 2007-12-26 | 联想(北京)有限公司 | JTAG module and debug method applying the module |
| US20090019328A1 (en) * | 2006-03-01 | 2009-01-15 | Koninklijke Philips Electronics N.V. | Ic circuit with test access control circuit using a jtag interface |
| CN101395488A (en) * | 2006-03-01 | 2009-03-25 | 皇家飞利浦电子股份有限公司 | IC circuit with test access control circuit using a JTAG interface |
| CN101719088B (en) * | 2009-11-23 | 2012-09-26 | 龙芯中科技术有限公司 | Device and method for detecting processor chip on line |
| CN103033736A (en) * | 2011-09-30 | 2013-04-10 | 飞思卡尔半导体公司 | Methods and apparatus for testing multiple-IC devices |
| CN102968364A (en) * | 2012-11-16 | 2013-03-13 | 中国航天科技集团公司第九研究院第七七一研究所 | Universal debugging interface-based SoC (System on Chip) hardware debugger |
| CN105450251A (en) * | 2015-12-07 | 2016-03-30 | 中国电子科技集团公司第十研究所 | Miniature double-receiving and double-sending universal terminal system level package method |
Non-Patent Citations (3)
| Title |
|---|
| PHILIPPECAUVET: "Chapter 5 - SIP Test Architectures", 《SYSTEM-ON-CHIP TEST ARCHITECTURES》 * |
| 何云强: "《电子线路设计、检验、测试使用手册第4卷》", 31 May 2005 * |
| 杨亮: "一种基于JTAG接口的SIP测试调试系统设计技术", 《半导体检测与设备》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113671360A (en) * | 2020-05-13 | 2021-11-19 | 圣邦微电子（北京）股份有限公司 | I2C interface device testing method and device and I2C interface device |
| CN112466381A (en) * | 2020-11-26 | 2021-03-09 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112466381B (en) * | 2020-11-26 | 2022-09-13 | 西安微电子技术研究所 | Test chip suitable for testing DDR3 physical layer electrical function |
| CN112612264A (en) * | 2020-12-22 | 2021-04-06 | 北京时代民芯科技有限公司 | Serial port self-testing method in CAN bus controller |
| CN114089172A (en) * | 2021-11-22 | 2022-02-25 | 中国电子科技集团公司第五十八研究所 | JTAG debugging method of PCIE IO expansion chip |
| CN114089172B (en) * | 2021-11-22 | 2024-04-09 | 中国电子科技集团公司第五十八研究所 | JTAG debugging method of PCIE IO expansion chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Bleeker et al. | Boundary-scan test: a practical approach | |
| CN109581197A (en) | A kind of SiP encapsulation test macro based on jtag interface | |
| US7574637B2 (en) | Method and apparatus for optimized parallel testing and access of electronic circuits | |
| US8384411B2 (en) | Method and device for measuring inter-chip signals | |
| US8127187B2 (en) | Method and apparatus of ATE IC scan test using FPGA-based system | |
| CN105474178B (en) | Verifying and debugging based on programmable interface | |
| CN113157501B (en) | ATE (automatic test equipment) tester-based AC (alternating current) parameter testing method for microsystem module | |
| CN207965049U (en) | Circuit for TAP signals to be coupled to the jtag interface in integrated antenna package | |
| US20210333326A1 (en) | Switch-Mode Based Interposer Enabling Self-Testing Of An MCM Without Known Good Die | |
| JP2009533691A (en) | Test access port switch | |
| JP4648622B2 (en) | Progressive extended compression mask for dynamic tracing | |
| CN114994509A (en) | Method for designing testability of chip | |
| US20030126533A1 (en) | Testing of circuit modules embedded in an integrated circuit | |
| US20040059971A1 (en) | Device under test interface card with on-board testing | |
| US8621125B2 (en) | System and method of sending and receiving data and commands using the TCK and TMS of IEEE 1149.1 | |
| JP2004178590A (en) | Address range comparator for detecting memory accesses of multi sizes by data matching qualification and full or partial ovrlap | |
| CN103137211B (en) | A kind of emulation test system of NVM build-in self-test | |
| US20210116497A1 (en) | Method of and an Arrangement for Analyzing Manufacturing Defects of Multi-Chip Modules Made Without Known Good Die | |
| CN207601244U (en) | For TAP signals to be coupled to the circuit system of jtag interface | |
| Chou et al. | Hierarchical test integration methodology for 3-D ICs | |
| Rumyantsev et al. | Development of a high-speed multi-target measurement system-on-chip | |
| EP2943803B1 (en) | Microcontroller analysis tools | |
| JP2004156976A (en) | Test method of semiconductor integrated circuit, probe card, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device | |
| Zhao et al. | Research on testing of a microsystem based on SiP | |
| Yu et al. | Evaluation and analysis of domestic ATE based on IC testing application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190405 |
|
| RJ01 | Rejection of invention patent application after publication |