CN100357751C - JTAG module and debug method applying the module - Google Patents
JTAG module and debug method applying the module Download PDFInfo
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- CN100357751C CN100357751C CNB2004100031970A CN200410003197A CN100357751C CN 100357751 C CN100357751 C CN 100357751C CN B2004100031970 A CNB2004100031970 A CN B2004100031970A CN 200410003197 A CN200410003197 A CN 200410003197A CN 100357751 C CN100357751 C CN 100357751C
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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Abstract
The present invention provides a JTAG module, which has the core that a safety module is added in the JTAG module. The safety module receives the instruction of a testing and accessing port (TAP) in the JTAG module, and transfers the received instruction to a corresponding register or a controller of the testing and accessing port. Simultaneously, the present invention also provides a debugging method which applies the JTAG module. When debugging is needed, the safety module is closed first, and then, normal debugging operation is carried out. At the moment, the safety module does not interfere with tests of a chip and a development process. After debugging operation is completed, the safety module is opened, and consequently, the testing and accessing port in a JTAG boundary scan test structure. In other words, a clock and input and output signals in a JTAG interface are closed. Consequently, an attacker can not make use of a JTAG port to obtain data in an SOC chip. Then, the conflict of the testability, the controllability and the security of SOC is solved.
Description
Technical field
The present invention relates to integrated circuit (IC) design and technical field of measurement and test, be meant a kind of JTAG (JointTest Action Group) module especially and use the adjustment method of this module.
Background technology
Test is one of most important link in integrated circuit (IC) design and the production run, generally is divided into two kinds of functional test and structured testings.Wherein, the purpose of functional test is to guarantee that designed operating system chip (SOC) and design idea are complementary, and verifies that promptly can the integrated circuit in the SOC correctly realize the function of design in advance according to technical conditions; Whether the purpose of structured testing is to test each SOC that is produced structurally qualified.
At present, most of CPU nuclear all provides jtag boundary sweep test structure for test, exploitation and emulation.Boundary-scan test technology is connection and the (JTAG of testing action group that is set up by each big semiconductor company (Philips, IBM, Intel etc.) at first, Join Test Action Group) proposed in 1988, nineteen ninety is defined as the standard (IEEE1149.1/2/3) of electronic product Testability Design by IEEE.
Jtag boundary sweep test structure be each I/O pin of chip and inner all require the position of logic testing to increase a boundary scan register (BSR) unit, and all BSR are connected successively, thereby form scan chain.When the chip operate as normal, all BSR unit all are transparent, do not influence the operate as normal of chip; When chip was tested, test data is stored, read in all BSR unit serially according to the instruction that receives, and realizes observation and control to chip internal state and data.
Figure 1 shows that the structural representation of the chip that has the jtag boundary scan chain of prior art.Illustrating in the empty frame is the JTAG module, and each pin of chip to be measured is connected in the core logic of chip to be measured by the boundary scan register in the JTAG module.The JTAG module comprises following four parts: the test access port (TAP) that is used to provide the required various data of test; Be used for selecting (TMS) signal to decipher the test pattern of serial input, make border scanning system enter corresponding test pattern and produce the TAP controller of various control signals; Be used for depositing test instruction by order register (IR) of serving as and the test data register group of forming by bypass register, boundary scan register and data register (TDR) with the shift register of latch.Wherein, include 5 ports in the TAP port, be respectively test clock (TCK) port, test pattern is selected (TMS) port, test data input (TDI) port, test data output (TDO) port and optional test reset signal (TRST) port.
Figure 2 shows that the principle of work synoptic diagram of the chip that has the jtag boundary scan chain of prior art.Test access port controller 240 receives from the steering order in the test access port 250, after the instruction that receives deciphered, the control boundary scan register enters the desired state of steering order, as test mode, simulation status or development status etc., wherein, TMS port acceptance test model selection instruction, TCK port receive clock signal, TRST port acceptance test reset instruction; Order register 230 is used to receive the steering order from TDI port in the test access port 250, and the steering order that receives is deposited; Data register is used to receive the data from TDI port in the test access port 250 in the test data register group 220, and the data that receive are deposited, order register is controlled the data in the data register according to the instruction that receives, and then realizes the control to boundary scan register.Send order register to or send data register to from the signal of TDI port and distinguished according to the signal of TMS port; Boundary scan register in the test data register group 220 are debugged the core logic 210 of chip to be measured, and by boundary scan register with debug results after tested the TDO ports in the access port 250 send external unit to.
Application JTAG module can realize the functional test to chip internal, or by control chip pin realization parameter testing, as test and export the driving force that cushions, electric leakage, AC and DC characteristic such as input threshold values etc. etc., or realize visit inner scanning path, the observability of the internal node that is difficult to visit with raising, or under the situation that does not need additional pin, be used for debugging on the sheet.
Each node of circuit input, output and the SOC chip internal of SOC can be observed and control to above-mentioned design for Measurability easily, is convenient to the tracking exploitation and debugging of test, emulation and the software of system.But but because the existence of Test Design and JTAG; make SOC lose the most basic security; originally the logical circuit that is used for increasing the device inside observability also can be used for checking the SOC internal state information by victim; thereby easy to doly obtain whole programs and data among the SOC by JTAG; this protection for IP is extremely disadvantageous; particularly for crypto chip, the existence of this design for Measurability mode and JTAG makes wherein key and sensitive information have no can say safely.
In order to solve the contradiction of measurability and reliability and security in the above-mentioned design for Measurability, mainly at present adopt following two kinds of methods to solve:
Method one: manual breakage method.This method is to finish in SOC test, and after the firmware among the SOC (FIRMWARE) loaded, the TAP of artificial destruction JTAG module attacked difficulty and realizes protection to the SOC chip by strengthening the assailant.
The defective of said method is: do not destroy because the measurability structure of chip internal and jtag circuit have, thereby can not fundamentally prevent to be attacked.Simultaneously, this method needs production firm to possess special-purpose production equipment, realizes that difficulty is big, the cost height, and when using this method and producing chip in enormous quantities, efficient is very low.
Method two: eliminate the JTAG method.This method is at first to use the chip print that has the JTAG module with emulation and debug function FIRMWARE is developed; after treating that FIRMWARE exploitation debugging is finished; carry out the flow second time again; remove the TAP of JTAG module in the chip, thereby realize the particularly information such as key in the crypto chip of IP in the protection SOC and sensitive information.
The defective of said method is: owing to need flow for the second time, increased production cost, and this method is that later FIRMWARE upgrading exploitation is made troubles.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of JTAG module and use the adjustment method of this module, to solve contradiction at measurability, controllability and the security of SOC.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of JTAG module comprises test access port 460 at least, test access port controller 440, order register 430 and comprise the test data register group 420 of boundary scan register, and this JTAG module further comprises:
The security module 450 that constitutes by register module 451 and logic processing module 452, wherein,
Described register module 451 receives from the chip selection signal of chip core logic 410 to be measured and the data-signal of keying security module, and sends the signal that receives to logic processing module 452;
Described logic processing module 452, access port 460 receptions are from the steering order or the data of external unit after tested, and after according to signal logical process being carried out in the instruction that receives from register module 451, send the steering order after the logical process to test access port controller 440 and order register 430, send the data after the logical process to test data register group 420; Perhaps, reception is from the test result information of test data register group 420, and according to this being received after object information carries out logical process from the signal of register module 451, with the object information after the logical process after tested access port 460 send external unit to.
Preferably, comprise one in the described test access port with upper port, comprise an above logic gate in the described logic processing module, comprise an above register in the described register module, the independent respectively chip selection signal and the data-signal of opening security module that receives from chip core logic to be measured of each register in the described register module, the output signal of each register is an input end of the interior logic gate of counterlogic processing module respectively, the signal of a port in the logic processing module in the corresponding test access port of another input end difference of each logic gate.
Preferably, comprise one in the described test access port, comprise an above logic gate in the described logic processing module, comprise two registers in the described register module with upper port,
Preferably, the signal of a port in the corresponding test access port of input end difference of each logic gate in the described logic processing module, the independent respectively chip selection signal and the data-signal of opening security module that receives from chip core logic to be measured of each register in the described register module, another input end of the effective logic gate of corresponding all high level of the output signal of a register, another input end of the effective logic gate of corresponding all low levels of the output signal of another register.
Preferably, described logic gate is and door that described register is 1 bit register.
A kind of application is the adjustment method of JTAG module as mentioned above, and this method may further comprise the steps:
When needs are debugged chip to be measured, judge at first whether security module is in opening, if, after then in the register of security module, writing the control word of closed safe module, carry out the normal debugging operation, otherwise, directly carry out the normal debugging operation.
Preferably, if security module is in closed condition, this method further comprises: whether the value of judging register in the security module is normal, if, then directly carry out the normal debugging operation, otherwise after in the register of security module, writing the control word of closed safe module, carry out the normal debugging operation again.
Preferably, after chip debugging to be measured was finished, this method further comprised: write the control word of opening security module in the register of security module.
Preferably, one or more ports in the test access port can be opened or close to the described control word that writes in the register of security module simultaneously.
Core of the present invention is to increase by a security module in existing JTAG module, the test access port that the mode of the enough control words of this security module energy is controlled in the JTAG module is opened or is closed, promptly when the debugging exploitation of the test of chip and FIRMWARE, this security module is in closed condition, the test of its nonintervention chip and development process, behind the debugging end-of-development of FIRMWARE, this security module enters opening under the operation of control word, close the test access port in the jtag boundary sweep test structure, promptly seal the clock in the JTAG module, input and or port such as output signal, thereby make the assailant can't utilize the TAP in the JTAG module to obtain the data of SOC chip internal, and then solved measurability at SOC, the contradiction of controllability and security.
The present invention is easy to realization, and with low cost.Compare with the manual breakage method, method of the present invention realizes reliable, and the efficient height; Compare with eliminating the JTAG method, need not to carry out the flow second time, reduced cost.And, can be at any time easily to FIRMWARE or the chip debugging operations of upgrading.
Description of drawings
Figure 1 shows that the structural representation of the chip that has the jtag boundary scan chain of prior art;
Figure 2 shows that the principle of work synoptic diagram of the chip that has the jtag boundary scan chain of prior art;
Figure 3 shows that the structural representation that has the chip of jtag boundary scan chain of the present invention;
Figure 4 shows that and use the principle of work synoptic diagram that has the chip of jtag boundary scan chain of the present invention;
Figure 5 shows that the principle assumption diagram of the security module of using the embodiment of the invention one;
Figure 6 shows that the principle assumption diagram of the security module of using the embodiment of the invention two;
Figure 7 shows that and use open and close JTAG module testing access port processing flow chart of the present invention.
Embodiment
For making technical scheme of the present invention clearer, again the present invention is described in further details below in conjunction with drawings and the specific embodiments.
Thinking of the present invention is: increase by a security module in existing JTAG module, this security module is under the control of control word, open or close the test access port in the JTAG module, promptly when the debugging exploitation of chip testing and FIRMWARE, control this security module and be in closed condition, make the test and the development process of its nonintervention chip, when chip testing finishes, after the debugging of FIRMWARE exploitation finished, control this security module by control word and enter opening, close the test access port in the jtag boundary sweep test structure, promptly seal the clock in the JTAG module, input and or port such as output signal, thereby make the assailant can't utilize the TAP in the JTAG module to obtain the data of SOC chip internal, and then solved measurability at SOC, the contradiction of controllability and security.
Figure 3 shows that the structural representation that has the chip of jtag boundary scan chain of the present invention.Illustrating in the empty frame is to use the JTAG module that has security module of the present invention, and each pin of chip to be measured is connected in the core logic of chip to be measured by the boundary scan register in the JTAG module.At this moment, all instructions or data that the TAP port in this JTAG module receives need just can send to relevant register or controller by security module.Like this, under the situation that security module is closed, instruction or signal from the TAP port can normally arrive relevant register or controller, promptly can carry out normal debugging to chip by the jtag boundary scan chain, also can obtain information such as chip internal state, data simultaneously; Under the situation that security module is opened, instruction or data from the TAP port can't reach relevant register or controller, promptly can not carry out debugging operations to chip, thereby also just can not obtain information such as chip internal state, data by the jtag boundary scan chain by the jtag boundary scan chain.
Figure 4 shows that and use the chip operation principle schematic that has the jtag boundary scan chain of the present invention.Further comprise the security module 450 that constitutes by register module 451 and logic processing module 452 in the JTAG module of the present invention, wherein, register module 451 in the security module 450, reception is from the chip selection signal of chip core logic 410 to be measured and open and close the signal of security module data, and sends the signal that receives to logic processing module 452; Logic processing module 452 in the security module 450, the steering order or the data that receive of access port 460 after tested, and after according to signal the command signal that receives being carried out logical process from register module 451, send the steering order after logical process to test access port controller 460 and order register 430, send the data after logical process to test data register group 420; Perhaps, the test result information that logic processing module 452 in the security module 450 receives from test data register group 420, and according to signal this is received object information and carries out logical process from register module 451, and with the object information after the logical process after tested access port 460 send external unit to.
After the steering order that test access port controller 440 receives from security module, the instruction that receives is deciphered, the control boundary scan register enters the desired state of steering order, as test mode, simulation status or development status etc., wherein, instruction from the Inner_TMS port of security module is the test pattern selection instruction, from the Inner_TCK port of security module be clock signal, be the test reset instruction from the Inner_TRST port of security module; Order register 430 is used to receive the steering order from the Inner_TDI port of security module, and the steering order that receives is deposited; Data register is used to receive the data from the Inner_TDI port of security module in the test data register group 420, and the data that receive are deposited, order register is controlled the data in the data register according to the instruction that receives, and then realizes the control to boundary scan register.Send order register to or send data register to from the signal of Inner_TDI port and distinguished according to the signal of Inner_TMS port; Boundary scan register in the test data register group 420 is debugged the core logic 410 of chip to be measured, and send debug results to security module through the Inner_TDO port by boundary scan register, send external unit by security module to by the TDO port again.Like this, under the control of security module, realize opening or closing the purpose of test access port.
Figure 5 shows that the principle assumption diagram of the security module of using the embodiment of the invention one.In the present embodiment, comprise an above logic gate in the logic processing module in the security module, comprise an above register in the register module in the security module.An input end of each logic gate is an interior port of corresponding test access port respectively, the output terminal of each logic gate is corresponding with the signal of the test access port of this logic gate of input, be TMS, TDI, TDO, the input end of the respectively corresponding logic gate of TCK and TRST port, correspondingly, the output terminal of each logic gate is followed successively by Inner_TMS, Inner_TDI, Inner_TDO, Inner_TCK and Inner_TRST, another input end of each logic gate is the output terminal of the interior register of corresponding register module respectively, and each register independently receives from the chip selection signal of chip core logic to be measured respectively and opens the data-signal of security module.
Referring to Fig. 5, suppose that the logic gate in the logic processing module in the safety chip is " with door " and disjunction gate, register in the register module is 1 bit register, and chip to be measured is during good debug, TMS in the test access port, TDI, TDO, it is high that TCK and TRST port are respectively, low, low, high, high level is effective, then when debugging chip to be measured, write data-signal 1 in the register in security module respectively, 0,0,1,1, make the Inner_TMS of security module output, Inner_TDI, Inner_TDO, Inner_TCK and Inner_TRST signal respectively with TMS, TDI, TDO, TCK and TRST signal keep level signal same, it is the closed safe module, like this, security module to the test access port of JTAG module without any influence.When the debugging to chip to be measured finishes, write data- signal 0,1,1,0,0 in the register in security module respectively, make Inner_TMS, Inner_TDI, Inner_TDO, Inner_TCK and the Inner_TRST signal of security module output keep opposite level signal with the operate as normal signal of TMS, TDI, TDO, TCK and TRST respectively, promptly open security module, like this, make outside TMS, TDI, TDO, TCK and TRST signal no longer work, and then arrived the purpose of the visit test port of sealing JTAG module.
Figure 6 shows that the principle assumption diagram of the security module of using the embodiment of the invention two.In the present embodiment, comprise an above logic gate in the logic processing module in the security module, comprise two registers in the register module in the security module.An input end of each logic gate is an interior port of corresponding test access port respectively, the output terminal of each logic gate is corresponding with the signal of the test access port of this logic gate of input, be TMS, TDI, TDO, TCK and TRST port be an input end of counterlogic door respectively, correspondingly, the output terminal of each logic gate is followed successively by Inner_TMS, Inner_TDI, Inner_TDO, Inner_TCK and Inner_TRST, another input end of the effective port of corresponding all low levels of the output signal of register place logic gate in the register module, another input end of the effective port of corresponding all high level of the output signal of another register place logic gate promptly allows all need another input port of logic gate of same level signal to accept the control of same register; Each register is independent respectively to be received from the chip selection signal of chip core logic to be measured and the data-signal of unlatching security module.
Referring to Fig. 6, in the present embodiment, suppose that the logic gate in the logic processing module in the safety chip is " with door " and disjunction gate, register in the register module is 1 bit register, and chip to be measured is during good debug, TMS in the test access port, TDI, TDO, it is high that TCK and TRST port are respectively, low, low, high, high level is effective, then when debugging chip to be measured, write data-signal 0 in the register in security module respectively, 1, make the Inner_TMS of security module output, Inner_TDI, Inner_TDO, Inner_TCK and Inner_TRST signal respectively with TMS, TDI, TDO, TCK and TRST signal keep level signal same, it is the closed safe module, like this, security module to the test access port of JTAG module without any influence.When the debugging to chip to be measured finishes, write data-signal 1,0 in the register in security module respectively, make Inner_TMS, Inner_TDI, Inner_ TDO, Inner_TCK and the Inner_TRST signal of security module output keep opposite level signal with the operate as normal signal of TMS, TDI, TDO, TCK and TRST respectively, promptly open security module, outside TMS, TDI, TDO, TCK and TRST signal are no longer worked, and then arrived the purpose of the visit test port of sealing JTAG module.
The above only is two kinds of embodiments of safety chip, but be not limited to this, security module can have multiple implementation, reaches simultaneously the purpose of opening, closing one or more ports in the test access port in the JTAG module as long as guarantee by write different control words in register.For example, register module in the security module can also can be used the multidigit register with 1 bit register, this register can be controlled many signal line, also can only control wherein 1 signal line, as long as reach the purpose that realizes opening, closing one or more ports in the JTAG build-in test access port by software.
Figure 7 shows that and use open and close JTAG module testing access port processing flow chart of the present invention.
So far, this flow process guaranteed under the security module closing state, and the test access port of JTAG can operate as normal, promptly can obtain information such as chip internal state, data by the test access port of JTAG; Under the state that security module is opened, the test access port in the JTAG is unavailable, promptly can not obtain information such as chip internal state, data by the test access port of JTAG.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind of JTAG module, at least comprise test access port (460), test access port controller (440), order register (430) and comprise the test data register group (420) of boundary scan register is characterized in that this JTAG module further comprises:
By the security module (450) of register module (451) and logic processing module (452) formation, wherein,
Described register module (451) receives from the chip selection signal of chip core logic to be measured (410) and the data-signal of keying security module, and sends the signal that receives to logic processing module (452);
Described logic processing module (452), access port (460) receives steering order or the data from external unit after tested, and after according to signal logical process being carried out in the instruction that receives from register module (451), send the steering order after the logical process to test access port controller (440) and order register (430), send the data after the logical process to test data register group (420); Perhaps, reception is from the test result information of test data register group (420), and according to this being received after object information carries out logical process from the signal of register module (451), with the object information after the logical process after tested access port (460) send external unit to.
2, according to the described module of claim 1, it is characterized in that, comprise one in the described test access port, comprise an above logic gate in the described logic processing module, comprise an above register in the described register module with upper port,
The independent respectively chip selection signal and the data-signal of opening security module that receives from chip core logic to be measured of each register in the described register module, the output signal of each register is an input end of the interior logic gate of counterlogic processing module respectively, the signal of a port in the logic processing module in the corresponding test access port of another input end difference of each logic gate.
3, according to the described module of claim 1, it is characterized in that, comprise one in the described test access port, comprise an above logic gate in the described logic processing module, comprise two registers in the described register module with upper port,
The signal of a port in the corresponding test access port of input end difference of each logic gate in the described logic processing module, the independent respectively chip selection signal and the data-signal of opening security module that receives from chip core logic to be measured of each register in the described register module, another input end of the effective logic gate of corresponding all high level of the output signal of a register, another input end of the effective logic gate of corresponding all low levels of the output signal of another register.
According to claim 2 or 3 described modules, it is characterized in that 4, described logic gate is and door that described register is 1 bit register.
5, a kind of application rights requires the adjustment method of 1 described JTAG module, it is characterized in that, this method may further comprise the steps:
When needs are debugged chip to be measured, judge at first whether security module is in opening, if, after then in the register of security module, writing the control word of closed safe module, carry out the normal debugging operation, otherwise, directly carry out the normal debugging operation.
6, method according to claim 5, it is characterized in that, if security module is in closed condition, this method further comprises: whether the value of judging register in the security module is normal, if, then directly carry out the normal debugging operation, otherwise after in the register of security module, writing the control word of closed safe module, carry out the normal debugging operation again.
According to claim 5 or 6 described methods, it is characterized in that 7, after chip debugging to be measured was finished, this method further comprised: write the control word of opening security module in the register of security module.
8, method according to claim 7 is characterized in that, one or more ports in the test access port can be opened or close to the described control word that writes in the register of security module simultaneously.
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| CN109425824A (en) * | 2017-08-28 | 2019-03-05 | 意法半导体国际有限公司 | The serial and concurrent test access port selection of combination in jtag interface |
| CN109425824B (en) * | 2017-08-28 | 2021-02-12 | 意法半导体国际有限公司 | Combined serial and parallel test access port selection in JTAG interfaces |
| US11041905B2 (en) | 2017-08-28 | 2021-06-22 | Stmicroelectronics International N.V. | Combinatorial serial and parallel test access port selection in a JTAG interface |
| CN109581197A (en) * | 2018-12-28 | 2019-04-05 | 中国电子科技集团公司第五十八研究所 | A kind of SiP encapsulation test macro based on jtag interface |
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