CN102340304B - TAP (test access port) interface optimization circuit - Google Patents
TAP (test access port) interface optimization circuit Download PDFInfo
- Publication number
- CN102340304B CN102340304B CN 201110254920 CN201110254920A CN102340304B CN 102340304 B CN102340304 B CN 102340304B CN 201110254920 CN201110254920 CN 201110254920 CN 201110254920 A CN201110254920 A CN 201110254920A CN 102340304 B CN102340304 B CN 102340304B
- Authority
- CN
- China
- Prior art keywords
- signal
- circuit
- register
- output
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a TAP (test access port) interface optimization circuit. The number of PINs of a conventional TAP interface is decreased from four or five to two or three on the premise of not changing test clock frequency before optimization, thereby realizing functions of a boundary scanning circuit in a target IC (integrated circuit) by utilizing a JTAG (joint test action group) controller. The TAP interface optimization circuit is applied to the realization of functions for testing, simulating, debugging and the like over the target IC in the boundary scanning circuit requiring serial operations, and is more applicable to circuits such as a microcontroller, a microprocessor, mixed signal equipment and the like with limited PIN numbers.
Description
Technical field
The present invention relates to a kind of TAP interface optimized circuit, can be used in the various circuit with standard boundary-scan function, especially for the limited circuit of the PIN pin numbers such as microcontroller, microprocessor, mixed signal device, have more applicability.
Background technology
Traditional boundary scan chain substantially all is to realize on the basis of IEEE 1149.1 standards, some circuit of realizing based on standards such as IEEE 1149.4, IEEE 1149.5, IEEE 1149.6, IEEE 1532 also are as basis, the boundary scan chain that is applied to different field and differs from one another take IEEE 1149.1 standards.They all adopt the TAP interface of four or five PIN leg structures, comprise test data output signal TDO, test mode select signal TMS, test clock signals TCK, input signal of test data TDI and optional test reset signal (asynchronous reset signal) TRST.As shown in Figure 1, jtag controller is by the access of five PIN pin realizations to boundary scan chain among the target IC.
But, because most systems is now all integrated a plurality of IC, and strict size restrictions arranged, therefore, must as much as possible reduce PIN pin and signal control line number in order to reach the purpose that adds other function PIN pin and (perhaps) reduction packaging cost, finally help the designer to reach the design object of target IC volume external form.And the TAP interface circuit of existing four or five PIN leg structures structurally can not meet the demands.
So far, there has been some TAP (Test Access Port) interface optimisation technique in industry.New boundary scan standard IEEE 1149.7 issued the second season in 2009, it has realized PIN pin number is compressed to two purpose by a kind of very complicated mode on the basis of IEEE 1149.1 standards, but, interface conversion and control circuit are too complicated, hardware spending is larger, the ancillary equipment that also needs in case of necessity to introduce specific function could be realized being difficult for the purpose of testing and debugging meeting the demands in performance fully.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art part, a kind of new relatively simple TAP interface optimized circuit is provided, so that do not change optimize before under the prerequisite of testing clock frequency, four of traditional TAP interface or five PIN pin are compressed to two or three.
Technical solution of the present invention is:
A kind of TAP interface optimized circuit comprises transmitting terminal 214 and receiving terminal 215, described transmitting terminal 214 comprise again jtag controller 102, the first register 201, the second register 202, with door 203 and first bidirectional transmission circuit 204; Described receiving terminal 215 comprises that again boundary scan chain 103, electrify restoration circuit 210, reset synchronous circuit 211, control logic 212, the second bidirectional transmission circuit 205, first catch register 206, second and catch register 207, first and upgrade register 208, second and upgrade register 209, TAP state machine 213 and pull-up circuit 216;
In receiving terminal 215, move on the test mode select signal of pull-up circuit 216 with input and send into reset synchronous circuit 211 and second after the high level and catch register 207; Electrify restoration circuit 210 provides the electrification reset pulse for reset synchronous circuit 211, reset synchronous circuit 211 also receives the synchronous reset signal that TAP state machine 213 provides, and the synchronous reset signal of TAP state machine 213 outputs also inputs to simultaneously control logic 212, first and upgrades the set end that the reset terminal and second of register 208 upgrades register 209; Reset synchronous circuit 211 output enable signals are also exported asynchronous reset signal to TAP state machine 213 and boundary scan chain 103 simultaneously to control logic 212;
The second bidirectional transmission circuit 205 receives the enable signal of TAP state machine 213 outputs and the test data output signal of boundary scan chain 103, and the output signal of the second bidirectional transmission circuit 205 is sent into first and caught register 206; First catches register 206 and the second output of catching register 207 is connected respectively to first and upgrades the data input pin that register 208 and second upgrades register 209; Control logic 212 output refresh clock signals upgrade register 208 and second to first and upgrade register 209, also export simultaneously test clock signals to boundary scan chain 103; First upgrades output signal that register 208 and second upgrades register 209 respectively as input signal of test data and the test mode select signal of boundary scan chain 103.
Described the first bidirectional transmission circuit 204 comprises buffer 601, resistance 605 and the first voltage comparator circuit 603, and described the second bidirectional transmission circuit 205 comprises tristate buffer 602, resistance 606 and second voltage comparison circuit 604;
The input signal of the first bidirectional transmission circuit 204 is sent in buffer 601 and the first voltage comparator circuit 603 simultaneously, the output of buffer 601 is through being connected to the first voltage comparator circuit 603 after the resistance 605, send in the resistance 606 and second voltage comparison circuit 604 in the second bidirectional transmission circuit 205 as the exchanges data signal simultaneously; The first voltage comparator circuit 603 is according to the inverted signal of the input signal of the described output of exchanges data signal deciding high level, low level or the first bidirectional transmission circuit 204; The other end of resistance 606 is connected to the output of tristate buffer 602, the ternary control end of tristate buffer 602 connects the enable signal of input, the input of tristate buffer 602 connects the test data output signal from boundary scan chain 103, and second voltage comparison circuit 604 is according to the inverted signal of the test data output signal of the output of exchanges data signal deciding high level, low level or described boundary scan chain 103.
Described resistance 605 is identical with the resistance of resistance 606, and described buffer 601 is identical with the driving force of tristate buffer 602.
Described control logic 212 comprise with door 302, with the door 303 and or the door 301; External timing signal is input to the input with door 303, and its inverted signal is input to the input with door 302; The synchronous reset signal of the enable signal that reset synchronous circuit 211 provides and TAP state machine 213 outputs is input to or two inputs of door 301 simultaneously, or door 301 output be connected to simultaneously two with door as two with inputs, be the refresh clock signal with the output of door 302, be test clock signals to boundary scan chain 103 with the output of door 303.
Described reset synchronous circuit 211 comprises state machine 501 and register 502;
Four inputs of state machine 501 are respectively through pull-up circuit 216 and process test mode select signal, electrification reset pulse, external timing signal and synchronous reset signal afterwards; The inverted signal of external timing signal also is input to the clock end of register 502, and the electrification reset pulse also is input to the reset terminal of register 502; One of state machine 501 is output as asynchronous reset signal, and another output CE is by the enable signal of register 502 outputs as control logic 212;
The state transitions of described state machine 501 is closed:
Externally under the effect of clock signal, if the electrification reset pulse effectively or synchronous reset signal when being low level, state machine 501 gets the hang of 504 by state 503; Get the hang of after 504, if when the test mode select signal after described process pull-up circuit 216 processing is low level, get the hang of 505 by state 504; Get the hang of after 505, if when described test mode select signal after processing through pull-up circuit 216 is low level, get the hang of 506, on the contrary return state 504 then; Get the hang of after 506, if when the test mode select signal after described process pull-up circuit 216 processing is low level, return state 504, on the contrary then get the hang of 507; Get the hang of after 507, if when described test mode select signal after processing through pull-up circuit 216 is high level, get the hang of 508, on the contrary return state 504 then; Get the hang of after 508, if synchronous reset signal is high level, then enter into initial condition, namely state 503;
Described state 503 is initial condition, that is: the CE of state machine 501 outputs is low level, when synchronous reset signal is high level, continues to keep initial condition constant;
Described state 504: receive described through the test mode select signal after pull-up circuit 216 processing, the asynchronous reset signal of output is low level, when the test mode select signal after described process pull-up circuit 216 is processed is high level, continue to keep this state;
Described state 505: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 506: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 507: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 508: the CE of state machine 501 outputs is high level, and the asynchronous reset signal of output is high level, when synchronous reset signal is low level, continues to keep this state constant.
The present invention's beneficial effect compared with prior art is:
1, the present invention with compare based on the designed TAP interface circuit structure of IEEE 1149.1 standards, the present invention is compressed to two or three (when transmitting terminal 214 and receiving terminal 215 have clock module that clock is provided separately with the PIN pin, peripheral clock signal control line of the present invention can omit, this moment, the PIN pin number of TAP interface was two), PIN pin number and signal control line have been reduced, help the designer to reach the purpose of design of target IC volume external form, reduce packaging cost, perhaps also can be chosen in other functional pin of adding in the situation that does not change the volume external form.
2, testing clock frequency used in the present invention (external timing signal) equates with the testing clock frequency of the common boundaries scanning circuit of not optimizing all the time, so the present invention program is on not impact of test rate, can be not slack-off.
Description of drawings
Fig. 1 is a kind of traditional 5-PIN structure jtag circuit implementation schematic diagram;
Fig. 2 is the TAP interface optimized circuit implementation schematic diagram that the present invention proposes;
Fig. 3 is the composition schematic diagram of control logic of the present invention;
Fig. 4 is the state transition diagram of the TAP state machine of IEEE 1149.1 prescribed by standard;
Fig. 5 A is the composition schematic diagram of reset synchronous circuit of the present invention;
Fig. 5 B is the state transition diagram of state machine among Fig. 5 A;
Fig. 6 is the schematic diagram of bidirectional transmission circuit of the present invention;
Fig. 7 is the operation principle schematic diagram of voltage comparator circuit among Fig. 6;
Fig. 8 is the partial data flow graph of the designed circuit of the present invention.
Embodiment
Figure 1 shows that the circuit implementing scheme schematic diagram that traditional use TAP controller conducts interviews to the boundary scan chain among the target IC.This circuit is comprised of clock source 101, jtag controller 102, boundary scan chain 103, TAP interface 104.Wherein, clock source 101 provides external timing signal CLK for jtag controller 102, and has generated the required test clock signals TCK of boundary scan chain among the target IC 103 after processing through jtag controller 102.The control that jtag controller 102 uses five JTAG control lines (TDO, TMS, TCK, TDI and TRST) to realize boundary scan chain 103 among the target IC by TAP interface 104.
Figure 2 shows that the TAP interface optimized circuit implementation schematic diagram that the present invention proposes, comprise transmitting terminal 214 and receiving terminal 215, the two links to each other by three bars control lines (exchanges data signal DIO, test mode select signal TMS and external timing signal CLK).External timing signal CLK can be driven by the clock source that provides in transmitting terminal 214 or the receiving terminal 215, also can be driven by external clock reference.When transmitting terminal 214 and receiving terminal 215 have clock module that clock is provided separately, peripheral clock signal clk of the present invention can omit, this moment, the TAP interface PIN pin number of target IC just can be compressed into two, and only residues is according to exchange signal DIO and PIN pin corresponding to test mode select signal TMS.
Described transmitting terminal 214 comprise again jtag controller 102, the first register 201, the second register 202, with door 203 and first bidirectional transmission circuit 204; Described receiving terminal 215 comprises that again boundary scan chain 103, electrify restoration circuit 210, reset synchronous circuit 211, control logic 212, the second bidirectional transmission circuit 205, first catch register 206, second and catch register 207, first and upgrade register 208, second and upgrade register 209, TAP state machine 213 and pull-up circuit 216.
When asynchronous reset signal TRST_0 is low level, the output of the first register 201 and the second register 202 be reset to respectively 0 and set be 1, test clock signals TCK_0 perseverance is low level; When asynchronous reset signal TRST_0 is high level, no longer affect the first register 201, the second register 202 and with the output of door 203.The first bidirectional transmission circuit 204 has the function of bidirectional data exchange and transmission, and test data can be from the input of DOUT end, and DIO holds output, also can be from the input of DIO end, and TDI_0 holds output, and these two kinds of behaviors can be carried out simultaneously.From figure, also can find out, when asynchronous reset signal TRST_0 is high level, test clock signals TCK_0 has identical clock frequency with external timing signal CLK, and the first register 201 and the second register 202 are exported one group of new test data output signal TDO_0 and test mode select signal TMS_0 in each external timing signal CLK clock cycle.
In receiving terminal 215, move on the test mode select signal TMS_IN of pull-up circuit 216 with input and send into reset synchronous circuit 211 and second after the high level and catch register 207; Electrify restoration circuit 210 provides electrification reset pulse POR for reset synchronous circuit 211, reset synchronous circuit 211 also receives the synchronous reset signal RST that TAP state machine 213 provides, and the synchronous reset signal RST of TAP state machine 213 outputs also inputs to simultaneously control logic 212, first and upgrades the set end that the reset terminal and second of register 208 upgrades register 209; Reset synchronous circuit 211 output enable signal CENA also export asynchronous reset signal TRST to TAP state machine 213 and boundary scan chain 103 simultaneously to control logic 212.
The second bidirectional transmission circuit 205 receives the enable signal OENA of TAP state machine 213 outputs and the test data output signal TDO of boundary scan chain 103, and the output signal DIN of the second bidirectional transmission circuit 205 sends into first and catches register 206; First catches register 206 and the second output of catching register 207 is connected respectively to first and upgrades the data input pin that register 208 and second upgrades register 209; Control logic 212 output refresh clock signal UCK upgrade register 208 and second to first and upgrade register 209, also export simultaneously test clock signals TCK to boundary scan chain 103; First upgrades output signal that register 208 and second upgrades register 209 respectively as input signal of test data TDI and the test mode select signal TMS of boundary scan chain 103.
When target IC powers on, electrify restoration circuit 210 can provide an of short duration electrification reset pulse POR, be used for initial reset synchronous circuit 211, so that asynchronous reset signal TRST becomes low level, thereby make TAP state machine 213 be in TEST LOGIC RESET state shown in Figure 4.This function also can realize by other means, replaces such as the reset signal that can utilize target IC to provide.The Main Function of reset synchronous circuit 211 has two, and the one, when target IC was operated in the system that does not have a transmitting terminal 214, it can remain on reset mode with receiving terminal 215; The 2nd, when having transmitting terminal 214 in the system, it can play the synchronous effect of data, thus the correctness of determination data conversion and transmission.Control logic 212 is upgraded register 208 and second and is upgraded register 209 and refresh clock signal UCK is provided and provides test clock signals TCK for boundary scan chain 103 for first.The working method of the second bidirectional transmission circuit 205 and the first bidirectional transmission circuit 204 are similar, when the enable signal OENA of TAP state machine 213 outputs is high level, data can be from the input of DIO end, DIN holds output, also can be from the input of TDO end, DIO holds output, and these two kinds of behaviors can be carried out simultaneously; When enable signal OENA was low level, data only can be from the input of DIO end, and DIN holds output.First catch register 206 and second catch register 207 with outside clock signal clk as clock signal, catch in real time from the test mode select signal TMS_IN of transmitting terminal 214 output with from the signal DIN of the second bidirectional transmission circuit 205 outputs.First upgrade register 208 and second upgrade register 209 with refresh clock signal UCK as clock signal, and when asynchronous reset signal TRST is low level, their output be reset to respectively 0 and set be 1.The Functional Design of TAP state machine 213 is fully according to IEEE 1149.1 standards, the test mode select signal TMS of its input and test clock signals TCK are used for the state conversion of TAP state machine 213, and asynchronous reset signal TRST is used for the asynchronous reset of TAP state machine 213; The synchronous reset signal RST of output is low level when TEST LOGIC RESET state shown in Figure 4 only; Enable signal OENA becomes high level when TAP state machine 213 is in SHIFT-DR shown in Figure 4 or SHIFT-IR state.The test mode select signal TMS_IN of receiving terminal 215 can be pulled to high level by pull-up circuit 216 in the output driving situation that is not sent out end 214, otherwise identical with the output signal TMS of the second register 202 in the transmitting terminal 214.
Figure 3 shows that the composition schematic diagram of Fig. 2 control logic 212, comprise with door 302, with the door 303 and or the door 301.External timing signal CLK is input to the input with door 303, and its inverted signal is input to the input with door 302; The synchronous reset signal RST of the enable signal CENA that reset synchronous circuit 211 provides and TAP state machine 213 outputs is input to or two inputs of door 301 simultaneously, or the output OR of door 301 is connected to door 302 and 303 simultaneously as two inputs with door, be refresh clock signal UCK with the output of door 302, be test clock signals TCK to boundary scan chain 103 with the output of door 303.When OR was low level, test clock signals TCK and refresh clock signal UCK perseverance were low level; When OR is high level, test clock signals TCK has identical clock frequency with refresh clock signal UCK with external timing signal CLK, and test clock signals TCK and external timing signal CLK Complete Synchronization, refresh clock signal UCK and external timing signal CLK differ the clock cycle half.
Fig. 5 A is depicted as the composition schematic diagram of reset synchronous circuit 211 of the present invention, comprises state machine 501 and register 502.Four inputs of state machine 501 are respectively through pull-up circuit 216 and process test mode select signal TMS_IN, electrification reset pulse POR, external timing signal CLK and synchronous reset signal RST afterwards; The inverted signal of external timing signal CLK also is input to the clock end of register 502, and electrification reset pulse POR also is input to the reset terminal of register 502; One of state machine 501 is output as asynchronous reset signal TRST, and another output CE is by the enable signal CENA of register 502 outputs as control logic 212.The state machine 501 externally rising edge of clock signal clk carries out the state conversion, and register 502 triggers output by the trailing edge of CLK; The asynchronous reset signal TRST of state machine 501 outputs is used for the asynchronous reset of TAP state machine 213 and boundary scan chain 103.When electrification reset pulse POR was effective, the output of register 502 was reset to 0.
Fig. 5 B has described the state transitions relation of state machine 501 among Fig. 5 A.The state transitions of described state machine 501 is closed:
Externally under the effect of clock signal clk, if electrification reset pulse POR effectively or synchronous reset signal RST when being low level, state machine 501 gets the hang of 504 by state 503; Get the hang of after 504, if when the test mode select signal TMS_IN after described process pull-up circuit 216 processing are low level, get the hang of 505 by state 504; Get the hang of after 505, if when described test mode select signal TMS_IN after processing through pull-up circuit 216 are low level, get the hang of 506, on the contrary return state 504 then; Get the hang of after 506, if when the test mode select signal TMS_IN after described process pull-up circuit 216 processing are low level, return state 504, on the contrary then get the hang of 507; Get the hang of after 507, if when described test mode select signal TMS_IN after processing through pull-up circuit 216 are high level, get the hang of 508, on the contrary return state 504 then; Get the hang of after 508, if synchronous reset signal RST is high level, then enter into initial condition, namely state 503.
State 504: receive described through the test mode select signal TMS_IN after pull-up circuit 216 processing, the asynchronous reset signal TRST of output is low level, when the test mode select signal TMS_IN after described process pull-up circuit 216 is processed are high level, continue to keep this state;
State 505: receive described through the test mode select signal TMS_IN after pull-up circuit 216 processing;
State 506: receive described through the test mode select signal TMS_IN after pull-up circuit 216 processing;
State 507: receive described through the test mode select signal TMS_IN after pull-up circuit 216 processing;
State 508: the CE of state machine 501 outputs is high level, and the asynchronous reset signal TRST of output is high level, when synchronous reset signal RST is low level, continues to keep this state constant.
Based on above design, if electrification reset pulse POR effectively or synchronous reset signal RST when being low level, state machine 501 can get the hang of 504 by state 503, and as long as the test mode select signal TMS_IN of input is high level, state machine 501 will remain on state 504.Mention in the explanation of Fig. 2, when test mode select signal TMS_IN signal was not sent out the output driving of end 214, test mode select signal TMS_IN was pulled to high level by pull-up circuit 216.Therefore, state machine 501 continues to remain on state 504, and asynchronous reset signal TRST continues to remain low level, so receiving terminal 215 will be in the reset mode that is not activated, can not carry out work for target IC.
When transmitting terminal 214 linked to each other with receiving terminal 215 for the first time, because the impact of electrical property, circuit can produce some unknown code stream sequences.If these code streams are not controlled, then can have influence on the correctness of whole circuit working, therefore need to carry out synchronously.Can find out to only have when the test mode select signal TMS_IN of input is the code stream sequence of " 0011 " from Fig. 5 B, state machine 501 just can be transferred to state 508 accurately, and the reset mode of receiving terminal 215 could be removed, and just can be established synchronously.Therefore, the designed state transitions relation of the present invention can filter out the code stream sequence of following three kinds of the unknowns:
(1) " 101 " sequence, state change process is: 504-505-504;
(2) " 10001 " sequence, state change process is: 504-505-506-504;
(3) " 100101 " sequence, state change process is: 504-505-506-507-504.
Obviously, this provides a kind of design philosophy, that is if necessary, can filter out a greater variety of unknown code stream sequences by the behavior of change state machine 501, thereby reduce the probability of circuit synchronization failure.It should be noted that in the list entries " 0011 " last 1 will become first test mode select signal TMS data that offer boundary scan chain 103 and TAP state machine 213, TAP state machine 213 will still be in TEST LOGIC RESET state.
Figure 6 shows that the schematic diagram of bidirectional transmission circuit of the present invention, the first bidirectional transmission circuit 204 comprises that buffer 601, resistance 605 and the first voltage comparator circuit 603, the second bidirectional transmission circuits 205 comprise tristate buffer 602, resistance 606 and second voltage comparison circuit 604.
The input signal DOUT of the first bidirectional transmission circuit 204 sends in buffer 601 and the first voltage comparator circuit 603 simultaneously, the output of buffer 601 is through being connected to the first voltage comparator circuit 603 after the resistance 605, send in the resistance 606 and second voltage comparison circuit 604 in the second bidirectional transmission circuit 205 as exchanges data signal DIO simultaneously; The first voltage comparator circuit 603 determines the inverted signal of the input signal DOUT of output high level, low level or the first bidirectional transmission circuit 204 according to described exchanges data signal DIO; The other end of resistance 606 is connected to the output of tristate buffer 602, the ternary control end of tristate buffer 602 connects the enable signal OENA of input, the input of tristate buffer 602 connects the test data output signal TDO from boundary scan chain 103, and second voltage comparison circuit 604 determines the inverted signal of the test data output signal TDO of output high level, low level or described boundary scan chain 103 according to exchanges data signal DIO.
Fig. 7 is the operation principle schematic diagram of the first voltage comparator circuit 603 or second voltage comparison circuit 604, and whole circuit is comprised of the first bias current sources 702, the second bias current sources 703, p channel transistor 701, N channel transistor 704, MUX 705, buffer 706 and inverter 707.
Exchanges data signal DIO connects the grid of p channel transistor 701 and N channel transistor 704, is used for its switch of control; M signal S0 and S1 are used for the output of MUX 705 and select; The first bias current sources 702 is between p channel transistor 701 and the ground GND, and the second bias current sources 703 is between N channel transistor 704 and the power vd D; Input signal DOUT or TDO process inverter 707 are connected to an input of MUX 705, and two other input of MUX 705 links to each other with low level LOW with high level HIGH respectively; Output after the output signal of MUX 705 drives through buffer 706, and corresponding the first voltage comparator circuit 603, the first of the input signal of test data TDI_0 of output is caught the corresponding second voltage comparison circuit 604 of input signal DIN of register 206.
When exchanges data signal DIO is high level HIGH, p channel transistor 701 cut-offs, 704 conductings of N channel transistor, respective signal S0 is pulled down to low level LOW by N channel transistor 704, signal S1 is pulled down to low level LOW by the first bias current sources 702, so MUX is output as high level HIGH; When exchanges data signal DIO is low level LOW, p channel transistor 701 conductings, 704 cut-offs of N channel transistor, respective signal S0 is pulled to high level HIGH by the second bias current sources 703, signal S1 is pulled to high level HIGH by p channel transistor 704, so MUX is output as low level LOW; When exchanges data signal DIO is intermediate level MID, this means p channel transistor 701 and the 704 equal conductings of N channel transistor, then signal S1 is pulled to high level HIGH by p channel transistor 704, signal S0 is pulled down to low level LOW by N channel transistor 704, so MUX 705 is output as the inverted signal of input signal DOUT (perhaps TDO).
In sum, can draw the logic true value table of bidirectional transmission circuit of the present invention among Fig. 6, as shown in the table.When the enable signal OENA of TAP state machine 213 outputs was high level, the first bidirectional transmission circuit 204 and the second bidirectional transmission circuit 205 were effectively carrying out bidirectional data exchange, and the data of DOUT end and TDI_0 end equate with the data of DIN end and TDO end respectively; When enable signal OENA is low level, only come driving data exchange signal DIO by the data of DOUT end, catch register 206 correct input signal DIN is provided for first.Under underrange " X " the expression current state, data are any.
| DOUT | TDI_0 | DIO | DIN | TDO | OENA |
| LOW | LOW | LOW | LOW | LOW | HIGH |
| LOW | HIGH | MID | LOW | HIGH | HIGH |
| HIGH | LOW | MID | HIGH | LOW | HIGH |
| HIGH | HIGH | HIGH | HIGH | HIGH | HIGH |
| LOW | X | LOW | LOW | X | LOW |
| HIGH | X | HIGH | HIGH | X | LOW |
Fig. 8 has described a complete workflow of circuit shown in Figure 2 take the immigration of test data as example.The sequence of test data of jtag controller 102 outputs is " D
N-1D
N-2D
1D
0".Under underrange " X " the expression current state, data are any.
In 1001 time periods, transmitting terminal 214 is connected with receiving terminal also and is connected, and exchanges data signal DIO is not also by external drive, and receiving terminal 215 has been initialised, and state machine 501 is in state 504, and asynchronous reset signal TRST is low level.Suppose that this moment, external timing signal CLK was driven by certain clock source, the rising edge of clock signal clk externally then, the driving perseverance that the test mode select signal TMS_IN of output is subject to pull-up circuit 216 is high level, even test mode select signal TMS_IN has of short duration saltus step, state machine 501 still can be got back to state 504.
In 1002 time periods, transmitting terminal 214 is connected with receiving terminal and is just begun to connect physical connection, and because the impact of electrical property can generate some unknown code stream sequences, these code stream sequences can stop synchronous finishing smoothly.Therefore, since the time period 1003, only has continuous input " 0011 " sequence 1004, state machine 501 just can accurately be transferred to state 508, the CE of asynchronous reset signal TRST and state machine 501 outputs becomes high level, the reset mode of receiving terminal 215 is disengaged, and half CLK is after the clock cycle, and test clock signals TCK and refresh clock signal UCK just can begin effectively.
When TAP state machine 213 was converted to the SHIFT-DR state from TEST LOGIC RESET state, enable signal OENA began effectively, and boundary scan chain 103 begins to move into sequence of test data 1005 " D
N-1D
N-2D
1D
0", simultaneously from TDO end output sequence 1006 " D
N-1' D
N-2' ... D
1' D
0' ".The test data that can find out boundary scan chain 103 input than the output of jtag controller 102 late two CLK clock cycle, but the actual clock frequency of using is identical with the clock frequency of external timing signal CLK in the whole test process, and the designed TAP interface optimized circuit of the present invention does not exert an influence to the testing clock frequency before optimizing.
After operation is finished, if need to continue test, need not again to carry out synchronously.With defined in IEEE 1149.1 standards, input continuously the test mode select signal TMS of five high level, TAP state machine 213 can return to TEST LOGIC RESET state again.
Claims (6)
1. a TAP interface optimized circuit is characterized in that comprising transmitting terminal 214 and receiving terminal 215, described transmitting terminal 214 comprise again jtag controller 102, the first register 201, the second register 202, with door 203 and first bidirectional transmission circuit 204; Described receiving terminal 215 comprises that again boundary scan chain 103, electrify restoration circuit 210, reset synchronous circuit 211, control logic 212, the second bidirectional transmission circuit 205, first catch register 206, second and catch register 207, first and upgrade register 208, second and upgrade register 209, TAP state machine 213 and pull-up circuit 216;
Jtag controller 102 output test data output signal and test mode select signal, successively as the input of the data of the first register 201 and the second register 202, the asynchronous reset signal of jtag controller 102 outputs be connected to simultaneously the reset terminal of the first register 201, the second register 202 the set end and with an input of door 203; The clock end, second that external timing signal is connected to the clock end of clock end, second register 202 of the first register 201 simultaneously, catch register 206 with another input, first of door 203 is caught clock end, reset synchronous circuit 211 and the control logic 212 of register 207; With the output of door 203 test clock signals as jtag controller 102; The output of the first register 201 is as the input signal of the first bidirectional transmission circuit 204, exchanges data and transmission between 204 realizations of the first bidirectional transmission circuit and the second bidirectional transmission circuit 205, the output signal of the first bidirectional transmission circuit 204 is as the input signal of test data of jtag controller 102; The output signal of the second register 202 is exported to receiving terminal 215 as the test mode select signal of described transmitting terminal 214;
In receiving terminal 215, move on the test mode select signal of pull-up circuit 216 with input and send into reset synchronous circuit 211 and second after the high level and catch register 207; Electrify restoration circuit 210 provides the electrification reset pulse for reset synchronous circuit 211, reset synchronous circuit 211 also receives the synchronous reset signal that TAP state machine 213 provides, and the synchronous reset signal of TAP state machine 213 outputs also inputs to simultaneously control logic 212, first and upgrades the set end that the reset terminal and second of register 208 upgrades register 209; Reset synchronous circuit 211 output enable signals are also exported asynchronous reset signal to TAP state machine 213 and boundary scan chain 103 simultaneously to control logic 212;
The second bidirectional transmission circuit 205 receives the enable signal of TAP state machine 213 outputs and the test data output signal of boundary scan chain 103, and the output signal of the second bidirectional transmission circuit 205 is sent into first and caught register 206; First catches register 206 and the second output of catching register 207 is connected respectively to first and upgrades the data input pin that register 208 and second upgrades register 209; Control logic 212 output refresh clock signals upgrade register 208 and second to first and upgrade register 209, also export simultaneously test clock signals to boundary scan chain 103; First upgrades output signal that register 208 and second upgrades register 209 respectively as input signal of test data and the test mode select signal of boundary scan chain 103.
2. a kind of TAP interface optimized circuit according to claim 1, it is characterized in that: described the first bidirectional transmission circuit 204 comprises buffer 601, resistance 605 and the first voltage comparator circuit 603, and described the second bidirectional transmission circuit 205 comprises tristate buffer 602, resistance 606 and second voltage comparison circuit 604;
The input signal of the first bidirectional transmission circuit 204 is sent in buffer 601 and the first voltage comparator circuit 603 simultaneously, the output of buffer 601 is through being connected to the first voltage comparator circuit 603 after the resistance 605, send in the resistance 606 and second voltage comparison circuit 604 in the second bidirectional transmission circuit 205 as the exchanges data signal simultaneously; The first voltage comparator circuit 603 is according to the inverted signal of the input signal of the described output of exchanges data signal deciding high level, low level or the first bidirectional transmission circuit 204; The other end of resistance 606 is connected to the output of tristate buffer 602, the ternary control end of tristate buffer 602 connects the enable signal of input, the input of tristate buffer 602 connects the test data output signal from boundary scan chain 103, and second voltage comparison circuit 604 is according to the inverted signal of the test data output signal of the output of exchanges data signal deciding high level, low level or described boundary scan chain 103.
3. a kind of TAP interface optimized circuit according to claim 2, it is characterized in that: described resistance 605 is identical with the resistance of resistance 606, and described buffer 601 is identical with the driving force of tristate buffer 602.
4. a kind of TAP interface optimized circuit according to claim 1 is characterized in that: described control logic 212 comprise with door 302, with door 303 and or door 301; External timing signal is input to the input with door 303, and its inverted signal is input to the input with door 302; The synchronous reset signal of the enable signal that reset synchronous circuit 211 provides and TAP state machine 213 outputs is input to or two inputs of door 301 simultaneously, or door 301 output be connected to simultaneously two with door as two with inputs, be the refresh clock signal with the output of door 302, be test clock signals to boundary scan chain 103 with the output of door 303.
5. a kind of TAP interface optimized circuit according to claim 1, it is characterized in that: described reset synchronous circuit 211 comprises state machine 501 and register 502;
Four inputs of state machine 501 are respectively through pull-up circuit 216 and process test mode select signal, electrification reset pulse, external timing signal and synchronous reset signal afterwards; The inverted signal of external timing signal also is input to the clock end of register 502, and the electrification reset pulse also is input to the reset terminal of register 502; One of state machine 501 is output as asynchronous reset signal, and another output CE is by the enable signal of register 502 outputs as control logic 212.
6. a kind of TAP interface optimized circuit according to claim 5 is characterized in that: the state transitions of described state machine 501 is closed and is:
Externally under the effect of clock signal, if the electrification reset pulse effectively or synchronous reset signal when being low level, state machine 501 gets the hang of 504 by state 503; Get the hang of after 504, if when the test mode select signal after described process pull-up circuit 216 processing is low level, get the hang of 505 by state 504; Get the hang of after 505, if when described test mode select signal after processing through pull-up circuit 216 is low level, get the hang of 506, on the contrary return state 504 then; Get the hang of after 506, if when the test mode select signal after described process pull-up circuit 216 processing is low level, return state 504, on the contrary then get the hang of 507; Get the hang of after 507, if when described test mode select signal after processing through pull-up circuit 216 is high level, get the hang of 508, on the contrary return state 504 then; Get the hang of after 508, if synchronous reset signal is high level, then enter into initial condition, namely state 503;
Described state 503 is initial condition, that is: the CE of state machine 501 outputs is low level, when synchronous reset signal is high level, continues to keep initial condition constant;
Described state 504: receive described through the test mode select signal after pull-up circuit 216 processing, the asynchronous reset signal of output is low level, when the test mode select signal after described process pull-up circuit 216 is processed is high level, continue to keep this state;
Described state 505: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 506: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 507: receive described through the test mode select signal after pull-up circuit 216 processing;
Described state 508: the CE of state machine 501 outputs is high level, and the asynchronous reset signal of output is high level, when synchronous reset signal is low level, continues to keep this state constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110254920 CN102340304B (en) | 2011-08-31 | 2011-08-31 | TAP (test access port) interface optimization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110254920 CN102340304B (en) | 2011-08-31 | 2011-08-31 | TAP (test access port) interface optimization circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102340304A CN102340304A (en) | 2012-02-01 |
| CN102340304B true CN102340304B (en) | 2013-05-01 |
Family
ID=45515841
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110254920 Active CN102340304B (en) | 2011-08-31 | 2011-08-31 | TAP (test access port) interface optimization circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102340304B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9564877B2 (en) | 2014-04-11 | 2017-02-07 | Qualcomm Incorporated | Reset scheme for scan chains with asynchronous reset signals |
| CN108872837A (en) * | 2018-08-28 | 2018-11-23 | 长鑫存储技术有限公司 | Data compression circuit, memory, arrangement for testing integrated circuit and test method |
| US10866283B2 (en) * | 2018-11-29 | 2020-12-15 | Nxp B.V. | Test system with embedded tester |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661385A (en) * | 2004-02-26 | 2005-08-31 | 联想(北京)有限公司 | JTAG module and debug method applying the module |
| CN1965242A (en) * | 2004-06-08 | 2007-05-16 | 西门子公司 | Test method and test device for testing an integrated circuit |
-
2011
- 2011-08-31 CN CN 201110254920 patent/CN102340304B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1661385A (en) * | 2004-02-26 | 2005-08-31 | 联想(北京)有限公司 | JTAG module and debug method applying the module |
| CN1965242A (en) * | 2004-06-08 | 2007-05-16 | 西门子公司 | Test method and test device for testing an integrated circuit |
Non-Patent Citations (4)
| Title |
|---|
| 一种基于JTAG TAP的嵌入式调试接口设计;张卫新;《微计算机应用》;20021130;第23卷(第6期);第330-334页 * |
| 基于边界扫描技术的TAP接口研究;王让定等;《计算机工程》;20030331;第29卷(第3期);第139-141页 * |
| 张卫新.一种基于JTAG TAP的嵌入式调试接口设计.《微计算机应用》.2002,第23卷(第6期),第330-334页. |
| 王让定等.基于边界扫描技术的TAP接口研究.《计算机工程》.2003,第29卷(第3期),第139-141页. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102340304A (en) | 2012-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103091620B (en) | Optimization method of capturing power consumption in scan test | |
| JP5687668B2 (en) | Optimized JTAG interface | |
| CN103576082B (en) | Low-power sweep trigger unit | |
| CN101363900B (en) | Method for testing FPGA device | |
| US8479068B2 (en) | Decoded register outputs enabling test clock to selected asynchronous domains | |
| CN102419415B (en) | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit | |
| US9322876B2 (en) | Control test point for timing stability during scan capture | |
| US7890826B2 (en) | Method and apparatus for test of asynchronous pipelines | |
| CN102340304B (en) | TAP (test access port) interface optimization circuit | |
| US8145963B2 (en) | Semiconductor integrated circuit device and delay fault testing method thereof | |
| Shi et al. | Test generation for ultra-high-speed asynchronous pipelines | |
| US20140298126A1 (en) | Latch circuit, scan test circuit and latch circuit control method | |
| US20170146600A1 (en) | Scan Logic For Circuit Designs With Latches And Flip-Flops | |
| CN101533069B (en) | Combined scanning unit of integrated circuit | |
| US10338930B2 (en) | Dual-rail delay insensitive asynchronous logic processor with single-rail scan shift enable | |
| US11017135B2 (en) | Scan logic for circuit designs with latches and flip-flops | |
| CN109188250B (en) | Chip IO port circuit capable of carrying out static parameter test | |
| CN106201950B (en) | Method for SOC asynchronous clock domain signal interface | |
| CN105320594A (en) | Clock driving switching method for verification environment | |
| CN202217036U (en) | Distributed test node chain and multi-chain system thereof | |
| CN219552990U (en) | Circuit structure of prototype verification platform | |
| CN103077051B (en) | load processing circuit, method and system | |
| CN104467809B (en) | Six edge triggered flip flops of odd and even data selector composition | |
| JP2014089055A (en) | Semiconductor device and test method thereof | |
| Conover | Asynchronous vs. Synchronous Microporcessors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |