CN101470170B - JTAG link test method and apparatus - Google Patents
JTAG link test method and apparatus Download PDFInfo
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- CN101470170B CN101470170B CN2008100975970A CN200810097597A CN101470170B CN 101470170 B CN101470170 B CN 101470170B CN 2008100975970 A CN2008100975970 A CN 2008100975970A CN 200810097597 A CN200810097597 A CN 200810097597A CN 101470170 B CN101470170 B CN 101470170B
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Abstract
The invention provides a test method of JTAG link and a device therefore. The test method for JATG link comprises: implanting a group of full-1 instruction codes into a JATG link; according to the full-1 instruction codes, selecting a 1-bit shift data register to connect each object device, and using the shift data register to capture the data of each object device; implanting the test vector containing characteristic codes into the shift data register via the JTAG link; using the shift data register to output the state of object device captured by each shift data register and the characteristic code in the test vector; according to the state of the object device output by the shift data register and the characteristic code, judging if the JTAG link is normal. The technical scheme can simply and easily test JTAG links.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of JTAG link test method and device thereof.
Background technology
In order to solve the test problem of VLSI (very large scale integrated circuit), by JTAG (JETA G, JointTest Action Group) boundary scan technique has been proposed, it is by being present in the boundary scan cell (BSC between device input and output pin and the kernel circuitry, Boundary Scan Description) device and peripheral circuit thereof are tested, thereby the controllability and the observability of device have been improved, solved the above-mentioned test problem that the modern electronic technology development brings, can finish test more conveniently by the circuit board of modern device assembling.Common this test is called as the JTAG link test.
The JTAG link test that prior art provides, the JTAG link that generally all is based on veneer is clear and definite, use then one or more groups and JTAG link one to one test vector test.In JTAG link test process, from the specific test vector of input end input of BSC, the test result of observing the output terminal output of BSC then judges according to described test result whether this JTAG link is normal.
Therefore, in carrying out the invention process, the inventor finds that there are the following problems at least in the prior art: in the technical scheme that prior art provides, for the different JTAG link of test, need the different test vector of input, therefore the JTAG link test method that provides of prior art does not possess versatility, uses inconvenience.
Summary of the invention
The technical matters that the embodiment of the invention will solve provides a kind of JTAG link test method and device thereof, can avoid testing different JTAG links and need import different test vectors.
For solving the problems of the technologies described above, the purpose of the embodiment of the invention is achieved through the following technical solutions:
The embodiment of the invention provides a kind of JTAG link test method, and it comprises:
Insert one group of complete 1 order code to the JTAG link, the length of described complete 1 order code is more than or equal to the quantity of tested device;
According to described complete 1 order code, JTAG link selection 1 bit shift data register is connected on each device under test of JTAG link, and the state of described each device under test of shifted data registers capture;
The test vector that will comprise condition code is inserted in the described shifted data register by the JTAG link, and the length of described test vector is greater than the quantity of tested device;
The state of the device under test of each shifted data registers capture of shifted data register output and the condition code in the test vector;
According to the state and the condition code of the device under test of described shifted data register output, judge whether the JTAG link is normal.
The embodiment of the invention also provides a kind of JTAG link test device, and it comprises:
Input block, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and inserts the test vector that comprises condition code, and the length of described test vector is greater than the quantity of tested device;
Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;
The shifted data register is used for the test vector of inserting according to input block, exports the state of device under test of each shifted data registers capture and the condition code in the test vector;
Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.
The embodiment of the invention also provides a kind of communication facilities, comprises JTAG link test device, is used to test the JTAG link of being made up of device under test, comprising:
Input block is used to insert one group of complete 1 order code, and the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and inserts the test vector that comprises condition code, and the length of described test vector is greater than the quantity of tested device;
Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;
The shifted data register is used for the test vector of inserting according to input block, exports the state of device under test of each shifted data registers capture and the condition code in the test vector;
Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.
The JTAG link test method and the device thereof that provide by the embodiment of the invention, state by each device under test of shifted data registers capture, when the input of shifted data register contains the test vector of condition code, the state of output device under test and the condition code in the test vector, therefore according to the state and the condition code of the device under test of output, can judge whether the JTAG link is normal, identical test vector can be imported for different JTAG links, test can be realized simply and easily the JTAG link.
Description of drawings
Fig. 1 is the process flow diagram of an embodiment of JTAG link test method of the present invention;
Fig. 2 is the structural drawing of an embodiment of JTAG link test device of the present invention.
Embodiment
The embodiment of the invention provides a kind of JTAG link test method and device thereof.For making technical scheme of the present invention clearer, below with reference to accompanying drawing and enumerate embodiment, the present invention is described in more detail.
Please refer to Fig. 1, be the process flow diagram of first embodiment of JTAG link test method of the present invention.In the present embodiment, the device of supposing to be connected on the JTAG link to be tested has three.
The detailed process of JTAG link test comprises:
Step 101: insert one group of complete 1 order code to the JTAG link, the length of described complete 1 order code is more than or equal to the quantity of device to be tested;
Device to be tested is serially connected by jtag interface, forms the JTAG link.Wherein, each device to be tested all is connected on the corresponding jtag interface, and each jtag interface includes four input interfaces and an output interface.Wherein, four input interfaces are respectively: test data input (TDI, TestDate Input), test clock input (TCK, Test Clock Input), test pattern is selected (TMS, TestMode Selection Input), test reset (TRST Test Reset Input), output interface is test data output (TDO, Test Date Output).Data are by TDI pin input jtag interface; Data are exported from jtag interface by the TDO pin; TMS is used for being provided with jtag interface and is in certain specific test pattern; TRST is used for test reset, and low level is effective.
Therefore, the TDI pin in the JTAG link is imported one group complete 1 order code.For all devices, complete 1 order code is the BYPASS instruction.Described complete 1 order code need comprise abundant bit, therefore can guarantee that the order register between the device under test on the JTAG link all can move into the instruction of 1 bit, the length of described complete 1 order code is greater than or equals the quantity of device to be tested.
Step 102: according to described complete 1 order code, select to be connected the TDI of each jtag interface in the JTAG link and 1 shifted data register between the TDO, and the state of each device under test of shifted data registers capture of described selection;
Be connected with the boundary scan register unit between the input and output pin of tested device, usually, the boundary scan register unit comprises data register and order register.Order register is used for realizing the control to the data register, and data register is used for realizing observation and the control to the input and output of chip.For the input pin of tested device, can by the data register that is attached thereto data load in this input pin; For the output pin of tested device, also can catch output signal on (Capture) this output pin by the data register that is attached thereto.
In the present embodiment, can select to have the shifted data register of 1 bit by the BYPASS instruction, therefore by insert one group of sufficiently long complete 1 order code to the JTAG link, be equivalent to select 1 shifted data register, be connected between the TDI and TDO of each jtag interface in the JTAG link.The state that described 1 shifted data register is caught in the data shift process is 0 bit.
Step 103: insert the test vector that comprises condition code by the described shifted data register of JTAG chain road direction, the length of described test vector is greater than the quantity of tested device;
Described condition code can be for comprising one or more bits of non-complete 0 arbitrarily.If the bit number that condition code comprised is greater than number of devices to be tested, described test vector can only comprise condition code, also can comprise other bits; If the bit number that is comprised of condition code, can add other bits less than number of devices to be tested up to the length of the test vector quantity greater than tested device in test vector.Described test vector is arranged in the mode of moving to right.For example in the present embodiment, device to be tested has three, supposes that condition code is 0101, then import the JTAG link test vector can for ... 1110101 ... 0000101 or the like.
Described test vector is under the driving of TCK, by in one one bit serial of TDI interface input JTAG link, that is to say the clock period of each TCK, all imports bit in the bit test vector to the TDI interface.Owing to connected 11 shifted data register between the TDI of each jtag interface and the TDO, therefore described test vector is under the control of TCK, finally will be input in the described shifted data register, and the state of the tested device that described shifted data register is caught and condition code also can be by one one bit serial outputs of TDO interface by the TDI interface.
Step 104: the shifted data register outputs test result, and described test result comprises the state of device under test of each shifted data registers capture and the condition code in the test vector;
Specifically describe the process of input of JTAG link test vector and test data output below for example:
In the present embodiment, have three devices to be tested to be connected on the JTAG link, suppose that the test vector of inserting the JTAG link is ... 1110101, wherein 0101 is condition code.
Behind complete 1 instruction input JTAG link, the state that shift register is caught from each tested device is 0.
When the triggering of first clock period of TCK when arriving, first bit 1 of test vector is imported in the shifted data register of first tested device correspondence by the TDI interface, simultaneously, in the shifted data register of the 3rd tested device correspondence 0 is from TDO interface output JTAG link, therefore TCK is in first clock period, and the bit of exporting from the JTAG link is 0;
When the triggering of second clock period of TCK when arriving, second bit 0 of test vector imported in the shifted data register of first tested device correspondence by the TDI interface, simultaneously, 1 of original storage is displaced in the shifted data register of second tested device correspondence in first tested device, 0 of original storage is displaced in the shifted data register of second tested device correspondence in second tested device, in the shifted data register of the 3rd tested device correspondence 0 is from TDO interface output JTAG link, therefore TCK is in second clock period, is 0 from the bit of JTAG link output;
When the triggering of the 3rd clock period of TCK when arriving, the 3rd bit 1 of test vector imported in the shifted data register of first tested device correspondence by the TDI interface, simultaneously, 0 of original storage is displaced in the shifted data register of second tested device correspondence in first tested device, 1 of original storage is displaced in the shifted data register of the 3rd tested device correspondence in second tested device, in the shifted data register of the 3rd tested device correspondence 0 is from TDO interface output JTAG link, therefore TCK is in the 3rd clock period, is 0 from the bit of JTAG link output;
When the triggering of the 4th clock period of TCK when arriving, the 4th bit 0 of test vector imported in the shifted data register of first tested device correspondence by the TDI interface, simultaneously, 1 of original storage is displaced in the shifted data register of second tested device correspondence in first tested device, 0 of original storage is displaced in the shifted data register of the 3rd tested device correspondence in second tested device, in the shifted data register of the 3rd tested device correspondence 1 is from TDO interface output JTAG link, therefore TCK is in the 3rd clock period, is 1 from the bit of JTAG link output;
By that analogy, through 7 TCK week after dates, the bit of exporting from the JTAG link is followed successively by 0101000.
Step 105:, judge whether the JTAG link is normal according to the state and the condition code of the device under test of described shifted data register output.
For example, comprise complete condition code in the test result of output, and be offset 30, on the link when to be measured device count be 3, therefore can judge that tested device is all normal.
Please refer to Fig. 2, be the structural drawing of an embodiment of JTAG link test device of the present invention.Described JTAG link test device comprises input block 21, order register 22, shifted data register 23, test clock input block 24, judging unit 25.
Described input block 21, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and inserts the test vector that comprises condition code, and the length of described test vector is greater than the quantity of tested device.
Described condition code can be for comprising one or more bits of non-complete 0 arbitrarily.If the bit number that condition code comprised is greater than number of devices to be tested, described test vector can only comprise condition code, also can comprise other bits; If the bit number that is comprised of condition code, can add other bits less than number of devices to be tested up to the length of the test vector quantity greater than tested device in test vector.
Described selected cell 22 is used for complete 1 order code according to described receiving element 21 receptions, selects 1 shifted data register to be connected on each device under test.
For all devices, complete 1 order code is the BYPASS instruction.Can select to have the shifted data register of 1 bit by the BYPASS instruction, so, be equivalent to select 1 shifted data register, be connected on the jtag test device by insert one group of sufficiently long complete 1 order code to the jtag test device.
Described shifted data register 23 is used for the test vector of inserting according to input block, exports the state of device under test of each shifted data registers capture and the condition code in the test vector.
Described test clock unit 24 is used to produce test clock; Described input block 21 is specially first input block, be used to insert one group of complete 1 order code, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and according to described test clock, import bit in the described test vector successively to described shifted data register 23, described shifted data register 23 is specially the first shifted data register, be used for according to described test clock, the state and the condition code of device under test are exported successively as test result.
Behind complete 1 instruction input JTAG link, the state that shift register is caught from each tested device is 0.
Described judging unit 25 is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.
In addition, the embodiment of the invention also provides a kind of communication facilities, comprises JTAG link test device, is used to test the JTAG link of being made up of device under test.
Described JTAG link test device comprises:
Input block is used to insert one group of complete 1 order code, and the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and inserts the test vector that comprises condition code, and the length of described test vector is greater than the quantity of tested device;
Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;
The shifted data register is used for catching the state of each shifted data register device under test and the condition code of test vector;
Judging unit is used for state and condition code according to the device under test of shifted data registers capture, judges whether the JTAG link is normal.
Described JTAG link test device can further include:
The test clock unit is used to produce test clock;
Described input block is specially first receiving element, be used to insert one group of complete 1 order code, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and the test clock that produces according to described test clock unit, import bit in the described test vector successively to described shifted data register
Described shifted data register is specially the first shifted data register, is further used for according to described test clock, exports the state and the condition code of device under test successively.
The JTAG link test method and the device thereof that provide by the embodiment of the invention, state by each device under test of shifted data registers capture, when the input of shifted data register contains the test vector of condition code, the state of output device under test and the condition code in the test vector, therefore according to the state and the condition code of the device under test of output, can judge whether the JTAG link is normal, identical test vector can be imported for different JTAG links, test can be realized simply and easily the JTAG link.
More than a kind of JTAG link test method provided by the present invention and device thereof are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used to help to understand disclosed technical scheme; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (4)
1. a JTAG JTAG link test method is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:
Insert one group of complete 1 order code to the JTAG link, the length of described complete 1 order code is more than or equal to the quantity of tested device;
According to described complete 1 order code, JTAG link selection 1 bit shift data register is connected on each device under test of JTAG link, and the state of described each device under test of shifted data registers capture;
According to test clock, the bit that will comprise in the test vector of condition code is imported in each shifted data register successively by the JTAG link, and the length of described test vector is greater than the quantity of tested device;
According to test clock, export the state of the device under test of catching in each shifted data register and the condition code in the test vector successively;
According to the state and the condition code of the device under test of described shifted data register output, judge whether the JTAG link is normal.
2. JTAG link test method according to claim 1 is characterized in that, described condition code is to comprise one or more bits of non-complete 0 arbitrarily.
3. a JTAG JTAG link test device is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:
The test clock unit is used to produce test clock;
Input block, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and the test clock that produces according to described test clock unit, import bit in the described test vector successively to the shifted data register;
Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;
The shifted data register is used for the test vector of inserting according to input block, according to described test clock, exports the state of device under test of each shifted data registers capture and the condition code in the test vector successively;
Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.
4. a communication facilities comprises JTAG link test device, is used to test the JTAG link of being made up of device under test, it is characterized in that, comprising:
The test clock unit is used to produce test clock;
Input block, be used for inserting one group of complete 1 order code to device to be tested, the length of described complete 1 order code is more than or equal to the quantity of device to be tested, and insert the test vector that comprises condition code, the length of described test vector is greater than the quantity of tested device, and the test clock that produces according to described test clock unit, import bit in the described test vector successively to the shifted data register;
Order register is used for complete 1 order code inserted according to described input block, selects 1 shifted data register to be connected on each device under test;
The shifted data register is used for the test vector of inserting according to input block, according to described test clock, exports the state of device under test of each shifted data registers capture and the condition code in the test vector successively;
Judging unit is used for state and condition code according to the device under test of shifted data register output, judges whether the JTAG link is normal.
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| CN102645609B (en) * | 2012-03-30 | 2014-12-10 | 上海斐讯数据通信技术有限公司 | Joint test action group (JTAG) link circuit test device and test method of JTAG chain circuit test device |
| CN104237666B (en) * | 2013-06-21 | 2017-05-03 | 京微雅格（北京）科技有限公司 | Method for testing devices in series connection chain of joint test action group |
| CN112994927B (en) * | 2021-02-04 | 2022-11-25 | 海光信息技术股份有限公司 | Retrieval method and retrieval device for daisy chain topology |
| CN114360632A (en) * | 2022-03-18 | 2022-04-15 | 中国科学院微电子研究所 | Solid state disk chip detection method and device comprising solid state disk main control chip |
| CN117007950A (en) * | 2022-04-29 | 2023-11-07 | 华为技术有限公司 | Method, apparatus, device, medium and program product for configuring IJTAG circuitry |
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