CN1763556A - Automatic connecting system for JTAG chain and implementing method thereof - Google Patents
Automatic connecting system for JTAG chain and implementing method thereof Download PDFInfo
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- CN1763556A CN1763556A CN 200410086421 CN200410086421A CN1763556A CN 1763556 A CN1763556 A CN 1763556A CN 200410086421 CN200410086421 CN 200410086421 CN 200410086421 A CN200410086421 A CN 200410086421A CN 1763556 A CN1763556 A CN 1763556A
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Abstract
The invention discloses a JTAG chain self-connection system, which comprises the following parts: JTAG controller, at least one JTAG interfaces, at least one JTAG device, CPU, logical control unit and self-connection to control JTAG chain, wherein the TDI pin of JTAG device and TDO pin of JTAG interface connect the input and output end of logical control unit separately; both TCK pin and TMS pin of JTAG interface connect the corresponding pins of JTAG device; the control signal switches the input and output end of logical control unit by CPU through control interface.
Description
Technical field
The present invention relates to JTAG (JTAG, Joint Test Action Group) interconnection technique, refer to a kind of JTAG chain automatic connecting system and its implementation especially.
Background technology
Along with circuit engineering enters ultra-large integrated (VLSI) epoch, the high complexity of VLSI circuit and multilayer board, surface encapsulation (SMT), wafer scale integrated (WSI) and the utilization of multi-chip module (MCM) technology in Circuits System, to such an extent as to make the physics accessibility of circuit node just progressively weaken disappearance, the testability of circuit and system sharply descends, test expense shared ratio in circuit and system overhead constantly rises, and the conventionally test method is being faced with the test difficulty that is on the rise.Have only the testability that improves circuit, just can make the test problem of circuit obtain simplifying and finally being resolved.Therefore people begin to seek more convenient, mode substitutes traditional detection means more efficiently.
JTAG is a kind of international standard test protocol, is mainly used in the chip internal test.Most now all supports the JTAG agreement than complex devices, and as DSP, FPGA device etc., generally the device with this support JTAG agreement is called the JTAG device.The jtag interface of standard is 4 lines: test pattern is selected input (TMS, Test Mode Select Input), test clock input (TCK, Test Clock Input), test data input (TDI, Test Data Input), test data output (TDO, Test Data Output).
Can carry out structured testing to device easily by the external jtag controller of jtag interface, improve testability.At present, Chang Yong JTAG chain method of attachment has two kinds of the independent chaining of each device and many devices series connection chainings:
As shown in Figure 1, be the method for the independent chaining of each device, promptly each JTAG device connects a jtag interface separately.This method has increased jtag interface undoubtedly, has not only taken the space of printed circuit board (PCB) (PCB), and makes test job complicated more.
Along with the continuous increase of design complexities, require same the number of devices on the JTAG chain also constantly to increase, employing will have the method for the device series connection chaining of jtag interface and also give birth to thereupon.The series connection chaining is that test data input, the output line that will have the chip of jtag interface couple together with the mode of series connection, be that TDI connects the mode that TDO connects TDI, form a scan chain, signal wire TCK, TMS then are that the mode by parallel connection couples together, and the pcb board at JTAG chain place externally has only a simple jtag interface like this.The method of many device series connection chainings has two kinds of situations.
A kind of method of the chaining of connecting is that the TDO pin of previous JTAG device and the TDI pin of a back JTAG device are together in series by a resistance, the resistance of this series connection is called access resistance, a resistance in parallel between the TDI pin of each JTAG device and the TDO pin, this parallel resistor is called bypass resistance, the TDI pin of jtag interface connects the TDI pin of first JTAG device in the JTAG chain, the TDO pin of jtag interface connects the TDO pin of last JTAG device in the JTAG chain, the TCK of jtag interface, tms signal is parallel to the TCK of each JTAG device in the JTAG chain, the TMS pin.JTAG chain as shown in Figure 2 adopts this method chaining, here be example to change the chaining state of JTAG device 2 in this JTAG chain, specifically describe the chaining way of this method: suppose that JTAG device 1 and JTAG device 3 are connected in the JTAG chain all the time, when needs seal in JTAG device 2 in the chain, welding resistance R 4 and resistance R 5 are not welded resistance R 1, resistance R 2 and resistance R 3 simultaneously; When needs pass devices 2, welding resistance R 2 is not welded resistance R 1, resistance R 3, resistance R 4 and resistance R 5 simultaneously.Can find out that from this method just have bigger hardware modifications workload in case chaining need be changed, dirigibility is not high.
Some device insides are had the JTAG device of bypass register function, can adopt the method for another kind of series connection chaining, as shown in Figure 3, directly adopt the method for series connection chaining to couple together between each JTAG device.Here the function of bypass register is equivalent to bypass resistance, by the setting of CPU to bypass register, and can auto by pass or insert this JTAG device.This method is because the JTAG device that seals in the JTAG chain is just fixing after pcb board completes, be that scan chain is certain, cause this method to have following problem: if a certain JTAG device does not temporarily need or breaks down in this JTAG chain, this JTAG chain will disconnect cisco unity malfunction owing to this JTAG device so.In addition,,, need add the hardware driving circuit,, can cause the very big change of pcb board like this as adopting chip for driving 74HC244 to control signal TCK, TMS etc. in order to guarantee the operate as normal of JTAG chain along with the increase of number of devices in the JTAG chain.Thereby increase a large amount of hardware change work, and influenced the reliability that the JTAG chain connects to a certain extent.
From the method that above JTAG chain connects, have in the prior art that hardware change amount is big, complexity is high, a shortcoming of dirigibility and poor reliability.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of JTAG chain automatic connecting system, and this system architecture is simple, and the chaining that can finish the JTAG chain neatly connects.
Another purpose of the present invention is to provide a kind of JTAG of realization chain from the method that is dynamically connected, and this method can be finished being dynamically connected certainly of JTAG chain in this system.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of JTAG chain automatic connecting system, comprise that at least one is used to connect the jtag interface of jtag controller, above JTAG device, CPU, this system also comprise: logic control element, be used to control being dynamically connected certainly of JTAG chain, its annexation is: the TDI pin of JTAG device and jtag interface links to each other with the I/O end of logic control element respectively with the TDO pin; The TCK pin of jtag interface all links to each other with the corresponding pin of JTAG device with the TMS pin; Control signal is inserted the I/O end of logic control element by control interface by CPU.
Logic control element is programmable logic chip or is combined by logic gates.
Each I/O end of logic control element connects a logic switch respectively.
Jtag interface further comprises: the logic control element that is dynamically connected certainly that at least one is used to connect jtag interface, above JTAG device, a CPU of jtag controller and is used to control the JTAG chain, and its annexation is: the TDI pin of JTAG device and jtag interface links to each other with the I/O end of logic control element respectively with the TDO pin; The TCK pin of jtag interface all links to each other with the corresponding pin of JTAG device with the TMS pin; Control signal is inserted the I/O end of logic control element by control interface by CPU.
A kind of JTAG of realization chain is from the method that is dynamically connected, in logic control element, set up the state of each logic switch and the one-to-one relationship of JTAG combination of devices mode, this method also comprises: logic control element receives the control signal from the outside, and the logic switch of each JTAG device I/O end correspondence is disconnected or closed according to the corresponding relation of the control signal of current reception and setting.This method further comprises: the state of current JTAG device is kept in the status register of logic control element.
The status information of CPU by reading from the logic control element status register determines whether the JTAG device exists.
Whether each JTAG device is connected into the JTAG chain is decided by two logic switches.
As seen from the above technical solutions, the present invention's this JTAG chain automatic connecting system and its implementation, because adopting logic control element controls the state of each device in the JTAG chain, when chaining need be changed, only need CPU to send control signal to logic control element by control interface, logic control element is selected the array mode of required JTAG chain according to control signal, can finish the scan chain chaining automatically and change.This scheme can be finished the chaining connection of JTAG chain automatically neatly and need not hardware is made amendment; If a certain device of access logic control element does not temporarily need or breaks down, can not influence the JTAG chain chaining that other inserts device yet.In addition, this scheme situation that device increases in handling the JTAG chain is more flexible, effective: increase outside not under the situation of hardware circuit, can divide into groups to select part of devices to insert in the JTAG chain, after test is finished, select the device chaining test of part in addition again, because adopt logic control element that the chaining state of device is controlled, it is very flexible that the mode of this part chaining just seems.
Description of drawings
Fig. 1 is the independent JTAG chain of each device of a prior art chaining connection diagram;
Fig. 2 is many devices of prior art JTAG chain series connection chaining connection diagram;
Fig. 3 is the typical JTAG chain of a prior art connection diagram;
Fig. 4 is many devices of the present invention JTAG chain series connection chaining connection diagram;
Fig. 5 is a logic control element logical organization synoptic diagram among Fig. 4;
Fig. 6 is a multimode JTAG chain series connection chaining connection diagram.
Embodiment
Core concept of the present invention is: the TDI pin and the TDO pin of each JTAG device are inserted a logic control element and in logic control element each I/O pin be provided with logic switch, set up one-to-one relationship between the state of each logic switch and the state of JTAG device in the JTAG chain.
Processor CPU writes different control signals by control interface to logic control element, and according to control information and the correct JTAG chain connected mode of corresponding relation selection, achieve a butt joint into the selection of the different JTAG devices of logic control element, thereby realize being dynamically connected certainly of JTAG chain.
For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing preferred embodiment that develops simultaneously, the present invention is described in more detail.
JTAG chain automatic connecting system of the present invention as shown in Figure 4, Fig. 4 is many devices of the present invention JTAG chain series connection chaining connection diagram, this system comprises that at least one is used to connect the jtag interface of jtag controller, above JTAG device, CPU and a logic control element, wherein logic control element 401 can be to adopt programmable chip, as FPGA; Also the circuit that can form by logic gates with control function.Among Fig. 4, the TDI pin of JTAG device 403, JTAG device 404, JTAG device 405 and jtag interface 406 links to each other with each I/O (I/O) pin of logic chip respectively with the TDO pin; Control signal is inserted the I/O pin of logic chip by CPU; The TCK pin of jtag interface 406 all is connected with the TMS pin with the corresponding TCK pin of each JTAG device with the TMS pin.
With reference to Fig. 5, Fig. 5 is the logical organization synoptic diagram of logic control element among Fig. 4, represents the chaining state of the TDI1 pin of JTAG device 403 with logic switch K1: logic switch K1=0, promptly disconnect, and the TDI1 pin of expression JTAG device 403 does not insert the JTAG chain; Logic switch K1=1, promptly closed, expression inserts the JTAG chain.Logic switch K2 represents the chaining state of the TDO1 pin of JTAG device 403: logic switch K2=0, promptly beat end to a1, and logic switch K2 disconnects, and the TDO1 pin of expression JTAG device 403 does not insert the JTAG chain; Logic switch K2=1 promptly beats the end to b1, logic switch K2 closure, and expression inserts the JTAG chain.Table 1 has been listed among the figure logic switch K1 to the state of logic switch K6 and the chaining state relation of JTAG device:
| Logic switch | State | Implication | |
| K1 | 0 | TDI1 does not insert | K1=K2=0, bypass JTAG device 403 K1=K2=1 insert JTAG device 403 |
| 1 | TDI1 inserts | ||
| K2 | 0 | TDO1 does not insert | |
| 1 | TDO1 inserts | ||
| K3 | 0 | TDI2 does not insert | K3=K4=0, bypass JTAG device 404 K3=K4=1 insert JTAG device 404 |
| 1 | TDI2 inserts | ||
| K4 | 0 | TDO2 does not insert | |
| 1 | TDO2 inserts | ||
| K5 | 0 | TDI3 does not insert | K5=K6=0, |
| 1 | TDI3 inserts | ||
| K6 | 0 | TDO3 does not insert | |
| 1 | TDO3 inserts | ||
Table 1
In order to realize being dynamically connected certainly of JTAG chain, the implementation method of this programme is: all the combination chaining modes with each JTAG device deposit in the logic chip in advance, and and control signal between set up mapping relations one by one, can select corresponding JTAG combination of devices mode according to control signal information like this, promptly closed or disconnection respective logic switch.
Among Fig. 4, the JTAG device that inserts logic chip has three, draw easily, its all JTAG chain array modes have eight kinds, can be in advance deposit the array mode of these eight kinds of JTAG devices in logic chip with the form of tabulation, and between the array mode of JTAG device and logic switch state, set up one-to-one relationship.In the present embodiment, inserted three JTAG devices, needed six control signals, be respectively applied for the state of steering logic K switch 1, shown in dotted portion among Fig. 5 to logic switch K6.Present embodiment can select for use 8 control registers to deposit control word, and logic switch K1 can predesignate to the position of control signal in register of logic switch K6, closes such as desired location to be: xxK6K5K4K3K2K1, " x " represent that this position need not.When three JTAG devices of needs are formed a JTAG chain, only need CPU 402 in the register of logic chip, to write the xx111111 control word, in the logic chip tabulation, search and determine the state of JTAG device in the JTAG chain of this control word information correspondence then according to the information of control word, disconnect or closed respective logic switch according to control information at last, thereby realize automatically three JTAG devices are formed a JTAG chain.Here, the concrete operations of finishing according to control information are: with logic switch K1 closure; Logic switch K2 beats to b1 and holds; Logic switch K3 closure; Logic switch K4 beats to b2 and holds; Logic switch K5 closure; Logic switch K6 beats to b3 and holds.
With JTAG device 404 is example, and when this device of needs bypass, CPU writes the xx110011 control word by control interface to the logic chip control register, i.e. presentation logic K switch 1 closure; Logic switch K2 beats to b1 and holds; Logic switch K3 disconnects; Logic switch K4 beats to a2 and holds; Logic switch K5 closure; Logic switch K6 beats to b3 end, according to the one-to-one relationship disconnection or the closed respective switch of the array mode of control signal and JTAG device, so just finishes the bypass of JTAG device 404 again.
In addition, logic control element can be judged whether the JTAG device exists, and status information be write in the status register of logic control element by to the TDI of JTAG device, the detection of TDO pin level.Here, can select for use 8 bit status registers to deposit the JTAG device state, for example: the status information word is in the status register: xxxxx111, represent that three JTAG devices all exist.CPU 402 can read the status information in logic control element 401 status registers by control interface, with identification JTAG device whether in the JTAG chain.If JTAG device 405 does not exist, and this moment, JTAG device 403 and JTAG device 404 existed and all in chain, then the status word that reads of CPU is: xx000011, and the control word in the control register is: xx001111 can check so whether pcb board has neglected loading, leak the situation of weldering, brings convenience for testing or debugging.From here as can be seen, method provided by the invention can not influence the chaining that other inserts the JTAG device of logic chip because neglected loading, the leakage of JTAG device 405 are welded, at this moment, still can realize the various chaining combinations of JTAG device 403 and JTAG device 404 as required.
The JTAG chain that thought of the present invention can be applied to multimode connects, and in this case, can regard JTAG chain automatic connecting system shown in Figure 4 as a module, represents this module with a jtag interface.As shown in Figure 6, jtag interface 1 representation module 1, jtag interface 2 representation modules 2, jtag interface 3 representation modules 3.The TDI pin of these three interfaces and jtag interface 0 links to each other with each I/O (I/O) pin of logic chip respectively with the TDO pin; Control signal is inserted the I/O pin of logic chip by CPU; The TCK pin of jtag interface all is connected with the TMS pin with the corresponding TCK pin of each JTAG device with the TMS pin.All combination chaining modes with each jtag interface deposit in the logic control element in advance, and and control signal between set up mapping relations one by one, can select corresponding JTAG chain array mode according to control information like this.
Like this, can decide which jtag interface to insert the JTAG chain by CPU by the control word that control interface writes the register of logic chip easily and flexibly, which jtag interface be by bypass.For example, CPU sends control word to logic control element: xx001111, promptly be illustrated in bypass module 1 in this JTAG chain, and module 2 and module 3 insert this JTAG chain.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.
Claims (9)
1. JTAG chain automatic connecting system comprises that at least one is used to connect the jtag interface of jtag controller, above JTAG device, CPU; It is characterized in that described system also comprises: logic control element is used to control being dynamically connected certainly of JTAG chain;
The TDI pin of JTAG device and jtag interface links to each other with the I/O end of logic control element respectively with the TDO pin;
The TCK pin of jtag interface all links to each other with the corresponding pin of JTAG device with the TMS pin;
Control signal is inserted the I/O end of logic control element by control interface by CPU.
2. system according to claim 1 is characterized in that: described logic control element is a programmable logic chip.
3. system according to claim 1 is characterized in that: described logic control element is combined by logic gates.
4. system according to claim 1 is characterized in that: each I/O end of described logic control element connects a logic switch respectively.
5. system according to claim 1, it is characterized in that described jtag interface further comprises: the logic control element that is dynamically connected certainly that at least one is used to connect jtag interface, above JTAG device, a CPU of jtag controller and is used to control the JTAG chain;
The TDI pin of JTAG device and jtag interface links to each other with the I/O end of logic control element respectively with the TDO pin;
The TCK pin of jtag interface all links to each other with the corresponding pin of JTAG device with the TMS pin;
Control signal is inserted the I/O end of logic control element by control interface by CPU.
6. realize that the JTAG chain is from the method that is dynamically connected for one kind, it is characterized in that, in logic control element, set up the state of each logic switch and the one-to-one relationship of JTAG combination of devices mode, this method also comprises: logic control element receives the control signal from the outside, and the logic switch of each JTAG device I/O end correspondence is disconnected or closed according to the corresponding relation of the control signal of current reception and setting.
7. method according to claim 6 is characterized in that, this method further comprises: the state of current JTAG device is kept in the status register of logic control element.
8. method according to claim 6 is characterized in that: whether each JTAG device is connected into the JTAG chain is decided by two logic switches.
9. method according to claim 6 is characterized in that: the status information of CPU by from the logic control element status register, reading, determine whether the JTAG device exists.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2008022504A1 (en) * | 2006-08-17 | 2008-02-28 | Huawei Technologies Co., Ltd. | A boundary scan method, system and device |
| CN100435126C (en) * | 2006-12-25 | 2008-11-19 | 中国科学院安徽光学精密机械研究所 | JTAG simulation signal intensifier circuit based on high-speed processor |
| CN100440805C (en) * | 2006-11-06 | 2008-12-03 | 华为技术有限公司 | Method and system for remote-maintaining JTAG device in ATCA |
| CN101782626A (en) * | 2010-03-11 | 2010-07-21 | 苏州国芯科技有限公司 | JTAG port controller |
| CN101183139B (en) * | 2007-11-02 | 2010-12-08 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101470170B (en) * | 2007-12-27 | 2011-04-13 | 华为技术有限公司 | JTAG link test method and apparatus |
| CN102142911A (en) * | 2010-08-31 | 2011-08-03 | 华为技术有限公司 | Communication equipment and communication test method |
| CN101871995B (en) * | 2009-04-23 | 2013-01-02 | 华为技术有限公司 | JTAG (Joint Test Action Group) connection control device and veneer |
| CN104111400A (en) * | 2014-06-19 | 2014-10-22 | 中国航天科工集团第三研究院第八三五七研究所 | JTAG link interconnection method |
| CN105548863A (en) * | 2015-12-29 | 2016-05-04 | 广州慧睿思通信息科技有限公司 | Board-grade multichip joint test action group (JTAG) chain interconnection structure and method |
| CN106326058A (en) * | 2015-06-16 | 2017-01-11 | 中兴通讯股份有限公司 | JTAG debugging method and system of FPGA system |
| CN106918725A (en) * | 2015-12-25 | 2017-07-04 | 英业达科技有限公司 | Tool joint test work group signal concatenates the test circuit plate of circuit design |
| CN109613421A (en) * | 2018-12-21 | 2019-04-12 | 郑州云海信息技术有限公司 | A kind of jtag circuit and measure and control device |
| CN110659037A (en) * | 2019-09-25 | 2020-01-07 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
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| EP0834081B1 (en) * | 1995-06-07 | 2004-02-25 | Samsung Electronics Co., Ltd. | Method and apparatus for testing a megacell in an asic using jtag |
| US5852617A (en) * | 1995-12-08 | 1998-12-22 | Samsung Electronics Co., Ltd. | Jtag testing of buses using plug-in cards with Jtag logic mounted thereon |
| DE69734379T2 (en) * | 1996-08-30 | 2006-07-06 | Texas Instruments Inc., Dallas | Device for testing integrated circuits |
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| US7757139B2 (en) | 2006-08-17 | 2010-07-13 | Huawei Technologies Co., Ltd. | Boundary scan method, system and device |
| WO2008022504A1 (en) * | 2006-08-17 | 2008-02-28 | Huawei Technologies Co., Ltd. | A boundary scan method, system and device |
| CN100440805C (en) * | 2006-11-06 | 2008-12-03 | 华为技术有限公司 | Method and system for remote-maintaining JTAG device in ATCA |
| CN100435126C (en) * | 2006-12-25 | 2008-11-19 | 中国科学院安徽光学精密机械研究所 | JTAG simulation signal intensifier circuit based on high-speed processor |
| CN101183139B (en) * | 2007-11-02 | 2010-12-08 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101470170B (en) * | 2007-12-27 | 2011-04-13 | 华为技术有限公司 | JTAG link test method and apparatus |
| CN101871995B (en) * | 2009-04-23 | 2013-01-02 | 华为技术有限公司 | JTAG (Joint Test Action Group) connection control device and veneer |
| CN101782626A (en) * | 2010-03-11 | 2010-07-21 | 苏州国芯科技有限公司 | JTAG port controller |
| CN102142911A (en) * | 2010-08-31 | 2011-08-03 | 华为技术有限公司 | Communication equipment and communication test method |
| CN104111400A (en) * | 2014-06-19 | 2014-10-22 | 中国航天科工集团第三研究院第八三五七研究所 | JTAG link interconnection method |
| CN106326058A (en) * | 2015-06-16 | 2017-01-11 | 中兴通讯股份有限公司 | JTAG debugging method and system of FPGA system |
| CN106918725A (en) * | 2015-12-25 | 2017-07-04 | 英业达科技有限公司 | Tool joint test work group signal concatenates the test circuit plate of circuit design |
| CN105548863A (en) * | 2015-12-29 | 2016-05-04 | 广州慧睿思通信息科技有限公司 | Board-grade multichip joint test action group (JTAG) chain interconnection structure and method |
| CN105548863B (en) * | 2015-12-29 | 2018-04-17 | 广州慧睿思通信息科技有限公司 | A kind of structure and method of the interconnection of plate level multi-chip JTAG chains |
| CN109613421A (en) * | 2018-12-21 | 2019-04-12 | 郑州云海信息技术有限公司 | A kind of jtag circuit and measure and control device |
| CN110659037A (en) * | 2019-09-25 | 2020-01-07 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| WO2021056401A1 (en) * | 2019-09-25 | 2021-04-01 | 苏州浪潮智能科技有限公司 | Jtag-based burning device |
| US20220317178A1 (en) * | 2019-09-25 | 2022-10-06 | Inspur Suzhou Intelligent Technology Co., Ltd | JTAG-Based Burning Device |
| US11874323B2 (en) * | 2019-09-25 | 2024-01-16 | Inspur Suzhou Intelligent Technology Co., Ltd. | JTAG-based burning device |
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