CN106653096A

CN106653096A - NVM testing reading acceleration method and circuit

Info

Publication number: CN106653096A
Application number: CN201611189047.2A
Authority: CN
Inventors: 王辉
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2016-12-21
Filing date: 2016-12-21
Publication date: 2017-05-10

Abstract

The invention discloses an NVM testing reading acceleration method and circuit. The circuit comprises an address generation logic for generating an NVM address, an NVM for storing information, a comparison data generation logic for generating expected data, a comparison logic for generating a comparison result, a related register and the like. The method comprises the following steps: in an NVM reading-accelerated test, software is adopted for starting, and hardware automatically executes the work of NVM data reading comparison; the hardware automatically performs calculation according to a software configuration value in the NVM, operates the NVM to read out data, simultaneously calculates the expected data, compares the two pieces of data to obtain the comparison result to determine whether to continue the test or not, can continue comparison of the next address if the result is that the two pieces are equal, and stops the test and outputs the result to the software if the result is that the two pieces are unequal, and then the software can perform analysis and debugging in a manner of reading the register. According to the method, NVM reading and data comparison time can be effectively reduced.

Description

A kind of NVM test read-out speed-up methods and circuit

Technical field

The invention belongs to the test design field of IC chip, and in particular to design for Measurability field, by inside Parallel automaticdata compares can be effectively improved the reading of NVM memory and compare data speed.

Background technology

Wafer test is played a very important role in the manufacture process of semiconductor product, is processed from chip and is produced Come, to being sent in End-Customer handss, have passed through repeatedly different tests, it is ensured that the quality of product.And with semiconductor technology Technological progress and design complexities are gradually lifted, and to chip testing cost huge impact is generated.Testing time is elongated, makes core The piece construction cycle lengthens；Testing cost increases, and makes whole chips cost increase sharply.As NVM capacity is also increasing, NVM is tested Time rapid development, digital independent compares as the whether correct main method of NVM data storages is judged, the required time also increases Plus significantly.By the way of data read-out is compared to I/O parallel series output, it reads efficiency to traditional read method Low, the testing time is long, and increases as NVM capacity becomes the big multiple that presents.

In view of the foregoing, need to reduce testing cost as far as possible, therefore optimize the read operation of NVM tests and seem particularly Important, its benefit brought is also evident from, and the testing time can be greatly reduced, so as to reduce testing cost.

By the test basic skills for analyzing NVM, find to have used some features Pattern in a large number in NVM tests, every time The data of reading are regular to be followed, and following several specific test Pattern are included in the testing process of current main flow：Entirely " 0 " Pattern, complete " 1 " Pattern, Checkerboard Pattern, INV Checkerboard Pattern, AA Pattern, 55Pattern, Diagonal Pattern and Erase disturb Pattern.Therefore can be by design one Plant accelerating circuit to improve reading speed.

The content of the invention

It is an object of the invention to serial data reading elapsed time length of the NVM in feature Pattern when solving to test Problem, realizes internal parallel data read-around ratio compared with to improve speed by hardware.

The present invention is a kind of NVM tests read-out speed-up method, and using the implementation of devices at full hardware, detailed technical scheme is retouched State as follows：

The hardware circuit of the present invention includes：One address generating logic, NVM memory, one compare data genaration Logic, data CL Compare Logic, some groups of data register for being used to load information (are used for selection of configuration circuit function and face When data storage, including：Piece selects depositor, initial address register, end address register, Pattern type registers, original Beginning data register and Pattern data refer depositors) and other related combination logiies etc..

Described address generating logic read piece select depositor, initial address register, end address register and The value of Pattern type registers, carries out the control of NVM addresses, and control reads every time the address of data, and this address is write back In initial address register.Address generating logic receives the fail signals of CL Compare Logic output, if fail signals are 1, can be by NVM addresses stop change.When address generating logic judges that it is exported to the address of NVM and the equal value of end address register, Can be then 1 by finish signal outputs, represent that test terminates.

The described NVM memory for storage chip information, receives the control signal that address generating logic is produced, and defeated Go out the data storage of appropriate address.

Described comparison data genaration logic reads Pattern type registers, initial data depositor and receives address The value that logic produces address is generated, the value that this needs compares is calculated, in being stored in Pattern comparison reference depositors.

Described CL Compare Logic is compared data in NVM memory output data and Pattern comparison reference depositors Compared with it is 0 to export fail signals if equal, if unequal, fail signals are 1.

The operation principle of the present invention is as follows：Depositor, initial address register, end address deposit are selected by arranging piece Device, the value of Pattern type registers and initial data depositor, allow address generating logic according to different Pattern types Corresponding address control is produced, is compared data genaration logic and is coordinated address generation logical calculated to go out desired data, be stored in In Pattern data refer depositors.NVM memory receives the address and other control letters produced from address generating logic Number, export corresponding data storage.CL Compare Logic will be counted in NVM memory output data and Pattern data refer depositors According to directly being compared, fail invalidating signals continue to test if equal, until address generating logic produces finish signals.If Effectively, address generating logic stops producing the Wait Orders such as NVM addresses unequal then fail signals.As fail, can be by reading Address date is being analyzed debugging when taking fail in initial address register, Pattern data refers depositor and NVM.

NVM memory read-out speed-up method of the present invention is that chip internal reads comparison method, and energy effectively utilizes NVM are deposited The output maximum bandwidth of reservoir so that testing efficiency is lifted.

NVM memory read-out speed-up method of the present invention, only configuration register and startup are by software control, follow-up institute There is operation to be automatically performed by hardware, realize that High-Speed Automatic reading is compared.

Description of the drawings

Fig. 1 hardware circuit principle figures

Fig. 2 reads to compare flow chart automatically

Analysis debugging flow chart during Fig. 3 fail

Specific embodiment

The specific embodiment of the present invention is described in detail below in conjunction with Figure of description.

As shown in Fig. 1 hardware circuit principle figures of the present invention, 1 represents piece selects depositor, and 2 represent initial address register, 3 generations End of list (EOL) address register, 4 represent Pattern type registers, and 5 represent initial data depositor, and 6 represent address generation patrols Volume, data genaration logic is compared in 7 representatives, and 8 represent the NVM memory of storage information, and 9 represent Pattern data refer depositors, 10 represent CL Compare Logic.

The piece of 1 representative in Fig. 1 selects depositor, and in chip initial power-on, the depositor is in disarmed state, in being elected to During NVM memory, piece selects depositor to be in effective status.

In Fig. 12 represent initial address register, and its effect is the starting of the NVM memory for selecting to carry out reading comparison Address.

In Fig. 13 represent end address register, and its effect is the end of the NVM memory for selecting to carry out reading comparison Address.

In Fig. 14 represent Pattern type registers, and its different numerical value represents more different Pattern.

In Fig. 15 represent initial data depositor, for storing the data of the current comparison of initial address.

In Fig. 16 represent address generating logic, select depositor, initial address register, end address to post by reading piece The value of storage and Pattern type registers, carries out the control of NVM addresses, and control reads every time the address of data.Address generates Logic receives the fail signals of CL Compare Logic output, if fail signals are 1, can stop NVM addresses changing, if fail signals For 0, then may proceed to control NVM addresses.When address generating logic judges that the value of NVM addresses and end address register is equal, then Can be 1 by finish signal outputs, represent that test terminates.

In Fig. 17 representative compares data genaration logic, its read Pattern type registers, initial data depositor and The value that address generating logic produces address is received, the value that this needs compares is calculated, the deposit of Pattern comparison references is stored in In device.

In Fig. 18 represent the NVM memory of storage chip information, receive the control signal that address generating logic is produced, and The data storage of output appropriate address.

In Fig. 19 represent Pattern data refer depositors, produce from comparing data genaration logic every time for storing Comparison data.

In Fig. 1 10 represent CL Compare Logic by data in NVM memory output data and Pattern comparison reference depositors It is compared, it is 0 that fail signals are exported if equal, if unequal, fail signals are 1.

Illustrate in Fig. 2 and started by software, hardware performs the workflow diagram that NVM data is read to compare automatically.From the stream Journey figure can be seen that only initial stage comparison information depositor and (select depositor, initial address register, end address deposit including piece Device, Pattern type registers, initial data depositor) relevant configuration is by software control, and comparison procedure is automatically complete by hardware Into.After the completion of comparing, if result Pass, comparison test next time can be proceeded, if result Fail, can be led to The mode for crossing reading depositor is debugged.

When illustrating fail in Fig. 3, address when initial address register obtains NVM fail is carried out by reading, read Pattern data refer depositors obtain correct desired value, visit again the data that address is stored when NVM reads fail, just Know wrong address and data, debugging can be analyzed.

Claims

1. accelerating circuit is read in a kind of NVM tests, it is characterised in that by address generating logic, compare data genaration logic, data CL Compare Logic, NVM memory, the data register for loading information (select depositor, initial address register, knot including piece Beam address register, Pattern type registers, initial data depositor and Pattern data refer depositors), Yi Jiqi The combination logic of its correlation is constituted, wherein：Described address generating logic reads piece and selects depositor, initial address register, knot The value of beam address register and Pattern type registers, carries out the control of NVM addresses, and control reads every time the address of data, And this address is write back in initial address register；Address generating logic receives the fail signals of CL Compare Logic output, if fail Signal is 1, then can stop NVM addresses changing；Address generating logic judges that it is exported and deposits to the address and end address of NVM Then can be 1 by finish signal outputs when the value of device is equal, represent that test terminates；Realize that internal parallel data is read by hardware Go out and compare to improve speed.

2. a kind of NVM tests read-out speed-up method, the circuit being applied to described in claim 1, it is characterised in that in NVM storages When device reads accelerated test, started by software, hardware performs the data read-out of NVM memory and the work for comparing automatically, leads to Cross parallel data to compare to reach the purpose of acceleration.

3. method according to claim 2, it is characterised in that be used to load the data register of information by described in software sets Device, hardware be automatically performed NVM memory test " address, expected data produce=>Digital independent=>Data compare " process, Judged whether to continue executing with test according to result of the comparison, and result is fed back to into software.

4. method according to claim 2, it is characterised in that：The circuit carries out maximum bit wide to NVM data storages Compare simultaneously.

5. method according to claim 2, it is characterised in that：The circuit can be according to Pattern type registers Value, is tested for different types of Pattern.

6. method according to claim 2, it is characterised in that：It is used to load the data register of information by software arrangements Value, circuit can automatically calculate the comparison expected value of each address.

7. method according to claim 2, it is characterised in that：When data comparative result occurs unequal, circuit keeps working as Front state, and wait at software command；When data comparative result is equal, circuit is automatically performed tests and waits software to be received Comparison instruction next time.

8. method according to claim 2, it is characterised in that：When data comparative result occurs unequal, software can lead to Cross and read the mode of data in data storage and NVM in depositor and be analyzed and debug.